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whitespace/tab cleanup in NativeARM.cpp
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1fb97a5e2d
@ -1210,7 +1210,7 @@ Assembler::asm_cmp(LIns *cond)
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if (c == 0 && cond->isop(LIR_eq)) {
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Register r = findRegFor(lhs, GpRegs);
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TEST(r,r);
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// No 64-bit immediates so fall-back to below
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// No 64-bit immediates so fall-back to below
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}
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else if (!rhs->isQuad()) {
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Register r = getBaseReg(lhs, c, GpRegs);
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@ -1228,9 +1228,9 @@ void
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Assembler::asm_loop(LInsp ins, NInsList& loopJumps)
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{
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(void)ins;
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JMP_long_placeholder(); // jump to SOT
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JMP_long_placeholder(); // jump to SOT
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verbose_only( if (_verbose && _outputCache) { _outputCache->removeLast(); outputf(" jmp SOT"); } );
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loopJumps.add(_nIns);
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#ifdef NJ_VERBOSE
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@ -1255,12 +1255,12 @@ Assembler::asm_fcond(LInsp ins)
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SETE(r);
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asm_fcmp(ins);
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}
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void
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Assembler::asm_cond(LInsp ins)
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{
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// only want certain regs
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LOpcode op = ins->opcode();
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LOpcode op = ins->opcode();
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Register r = prepResultReg(ins, AllowableFlagRegs);
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// SETcc only sets low 8 bits, so extend
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MOVZX8(r,r);
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@ -1288,11 +1288,11 @@ Assembler::asm_cond(LInsp ins)
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SETAE(r);
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asm_cmp(ins);
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}
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void
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Assembler::asm_arith(LInsp ins)
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{
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LOpcode op = ins->opcode();
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LOpcode op = ins->opcode();
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LInsp lhs = ins->oprnd1();
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LInsp rhs = ins->oprnd2();
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@ -1357,7 +1357,7 @@ Assembler::asm_arith(LInsp ins)
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if (op == LIR_add || op == LIR_addp)
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ADDi(rr, c);
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else if (op == LIR_sub)
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SUBi(rr, c);
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SUBi(rr, c);
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else if (op == LIR_and)
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ANDi(rr, c);
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else if (op == LIR_or)
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@ -1377,11 +1377,11 @@ Assembler::asm_arith(LInsp ins)
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if (rr != ra)
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MR(rr,ra);
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}
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void
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Assembler::asm_neg_not(LInsp ins)
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{
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LOpcode op = ins->opcode();
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LOpcode op = ins->opcode();
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Register rr = prepResultReg(ins, GpRegs);
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LIns* lhs = ins->oprnd1();
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@ -1400,11 +1400,11 @@ Assembler::asm_neg_not(LInsp ins)
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if ( rr != ra )
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MR(rr,ra);
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}
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void
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Assembler::asm_ld(LInsp ins)
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{
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LOpcode op = ins->opcode();
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LOpcode op = ins->opcode();
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LIns* base = ins->oprnd1();
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LIns* disp = ins->oprnd2();
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Register rr = prepResultReg(ins, GpRegs);
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@ -1419,7 +1419,7 @@ Assembler::asm_ld(LInsp ins)
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void
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Assembler::asm_cmov(LInsp ins)
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{
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LOpcode op = ins->opcode();
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LOpcode op = ins->opcode();
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LIns* condval = ins->oprnd1();
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NanoAssert(condval->isCmp());
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@ -1430,7 +1430,7 @@ Assembler::asm_cmov(LInsp ins)
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LIns* iffalse = values->oprnd2();
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NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
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const Register rr = prepResultReg(ins, GpRegs);
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// this code assumes that neither LD nor MR nor MRcc set any of the condition flags.
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@ -1439,18 +1439,18 @@ Assembler::asm_cmov(LInsp ins)
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if (op == LIR_cmov) {
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switch (condval->opcode()) {
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// note that these are all opposites...
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case LIR_eq: MRNE(rr, iffalsereg); break;
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case LIR_eq: MRNE(rr, iffalsereg); break;
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case LIR_ov: MRNO(rr, iffalsereg); break;
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case LIR_cs: MRNC(rr, iffalsereg); break;
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case LIR_lt: MRGE(rr, iffalsereg); break;
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case LIR_le: MRG(rr, iffalsereg); break;
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case LIR_gt: MRLE(rr, iffalsereg); break;
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case LIR_ge: MRL(rr, iffalsereg); break;
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case LIR_ult: MRAE(rr, iffalsereg); break;
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case LIR_ule: MRA(rr, iffalsereg); break;
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case LIR_ugt: MRBE(rr, iffalsereg); break;
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case LIR_uge: MRB(rr, iffalsereg); break;
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debug_only( default: NanoAssert(0); break; )
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case LIR_lt: MRGE(rr, iffalsereg); break;
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case LIR_le: MRG(rr, iffalsereg); break;
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case LIR_gt: MRLE(rr, iffalsereg); break;
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case LIR_ge: MRL(rr, iffalsereg); break;
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case LIR_ult: MRAE(rr, iffalsereg); break;
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case LIR_ule: MRA(rr, iffalsereg); break;
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case LIR_ugt: MRBE(rr, iffalsereg); break;
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case LIR_uge: MRB(rr, iffalsereg); break;
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default: debug_only( NanoAssert(0) ); break;
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}
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} else if (op == LIR_qcmov) {
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NanoAssert(0);
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@ -1458,7 +1458,7 @@ Assembler::asm_cmov(LInsp ins)
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/*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
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asm_cmp(condval);
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}
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void
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Assembler::asm_qhi(LInsp ins)
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{
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@ -1561,7 +1561,7 @@ Assembler::asm_quad(LInsp ins)
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if (q == 0.0) {
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// test (int64)0 since -0.0 == 0.0
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SSE_XORPDr(rr, rr);
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} else if (d == 1.0) {
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} else if (d == 1.0) {
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// 1.0 is extremely frequent and worth special-casing!
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static const double k_ONE = 1.0;
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LDSDm(rr, &k_ONE);
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