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Bug 1303690 - Baldr: MIPS: Fix alignment hints after review. r=bbouvier

Browse Source 
---
 .../jit/mips-shared/CodeGenerator-mips-shared.cpp  | 54 +++++++++--------
 js/src/jit/mips-shared/Lowering-mips-shared.cpp    |  2 -
 .../jit/mips-shared/MacroAssembler-mips-shared.cpp | 70 +++++++++++-----------
 .../jit/mips-shared/MacroAssembler-mips-shared.h   |  6 +-
 js/src/jit/mips32/CodeGenerator-mips32.cpp         | 25 ++++++--
 5 files changed, 83 insertions(+), 74 deletions(-)
This commit is contained in:
Heiher 2016-10-10 23:34:54 +08:00
parent 20e13a38d9
commit 22e94edb66
5 changed files with 83 additions and 74 deletions
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54
js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
View File

@ -1926,19 +1926,19 @@ CodeGeneratorMIPSShared::emitWasmLoad(T* lir)
memoryBarrier(mir->barrierBefore());
BaseIndex address(HeapReg, ptr, TimesOne);
if (mir->isUnaligned()) {
Register temp = ToRegister(lir->getTemp(1));
if (isFloat) {
if (byteSize == 4) {
masm.loadUnalignedFloat32(BaseIndex(HeapReg, ptr, TimesOne), temp,
ToFloatRegister(lir->output()));
} else
masm.loadUnalignedDouble(BaseIndex(HeapReg, ptr, TimesOne), temp,
ToFloatRegister(lir->output()));
if (byteSize == 4)
masm.loadUnalignedFloat32(address, temp, ToFloatRegister(lir->output()));
else
masm.loadUnalignedDouble(address, temp, ToFloatRegister(lir->output()));
} else {
masm.ma_load_unaligned(ToRegister(lir->output()), BaseIndex(HeapReg, ptr, TimesOne),
temp, static_cast<LoadStoreSize>(8 * byteSize),
masm.ma_load_unaligned(ToRegister(lir->output()), address, temp,
static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
}
@ -1947,13 +1947,14 @@ CodeGeneratorMIPSShared::emitWasmLoad(T* lir)
}
if (isFloat) {
if (byteSize == 4) {
masm.loadFloat32(BaseIndex(HeapReg, ptr, TimesOne), ToFloatRegister(lir->output()));
} else
masm.loadDouble(BaseIndex(HeapReg, ptr, TimesOne), ToFloatRegister(lir->output()));
if (byteSize == 4)
masm.loadFloat32(address, ToFloatRegister(lir->output()));
else
masm.loadDouble(address, ToFloatRegister(lir->output()));
} else {
masm.ma_load(ToRegister(lir->output()), BaseIndex(HeapReg, ptr, TimesOne),
static_cast<LoadStoreSize>(8 * byteSize), isSigned ? SignExtend : ZeroExtend);
masm.ma_load(ToRegister(lir->output()), address,
static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
}
memoryBarrier(mir->barrierAfter());
@ -2010,19 +2011,19 @@ CodeGeneratorMIPSShared::emitWasmStore(T* lir)
memoryBarrier(mir->barrierBefore());
BaseIndex address(HeapReg, ptr, TimesOne);
if (mir->isUnaligned()) {
Register temp = ToRegister(lir->getTemp(1));
if (isFloat) {
if (byteSize == 4) {
masm.storeUnalignedFloat32(ToFloatRegister(lir->value()), temp,
BaseIndex(HeapReg, ptr, TimesOne));
} else
masm.storeUnalignedDouble(ToFloatRegister(lir->value()), temp,
BaseIndex(HeapReg, ptr, TimesOne));
if (byteSize == 4)
masm.storeUnalignedFloat32(ToFloatRegister(lir->value()), temp, address);
else
masm.storeUnalignedDouble(ToFloatRegister(lir->value()), temp, address);
} else {
masm.ma_store_unaligned(ToRegister(lir->value()), BaseIndex(HeapReg, ptr, TimesOne),
temp, static_cast<LoadStoreSize>(8 * byteSize),
masm.ma_store_unaligned(ToRegister(lir->value()), address, temp,
static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
}
@ -2032,12 +2033,13 @@ CodeGeneratorMIPSShared::emitWasmStore(T* lir)
if (isFloat) {
if (byteSize == 4) {
masm.storeFloat32(ToFloatRegister(lir->value()), BaseIndex(HeapReg, ptr, TimesOne));
masm.storeFloat32(ToFloatRegister(lir->value()), address);
} else
masm.storeDouble(ToFloatRegister(lir->value()), BaseIndex(HeapReg, ptr, TimesOne));
masm.storeDouble(ToFloatRegister(lir->value()), address);
} else {
masm.ma_store(ToRegister(lir->value()), BaseIndex(HeapReg, ptr, TimesOne),
static_cast<LoadStoreSize>(8 * byteSize), isSigned ? SignExtend : ZeroExtend);
masm.ma_store(ToRegister(lir->value()), address,
static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
}
memoryBarrier(mir->barrierAfter());

2
js/src/jit/mips-shared/Lowering-mips-shared.cpp
View File

@ -339,7 +339,6 @@ LIRGeneratorMIPSShared::visitWasmLoad(MWasmLoad* ins)
lir->setTemp(0, tempCopy(base, 0));
define(lir, ins);
return;
}
@ -385,7 +384,6 @@ LIRGeneratorMIPSShared::visitWasmStore(MWasmStore* ins)
lir->setTemp(0, tempCopy(base, 0));
add(lir, ins);
return;
}

70
js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
View File

@ -446,47 +446,46 @@ MacroAssemblerMIPSShared::ma_load(Register dest, const BaseIndex& src,
}
void
MacroAssemblerMIPSShared::ma_load_unaligned(Register dest, const BaseIndex& src,
Register temp, LoadStoreSize size, LoadStoreExtension extension)
MacroAssemblerMIPSShared::ma_load_unaligned(Register dest, const BaseIndex& src, Register temp,
LoadStoreSize size, LoadStoreExtension extension)
{
int16_t encodedOffset;
int16_t lowOffset, hiOffset;
Register base;
asMasm().computeScaledAddress(src, SecondScratchReg);
if (Imm16::IsInSignedRange(src.offset) && Imm16::IsInSignedRange(src.offset + size / 8 - 1)) {
encodedOffset = Imm16(src.offset).encode();
base = SecondScratchReg;
lowOffset = Imm16(src.offset).encode();
hiOffset = Imm16(src.offset + size / 8 - 1).encode();
} else {
ma_li(ScratchRegister, Imm32(src.offset));
as_daddu(ScratchRegister, SecondScratchReg, ScratchRegister);
base = ScratchRegister;
encodedOffset = Imm16(0).encode();
lowOffset = Imm16(0).encode();
hiOffset = Imm16(size / 8 - 1).encode();
}
switch (size) {
case SizeByte:
if (ZeroExtend == extension)
as_lbu(dest, base, encodedOffset);
else
as_lb(dest, base, encodedOffset);
break;
case SizeHalfWord:
as_lbu(dest, base, encodedOffset);
as_lbu(temp, base, encodedOffset + 1);
as_ins(dest, temp, 8, 8);
if (ZeroExtend != extension)
as_seh(dest, dest);
as_lbu(dest, base, lowOffset);
if (extension != ZeroExtend)
as_lbu(temp, base, hiOffset);
else
as_lb(temp, base, hiOffset);
as_ins(dest, temp, 8, 24);
break;
case SizeWord:
as_lwl(dest, base, encodedOffset + 3);
as_lwr(dest, base, encodedOffset);
if (ZeroExtend == extension)
as_ext(dest, dest, 0, 32);
as_lwl(dest, base, hiOffset);
as_lwr(dest, base, lowOffset);
#ifdef JS_CODEGEN_MIPS64
if (extension != ZeroExtend)
as_dext(dest, dest, 0, 32);
#endif
break;
case SizeDouble:
as_ldl(dest, base, encodedOffset + 7);
as_ldr(dest, base, encodedOffset);
as_ldl(dest, base, hiOffset);
as_ldr(dest, base, lowOffset);
break;
default:
MOZ_CRASH("Invalid argument for ma_load");
@ -594,40 +593,39 @@ MacroAssemblerMIPSShared::ma_store(Imm32 imm, const BaseIndex& dest,
}
void
MacroAssemblerMIPSShared::ma_store_unaligned(Register data, const BaseIndex& dest,
Register temp, LoadStoreSize size, LoadStoreExtension extension)
MacroAssemblerMIPSShared::ma_store_unaligned(Register data, const BaseIndex& dest, Register temp,
LoadStoreSize size, LoadStoreExtension extension)
{
int16_t encodedOffset;
int16_t lowOffset, hiOffset;
Register base;
asMasm().computeEffectiveAddress(dest, SecondScratchReg);
if (Imm16::IsInSignedRange(dest.offset) && Imm16::IsInSignedRange(dest.offset + size / 8 - 1)) {
encodedOffset = Imm16(dest.offset).encode();
base = SecondScratchReg;
lowOffset = Imm16(dest.offset).encode();
hiOffset = Imm16(dest.offset + size / 8 - 1).encode();
} else {
ma_li(ScratchRegister, Imm32(dest.offset));
as_daddu(ScratchRegister, SecondScratchReg, ScratchRegister);
base = ScratchRegister;
encodedOffset = Imm16(0).encode();
lowOffset = Imm16(0).encode();
hiOffset = Imm16(size / 8 - 1).encode();
}
switch (size) {
case SizeByte:
as_sb(data, base, encodedOffset);
break;
case SizeHalfWord:
as_sb(data, base, encodedOffset);
as_sb(data, base, lowOffset);
as_ext(temp, data, 8, 8);
as_sb(temp, base, encodedOffset + 1);
as_sb(temp, base, hiOffset);
break;
case SizeWord:
as_swl(data, base, encodedOffset + 3);
as_swr(data, base, encodedOffset);
as_swl(data, base, hiOffset);
as_swr(data, base, lowOffset);
break;
case SizeDouble:
as_sdl(data, base, encodedOffset + 7);
as_sdr(data, base, encodedOffset);
as_sdl(data, base, hiOffset);
as_sdr(data, base, lowOffset);
break;
default:
MOZ_CRASH("Invalid argument for ma_store");

6
js/src/jit/mips-shared/MacroAssembler-mips-shared.h
View File

@ -105,8 +105,7 @@ class MacroAssemblerMIPSShared : public Assembler
void ma_load(Register dest, const BaseIndex& src, LoadStoreSize size = SizeWord,
LoadStoreExtension extension = SignExtend);
void ma_load_unaligned(Register dest, const BaseIndex& src, Register temp,
LoadStoreSize size = SizeWord,
LoadStoreExtension extension = SignExtend);
LoadStoreSize size, LoadStoreExtension extension);
// store
void ma_store(Register data, const BaseIndex& dest, LoadStoreSize size = SizeWord,
@ -114,8 +113,7 @@ class MacroAssemblerMIPSShared : public Assembler
void ma_store(Imm32 imm, const BaseIndex& dest, LoadStoreSize size = SizeWord,
LoadStoreExtension extension = SignExtend);
void ma_store_unaligned(Register data, const BaseIndex& dest, Register temp,
LoadStoreSize size = SizeWord,
LoadStoreExtension extension = SignExtend);
LoadStoreSize size, LoadStoreExtension extension);
// arithmetic based ops
// add

25
js/src/jit/mips32/CodeGenerator-mips32.cpp
View File

@ -500,13 +500,13 @@ CodeGeneratorMIPS::emitWasmLoadI64(T* lir)
masm.move32(Imm32(0), output.high);
else
masm.ma_sra(output.high, output.low, Imm32(31));
} else {
ScratchRegisterScope scratch(masm);
masm.ma_load_unaligned(output.low, BaseIndex(HeapReg, ptr, TimesOne), temp, SizeWord);
masm.ma_load_unaligned(output.low, BaseIndex(HeapReg, ptr, TimesOne),
temp, SizeWord, isSigned ? SignExtend : ZeroExtend);
masm.ma_addu(scratch, ptr, Imm32(INT64HIGH_OFFSET));
masm.ma_load_unaligned(output.high, BaseIndex(HeapReg, scratch, TimesOne),
temp, SizeWord);
temp, SizeWord, isSigned ? SignExtend : ZeroExtend);
}
return;
}
@ -561,6 +561,17 @@ CodeGeneratorMIPS::emitWasmStoreI64(T* lir)
}
unsigned byteSize = mir->byteSize();
bool isSigned;
switch (mir->accessType()) {
case Scalar::Int8: isSigned = true; break;
case Scalar::Uint8: isSigned = false; break;
case Scalar::Int16: isSigned = true; break;
case Scalar::Uint16: isSigned = false; break;
case Scalar::Int32: isSigned = true; break;
case Scalar::Uint32: isSigned = false; break;
case Scalar::Int64: isSigned = true; break;
default: MOZ_CRASH("unexpected array type");
}
memoryBarrier(mir->barrierBefore());
@ -570,13 +581,15 @@ CodeGeneratorMIPS::emitWasmStoreI64(T* lir)
if (byteSize <= 4) {
masm.ma_store_unaligned(value.low, BaseIndex(HeapReg, ptr, TimesOne),
temp, static_cast<LoadStoreSize>(8 * byteSize));
temp, static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
} else {
ScratchRegisterScope scratch(masm);
masm.ma_store_unaligned(value.low, BaseIndex(HeapReg, ptr, TimesOne), temp, SizeWord);
masm.ma_store_unaligned(value.low, BaseIndex(HeapReg, ptr, TimesOne),
temp, SizeWord, isSigned ? SignExtend : ZeroExtend);
masm.ma_addu(scratch, ptr, Imm32(INT64HIGH_OFFSET));
masm.ma_store_unaligned(value.high, BaseIndex(HeapReg, scratch, TimesOne),
temp, SizeWord);
temp, SizeWord, isSigned ? SignExtend : ZeroExtend);
}
return;
}