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Bug 1211409 - load/store exclusive for ARM-32. r=jolesen
This commit is contained in:
Lars T Hansen
parent
46310c2e6d
commit
3073aa69bc
91
js/src/jit-test/tests/atomics/mutual-exclusion.js
Normal file
91
js/src/jit-test/tests/atomics/mutual-exclusion.js
Normal file
@ -0,0 +1,91 @@
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// Let a few threads hammer on memory with atomics to provoke errors
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// in exclusion work. This test is not 100% fail-safe: the test may
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// pass despite a bug, but this is unlikely.
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if (!(this.SharedArrayBuffer && this.getSharedArrayBuffer && this.setSharedArrayBuffer))
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quit(0);
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// Map an Int32Array on shared memory. The first location is used as
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// a counter, each worker counts up on exit and the main thread will
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// wait until the counter reaches the number of workers. The other
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// elements are contended accumulators where we count up and down very
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// rapidly and for a long time, any failure in mutual exclusion should
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// lead to errors in the result. (For example, the test fails almost
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// immediately when I disable simulation of mutual exclusion in the
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// ARM simulator.)
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const numWorkers = 4; // You're not meant to change this
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const iterCount = 255; // Nor this
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const sabLength = 1024; // Nor this
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const oddResult = (function () {
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var v = 0;
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for ( var j=0 ; j < numWorkers ; j++ )
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v |= (iterCount << (8 * j));
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return v;
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})();
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const evenResult = 0;
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const sab = new SharedArrayBuffer(sabLength);
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setSharedArrayBuffer(sab);
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const iab = new SharedInt32Array(sab);
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function testRun(limit) {
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console.log("Limit = " + limit);
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// Fork off workers to hammer on memory.
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for ( var i=0 ; i < numWorkers ; i++ ) {
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evalInWorker(`
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const iab = new SharedInt32Array(getSharedArrayBuffer());
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const v = 1 << (8 * ${i});
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for ( var i=0 ; i < ${limit} ; i++ ) {
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for ( var k=0 ; k < ${iterCount} ; k++ ) {
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if (i & 1) {
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for ( var j=1 ; j < iab.length ; j++ )
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Atomics.sub(iab, j, v);
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}
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else {
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for ( var j=1 ; j < iab.length ; j++ )
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Atomics.add(iab, j, v);
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}
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}
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}
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Atomics.add(iab, 0, 1);
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`);
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}
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// Wait...
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while (Atomics.load(iab, 0) != numWorkers)
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;
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Atomics.store(iab, 0, 0);
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// Check the results and clear the array again.
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const v = (limit & 1) ? oddResult : evenResult;
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for ( var i=1 ; i < iab.length ; i++ ) {
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assertEq(iab[i], v);
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iab[i] = 0;
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}
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}
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function fib(n) {
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if (n < 2)
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return n;
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return fib(n-1) + fib(n-2);
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}
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const limit = (function () {
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var val = 5;
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if (typeof getJitCompilerOptions == "function") {
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var opt = getJitCompilerOptions();
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if (opt["ion.enable"])
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val = 10;
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}
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return val;
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})();
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console.log("This test can easily take 60s on 2015-class x86 hardware");
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for ( var i=2 ; i < limit ; i++ )
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testRun(fib(i));
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@ -36,9 +36,11 @@
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#include "mozilla/SizePrintfMacros.h"
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#include "asmjs/AsmJSValidate.h"
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#include "jit/AtomicOperations.h"
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#include "jit/arm/Assembler-arm.h"
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#include "jit/arm/disasm/Constants-arm.h"
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#include "vm/Runtime.h"
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#include "vm/SharedMem.h"
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extern "C" {
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@ -1127,6 +1129,8 @@ Simulator::Simulator()
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cacheLockHolder_ = nullptr;
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#endif
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redirection_ = nullptr;
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exclusiveMonitorHeld_ = false;
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exclusiveMonitor_ = 0;
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}
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bool
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@ -1478,6 +1482,27 @@ Simulator::setCallResult(int64_t res)
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set_register(r1, static_cast<int32_t>(res >> 32));
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}
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void
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Simulator::exclusiveMonitorSet(uint64_t value)
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{
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exclusiveMonitor_ = value;
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exclusiveMonitorHeld_ = true;
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}
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uint64_t
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Simulator::exclusiveMonitorGetAndClear(bool* held)
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{
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*held = exclusiveMonitorHeld_;
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exclusiveMonitorHeld_ = false;
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return *held ? exclusiveMonitor_ : 0;
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}
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void
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Simulator::exclusiveMonitorClear()
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{
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exclusiveMonitorHeld_ = false;
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}
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int
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Simulator::readW(int32_t addr, SimInstruction* instr)
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{
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@ -1504,14 +1529,66 @@ Simulator::writeW(int32_t addr, int value, SimInstruction* instr)
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}
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}
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// For the time being, define Relaxed operations in terms of SeqCst
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// operations - we don't yet need Relaxed operations anywhere else in
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// the system, and the distinction is not important to the simulation
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// at the level where we're operating.
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template<typename T>
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static
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T loadRelaxed(SharedMem<T*> addr)
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{
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return AtomicOperations::loadSeqCst(addr);
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}
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template<typename T>
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static
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T compareExchangeRelaxed(SharedMem<T*> addr, T oldval, T newval)
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{
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return AtomicOperations::compareExchangeSeqCst(addr, oldval, newval);
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}
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int
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Simulator::readExW(int32_t addr, SimInstruction* instr)
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{
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// The regexp engine emits unaligned loads, so we don't check for them here
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// like most of the other methods do.
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if ((addr & 3) == 0 || !HasAlignmentFault()) {
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SharedMem<int32_t*> ptr = SharedMem<int32_t*>::shared(reinterpret_cast<int32_t*>(addr));
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int32_t value = loadRelaxed(ptr);
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exclusiveMonitorSet(value);
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return value;
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} else {
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printf("Unaligned write at 0x%08x, pc=%p\n", addr, instr);
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MOZ_CRASH();
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}
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}
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int32_t
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Simulator::writeExW(int32_t addr, int value, SimInstruction* instr)
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{
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if ((addr & 3) == 0) {
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SharedMem<int32_t*> ptr = SharedMem<int32_t*>::shared(reinterpret_cast<int32_t*>(addr));
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bool held;
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int32_t expected = int32_t(exclusiveMonitorGetAndClear(&held));
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if (!held)
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return 1;
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int32_t old = compareExchangeRelaxed(ptr, expected, int32_t(value));
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return old != expected;
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} else {
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printf("Unaligned write at 0x%08x, pc=%p\n", addr, instr);
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MOZ_CRASH();
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}
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}
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uint16_t
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Simulator::readHU(int32_t addr, SimInstruction* instr)
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{
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// The regexp engine emits unaligned loads, so we don't check for them here
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// like most of the other methods do.
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if ((addr & 1) == 0 || !HasAlignmentFault()) {
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uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
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return *ptr;
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uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
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return *ptr;
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}
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printf("Unaligned unsigned halfword read at 0x%08x, pc=%p\n", addr, instr);
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MOZ_CRASH();
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@ -1554,6 +1631,39 @@ Simulator::writeH(int32_t addr, int16_t value, SimInstruction* instr)
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}
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}
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uint16_t
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Simulator::readExHU(int32_t addr, SimInstruction* instr)
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{
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// The regexp engine emits unaligned loads, so we don't check for them here
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// like most of the other methods do.
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if ((addr & 1) == 0 || !HasAlignmentFault()) {
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SharedMem<uint16_t*> ptr = SharedMem<uint16_t*>::shared(reinterpret_cast<uint16_t*>(addr));
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uint16_t value = loadRelaxed(ptr);
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exclusiveMonitorSet(value);
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return value;
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}
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printf("Unaligned atomic unsigned halfword read at 0x%08x, pc=%p\n", addr, instr);
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MOZ_CRASH();
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return 0;
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}
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int32_t
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Simulator::writeExH(int32_t addr, uint16_t value, SimInstruction* instr)
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{
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if ((addr & 1) == 0) {
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SharedMem<uint16_t*> ptr = SharedMem<uint16_t*>::shared(reinterpret_cast<uint16_t*>(addr));
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bool held;
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uint16_t expected = uint16_t(exclusiveMonitorGetAndClear(&held));
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if (!held)
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return 1;
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uint16_t old = compareExchangeRelaxed(ptr, expected, value);
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return old != expected;
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} else {
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printf("Unaligned atomic unsigned halfword write at 0x%08x, pc=%p\n", addr, instr);
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MOZ_CRASH();
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}
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}
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uint8_t
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Simulator::readBU(int32_t addr)
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{
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@ -1561,6 +1671,27 @@ Simulator::readBU(int32_t addr)
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return *ptr;
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}
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uint8_t
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Simulator::readExBU(int32_t addr)
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{
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SharedMem<uint8_t*> ptr = SharedMem<uint8_t*>::shared(reinterpret_cast<uint8_t*>(addr));
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uint8_t value = loadRelaxed(ptr);
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exclusiveMonitorSet(value);
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return value;
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}
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int32_t
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Simulator::writeExB(int32_t addr, uint8_t value)
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{
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SharedMem<uint8_t*> ptr = SharedMem<uint8_t*>::shared(reinterpret_cast<uint8_t*>(addr));
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bool held;
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uint8_t expected = uint8_t(exclusiveMonitorGetAndClear(&held));
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if (!held)
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return 1;
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uint8_t old = compareExchangeRelaxed(ptr, expected, value);
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return old != expected;
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}
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int8_t
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Simulator::readB(int32_t addr)
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{
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@ -1607,6 +1738,49 @@ Simulator::writeDW(int32_t addr, int32_t value1, int32_t value2)
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}
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}
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int32_t
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Simulator::readExDW(int32_t addr, int32_t* hibits)
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{
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#if defined(__clang__) && defined(__i386)
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// This is OK for now, we don't yet generate LDREXD.
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MOZ_CRASH("Unimplemented - 8-byte atomics are unsupported in Clang on i386");
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#else
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if ((addr & 3) == 0) {
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SharedMem<uint64_t*> ptr = SharedMem<uint64_t*>::shared(reinterpret_cast<uint64_t*>(addr));
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uint64_t value = loadRelaxed(ptr);
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exclusiveMonitorSet(value);
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*hibits = int32_t(value);
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return int32_t(value >> 32);
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}
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printf("Unaligned read at 0x%08x\n", addr);
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MOZ_CRASH();
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return 0;
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#endif
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}
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int32_t
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Simulator::writeExDW(int32_t addr, int32_t value1, int32_t value2)
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{
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#if defined(__clang__) && defined(__i386)
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// This is OK for now, we don't yet generate STREXD.
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MOZ_CRASH("Unimplemented - 8-byte atomics are unsupported in Clang on i386");
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#else
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if ((addr & 3) == 0) {
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SharedMem<uint64_t*> ptr = SharedMem<uint64_t*>::shared(reinterpret_cast<uint64_t*>(addr));
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uint64_t value = (uint64_t(value1) << 32) | uint32_t(value2);
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bool held;
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uint64_t expected = exclusiveMonitorGetAndClear(&held);
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if (!held)
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return 1;
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uint64_t old = compareExchangeRelaxed(ptr, expected, value);
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return old != expected;
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} else {
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printf("Unaligned write at 0x%08x\n", addr);
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MOZ_CRASH();
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}
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#endif
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}
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uintptr_t
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Simulator::stackLimit() const
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{
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@ -2554,33 +2728,27 @@ Simulator::decodeType01(SimInstruction* instr)
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} else {
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if (instr->bits(disasm::ExclusiveOpHi, disasm::ExclusiveOpLo) == disasm::ExclusiveOpcode) {
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// Load-exclusive / store-exclusive.
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//
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// Bare-bones simulation: the store always succeeds, and we
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// do not execute any fences. Also, we allow readDW and
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// writeDW to split the memory transaction.
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//
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// The next step up would involve remembering the value
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// that was read with load-exclusive so that we could use
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// compareExchange for the store-exclusive, and to
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// implement atomic doubleword read and write.
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//
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// Also see DMB/DSB/ISB below.
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if (instr->bit(disasm::ExclusiveLoad)) {
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int rn = instr->rnValue();
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int rt = instr->rtValue();
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int32_t address = get_register(rn);
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switch (instr->bits(disasm::ExclusiveSizeHi, disasm::ExclusiveSizeLo)) {
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case disasm::ExclusiveWord:
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set_register(rt, readW(address, instr));
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set_register(rt, readExW(address, instr));
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break;
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case disasm::ExclusiveDouble:
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set_dw_register(rt, readDW(address));
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case disasm::ExclusiveDouble: {
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MOZ_ASSERT((rt % 2) == 0);
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int32_t hibits;
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int32_t lobits = readExDW(address, &hibits);
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set_register(rt, lobits);
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set_register(rt+1, hibits);
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break;
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}
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case disasm::ExclusiveByte:
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set_register(rt, readBU(address));
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set_register(rt, readExBU(address));
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break;
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case disasm::ExclusiveHalf:
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set_register(rt, readHU(address, instr));
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set_register(rt, readExHU(address, instr));
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break;
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}
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} else {
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@ -2589,24 +2757,25 @@ Simulator::decodeType01(SimInstruction* instr)
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int rt = instr->bits(3,0);
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int32_t address = get_register(rn);
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int32_t value = get_register(rt);
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int32_t result = 0;
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switch (instr->bits(disasm::ExclusiveSizeHi, disasm::ExclusiveSizeLo)) {
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case disasm::ExclusiveWord:
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writeW(address, value, instr);
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result = writeExW(address, value, instr);
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break;
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case disasm::ExclusiveDouble: {
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MOZ_ASSERT((rt % 2) == 0);
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int32_t value2 = get_register(rt+1);
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writeDW(address, value, value2);
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break;
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MOZ_ASSERT((rt % 2) == 0);
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int32_t value2 = get_register(rt+1);
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result = writeExDW(address, value, value2);
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break;
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}
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case disasm::ExclusiveByte:
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writeB(address, (uint8_t)value);
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result = writeExB(address, (uint8_t)value);
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break;
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case disasm::ExclusiveHalf:
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writeH(address, (uint16_t)value, instr);
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result = writeExH(address, (uint16_t)value, instr);
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break;
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}
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set_register(rd, 0);
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set_register(rd, result);
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}
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} else {
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MOZ_CRASH(); // Not used atm
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@ -3329,12 +3498,15 @@ Simulator::decodeType7CoprocessorIns(SimInstruction* instr)
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int CRn = instr->bits(19,16);
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int CRm = instr->bits(3,0);
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if (opc1 == 0 && opc2 == 4 && CRn == 7 && CRm == 10) {
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// ARMv6 DSB instruction - do nothing now, see comments above
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// ARMv6 DSB instruction. We do not use DSB.
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MOZ_CRASH("DSB not implemented");
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} else if (opc1 == 0 && opc2 == 5 && CRn == 7 && CRm == 10) {
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// ARMv6 DMB instruction - do nothing now, see comments above
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// ARMv6 DMB instruction.
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AtomicOperations::fenceSeqCst();
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}
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else if (opc1 == 0 && opc2 == 4 && CRn == 7 && CRm == 5) {
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// ARMv6 ISB instruction - do nothing now, see comments above
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// ARMv6 ISB instruction. We do not use ISB.
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MOZ_CRASH("ISB not implemented");
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}
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else {
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MOZ_CRASH();
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@ -4156,16 +4328,16 @@ Simulator::decodeSpecialCondition(SimInstruction* instr)
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break;
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case 0xA:
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if (instr->bits(31,20) == 0xf57) {
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// Minimal simulation: do nothing.
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//
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// If/when we upgrade load-exclusive and store-exclusive (above) to
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// do something useful concurrency-wise, we should also upgrade
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// these instructions.
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switch (instr->bits(7,4)) {
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case 5: // DMB
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case 4: // DSB
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case 6: // ISB
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AtomicOperations::fenceSeqCst();
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break;
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case 4: // DSB
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// We do not use DSB.
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MOZ_CRASH("DSB unimplemented");
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case 6: // ISB
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// We do not use ISB.
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MOZ_CRASH("ISB unimplemented");
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default:
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MOZ_CRASH();
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}
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@ -248,18 +248,30 @@ class Simulator
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inline void writeB(int32_t addr, uint8_t value);
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inline void writeB(int32_t addr, int8_t value);
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|
||||
inline uint8_t readExBU(int32_t addr);
|
||||
inline int32_t writeExB(int32_t addr, uint8_t value);
|
||||
|
||||
inline uint16_t readHU(int32_t addr, SimInstruction* instr);
|
||||
inline int16_t readH(int32_t addr, SimInstruction* instr);
|
||||
// Note: Overloaded on the sign of the value.
|
||||
inline void writeH(int32_t addr, uint16_t value, SimInstruction* instr);
|
||||
inline void writeH(int32_t addr, int16_t value, SimInstruction* instr);
|
||||
|
||||
inline uint16_t readExHU(int32_t addr, SimInstruction* instr);
|
||||
inline int32_t writeExH(int32_t addr, uint16_t value, SimInstruction* instr);
|
||||
|
||||
inline int readW(int32_t addr, SimInstruction* instr);
|
||||
inline void writeW(int32_t addr, int value, SimInstruction* instr);
|
||||
|
||||
inline int readExW(int32_t addr, SimInstruction* instr);
|
||||
inline int writeExW(int32_t addr, int value, SimInstruction* instr);
|
||||
|
||||
int32_t* readDW(int32_t addr);
|
||||
void writeDW(int32_t addr, int32_t value1, int32_t value2);
|
||||
|
||||
int32_t readExDW(int32_t addr, int32_t* hibits);
|
||||
int32_t writeExDW(int32_t addr, int32_t value1, int32_t value2);
|
||||
|
||||
// Executing is handled based on the instruction type.
|
||||
// Both type 0 and type 1 rolled into one.
|
||||
void decodeType01(SimInstruction* instr);
|
||||
@ -432,6 +444,15 @@ class Simulator
|
||||
MOZ_ASSERT(cacheLockHolder_);
|
||||
redirection_ = redirection;
|
||||
}
|
||||
|
||||
private:
|
||||
// Exclusive access monitor
|
||||
void exclusiveMonitorSet(uint64_t value);
|
||||
uint64_t exclusiveMonitorGetAndClear(bool* held);
|
||||
void exclusiveMonitorClear();
|
||||
|
||||
bool exclusiveMonitorHeld_;
|
||||
uint64_t exclusiveMonitor_;
|
||||
};
|
||||
|
||||
#define JS_CHECK_SIMULATOR_RECURSION_WITH_EXTRA(cx, extra, onerror) \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user