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Backed out changeset 502f442198b6 (bug 1360248) for build bustage in WasmSignalHandlers.cpp, at least on Windows 2012. r=backout on a CLOSED TREE
This commit is contained in:
Sebastian Hengst
parent
e6d07c36b9
commit
67fb8912b0
@ -71,151 +71,6 @@ StackDecrementForCall(MacroAssembler& masm, uint32_t alignment, const VectorT& a
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return StackDecrementForCall(masm, alignment, StackArgBytes(args) + extraBytes);
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}
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static void
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SetupABIArguments(MacroAssembler& masm, const FuncExport& fe, Register argv, Register scratch)
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{
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// Copy parameters out of argv and into the registers/stack-slots specified by
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// the system ABI.
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for (ABIArgValTypeIter iter(fe.sig().args()); !iter.done(); iter++) {
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unsigned argOffset = iter.index() * sizeof(ExportArg);
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Address src(argv, argOffset);
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MIRType type = iter.mirType();
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switch (iter->kind()) {
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case ABIArg::GPR:
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if (type == MIRType::Int32)
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masm.load32(src, iter->gpr());
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else if (type == MIRType::Int64)
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masm.load64(src, iter->gpr64());
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break;
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#ifdef JS_CODEGEN_REGISTER_PAIR
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case ABIArg::GPR_PAIR:
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if (type == MIRType::Int64)
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masm.load64(src, iter->gpr64());
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else
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MOZ_CRASH("wasm uses hardfp for function calls.");
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break;
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#endif
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case ABIArg::FPU: {
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static_assert(sizeof(ExportArg) >= jit::Simd128DataSize,
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"ExportArg must be big enough to store SIMD values");
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switch (type) {
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case MIRType::Int8x16:
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case MIRType::Int16x8:
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case MIRType::Int32x4:
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case MIRType::Bool8x16:
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case MIRType::Bool16x8:
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case MIRType::Bool32x4:
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masm.loadUnalignedSimd128Int(src, iter->fpu());
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break;
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case MIRType::Float32x4:
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masm.loadUnalignedSimd128Float(src, iter->fpu());
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break;
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case MIRType::Double:
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masm.loadDouble(src, iter->fpu());
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break;
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case MIRType::Float32:
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masm.loadFloat32(src, iter->fpu());
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break;
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default:
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MOZ_MAKE_COMPILER_ASSUME_IS_UNREACHABLE("unexpected FPU type");
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break;
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}
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break;
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}
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case ABIArg::Stack:
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switch (type) {
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case MIRType::Int32:
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masm.load32(src, scratch);
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masm.storePtr(scratch, Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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case MIRType::Int64: {
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Register sp = masm.getStackPointer();
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#if JS_BITS_PER_WORD == 32
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masm.load32(Address(src.base, src.offset + INT64LOW_OFFSET), scratch);
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masm.store32(scratch, Address(sp, iter->offsetFromArgBase() + INT64LOW_OFFSET));
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masm.load32(Address(src.base, src.offset + INT64HIGH_OFFSET), scratch);
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masm.store32(scratch, Address(sp, iter->offsetFromArgBase() + INT64HIGH_OFFSET));
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#else
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Register64 scratch64(scratch);
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masm.load64(src, scratch64);
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masm.store64(scratch64, Address(sp, iter->offsetFromArgBase()));
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#endif
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break;
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}
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case MIRType::Double:
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masm.loadDouble(src, ScratchDoubleReg);
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masm.storeDouble(ScratchDoubleReg,
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Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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case MIRType::Float32:
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masm.loadFloat32(src, ScratchFloat32Reg);
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masm.storeFloat32(ScratchFloat32Reg,
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Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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case MIRType::Int8x16:
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case MIRType::Int16x8:
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case MIRType::Int32x4:
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case MIRType::Bool8x16:
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case MIRType::Bool16x8:
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case MIRType::Bool32x4:
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masm.loadUnalignedSimd128Int(src, ScratchSimd128Reg);
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masm.storeAlignedSimd128Int(
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ScratchSimd128Reg, Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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case MIRType::Float32x4:
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masm.loadUnalignedSimd128Float(src, ScratchSimd128Reg);
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masm.storeAlignedSimd128Float(
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ScratchSimd128Reg, Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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default:
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MOZ_MAKE_COMPILER_ASSUME_IS_UNREACHABLE("unexpected stack arg type");
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}
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break;
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}
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}
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}
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static void
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StoreABIReturn(MacroAssembler& masm, const FuncExport& fe, Register argv)
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{
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// Store the return value in argv[0]
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switch (fe.sig().ret()) {
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case ExprType::Void:
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break;
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case ExprType::I32:
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masm.store32(ReturnReg, Address(argv, 0));
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break;
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case ExprType::I64:
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masm.store64(ReturnReg64, Address(argv, 0));
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break;
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case ExprType::F32:
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if (!JitOptions.wasmTestMode)
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masm.canonicalizeFloat(ReturnFloat32Reg);
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masm.storeFloat32(ReturnFloat32Reg, Address(argv, 0));
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break;
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case ExprType::F64:
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if (!JitOptions.wasmTestMode)
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masm.canonicalizeDouble(ReturnDoubleReg);
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masm.storeDouble(ReturnDoubleReg, Address(argv, 0));
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break;
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case ExprType::I8x16:
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case ExprType::I16x8:
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case ExprType::I32x4:
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case ExprType::B8x16:
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case ExprType::B16x8:
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case ExprType::B32x4:
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// We don't have control on argv alignment, do an unaligned access.
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masm.storeUnalignedSimd128Int(ReturnSimd128Reg, Address(argv, 0));
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break;
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case ExprType::F32x4:
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// We don't have control on argv alignment, do an unaligned access.
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masm.storeUnalignedSimd128Float(ReturnSimd128Reg, Address(argv, 0));
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break;
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case ExprType::Limit:
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MOZ_CRASH("Limit");
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}
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}
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#if defined(JS_CODEGEN_ARM)
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// The ARM system ABI also includes d15 & s31 in the non volatile float registers.
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// Also exclude lr (a.k.a. r14) as we preserve it manually)
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@ -316,8 +171,105 @@ wasm::GenerateEntry(MacroAssembler& masm, const FuncExport& fe)
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// Bump the stack for the call.
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masm.reserveStack(AlignBytes(StackArgBytes(fe.sig().args()), WasmStackAlignment));
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// Copy parameters out of argv and into the wasm ABI registers/stack-slots.
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SetupABIArguments(masm, fe, argv, scratch);
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// Copy parameters out of argv and into the registers/stack-slots specified by
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// the system ABI.
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for (ABIArgValTypeIter iter(fe.sig().args()); !iter.done(); iter++) {
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unsigned argOffset = iter.index() * sizeof(ExportArg);
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Address src(argv, argOffset);
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MIRType type = iter.mirType();
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switch (iter->kind()) {
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case ABIArg::GPR:
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if (type == MIRType::Int32)
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masm.load32(src, iter->gpr());
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else if (type == MIRType::Int64)
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masm.load64(src, iter->gpr64());
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break;
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#ifdef JS_CODEGEN_REGISTER_PAIR
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case ABIArg::GPR_PAIR:
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if (type == MIRType::Int64)
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masm.load64(src, iter->gpr64());
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else
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MOZ_CRASH("wasm uses hardfp for function calls.");
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break;
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#endif
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case ABIArg::FPU: {
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static_assert(sizeof(ExportArg) >= jit::Simd128DataSize,
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"ExportArg must be big enough to store SIMD values");
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switch (type) {
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case MIRType::Int8x16:
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case MIRType::Int16x8:
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case MIRType::Int32x4:
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case MIRType::Bool8x16:
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case MIRType::Bool16x8:
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case MIRType::Bool32x4:
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masm.loadUnalignedSimd128Int(src, iter->fpu());
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break;
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case MIRType::Float32x4:
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masm.loadUnalignedSimd128Float(src, iter->fpu());
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break;
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case MIRType::Double:
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masm.loadDouble(src, iter->fpu());
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break;
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case MIRType::Float32:
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masm.loadFloat32(src, iter->fpu());
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break;
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default:
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MOZ_MAKE_COMPILER_ASSUME_IS_UNREACHABLE("unexpected FPU type");
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break;
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}
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break;
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}
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case ABIArg::Stack:
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switch (type) {
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case MIRType::Int32:
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masm.load32(src, scratch);
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masm.storePtr(scratch, Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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case MIRType::Int64: {
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Register sp = masm.getStackPointer();
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#if JS_BITS_PER_WORD == 32
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masm.load32(Address(src.base, src.offset + INT64LOW_OFFSET), scratch);
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masm.store32(scratch, Address(sp, iter->offsetFromArgBase() + INT64LOW_OFFSET));
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masm.load32(Address(src.base, src.offset + INT64HIGH_OFFSET), scratch);
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masm.store32(scratch, Address(sp, iter->offsetFromArgBase() + INT64HIGH_OFFSET));
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#else
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Register64 scratch64(scratch);
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masm.load64(src, scratch64);
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masm.store64(scratch64, Address(sp, iter->offsetFromArgBase()));
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#endif
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break;
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}
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case MIRType::Double:
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masm.loadDouble(src, ScratchDoubleReg);
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masm.storeDouble(ScratchDoubleReg,
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Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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case MIRType::Float32:
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masm.loadFloat32(src, ScratchFloat32Reg);
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masm.storeFloat32(ScratchFloat32Reg,
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Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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case MIRType::Int8x16:
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case MIRType::Int16x8:
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case MIRType::Int32x4:
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case MIRType::Bool8x16:
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case MIRType::Bool16x8:
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case MIRType::Bool32x4:
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masm.loadUnalignedSimd128Int(src, ScratchSimd128Reg);
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masm.storeAlignedSimd128Int(
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ScratchSimd128Reg, Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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case MIRType::Float32x4:
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masm.loadUnalignedSimd128Float(src, ScratchSimd128Reg);
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masm.storeAlignedSimd128Float(
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ScratchSimd128Reg, Address(masm.getStackPointer(), iter->offsetFromArgBase()));
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break;
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default:
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MOZ_MAKE_COMPILER_ASSUME_IS_UNREACHABLE("unexpected stack arg type");
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}
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break;
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}
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}
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// Set the FramePointer to null for the benefit of debugging.
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masm.movePtr(ImmWord(0), FramePointer);
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@ -344,8 +296,42 @@ wasm::GenerateEntry(MacroAssembler& masm, const FuncExport& fe)
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// Recover the 'argv' pointer which was saved before aligning the stack.
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masm.Pop(argv);
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// Store the return value into argv.
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StoreABIReturn(masm, fe, argv);
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// Store the return value in argv[0]
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switch (fe.sig().ret()) {
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case ExprType::Void:
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break;
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case ExprType::I32:
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masm.store32(ReturnReg, Address(argv, 0));
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break;
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case ExprType::I64:
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masm.store64(ReturnReg64, Address(argv, 0));
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break;
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case ExprType::F32:
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if (!JitOptions.wasmTestMode)
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masm.canonicalizeFloat(ReturnFloat32Reg);
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masm.storeFloat32(ReturnFloat32Reg, Address(argv, 0));
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break;
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case ExprType::F64:
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if (!JitOptions.wasmTestMode)
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masm.canonicalizeDouble(ReturnDoubleReg);
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masm.storeDouble(ReturnDoubleReg, Address(argv, 0));
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break;
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case ExprType::I8x16:
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case ExprType::I16x8:
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case ExprType::I32x4:
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case ExprType::B8x16:
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case ExprType::B16x8:
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case ExprType::B32x4:
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// We don't have control on argv alignment, do an unaligned access.
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masm.storeUnalignedSimd128Int(ReturnSimd128Reg, Address(argv, 0));
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break;
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case ExprType::F32x4:
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// We don't have control on argv alignment, do an unaligned access.
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masm.storeUnalignedSimd128Float(ReturnSimd128Reg, Address(argv, 0));
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break;
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case ExprType::Limit:
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MOZ_CRASH("Limit");
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}
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// Restore clobbered non-volatile registers of the caller.
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masm.PopRegsInMask(NonVolatileRegs);
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