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Bug 1019831: SIMD x86-x64: Float32x4 unaligned moves; r=sunfish

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--HG--
extra : rebase_source : dc004250dac2c3e44a482e334c64aa38fb46f388
This commit is contained in:
Benjamin Bouvier 2014-08-07 17:58:41 +02:00
parent 1d05e1c042
commit 7b824bf050
3 changed files with 60 additions and 0 deletions
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28
js/src/assembler/assembler/X86Assembler.h
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@ -285,7 +285,9 @@ private:
typedef enum {
OP2_UD2 = 0x0B,
OP2_MOVSD_VsdWsd = 0x10,
OP2_MOVPS_VpsWps = 0x10,
OP2_MOVSD_WsdVsd = 0x11,
OP2_MOVPS_WpsVps = 0x11,
OP2_UNPCKLPS_VsdWsd = 0x14,
OP2_MOVAPD_VsdWsd = 0x28,
OP2_MOVAPS_VsdWsd = 0x28,
@ -2867,6 +2869,32 @@ public:
m_formatter.twoByteOp(OP2_MOVAPS_VsdWsd, (RegisterID)dst, base, index, scale, offset);
}
void movups_rm(XMMRegisterID src, int offset, RegisterID base)
{
spew("movups %s, %s0x%x(%s)",
nameFPReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base));
m_formatter.twoByteOp(OP2_MOVPS_WpsVps, (RegisterID)src, base, offset);
}
void movups_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
spew("movups %s, %d(%s,%s,%d)",
nameFPReg(src), offset, nameIReg(base), nameIReg(index), 1<<scale);
m_formatter.twoByteOp(OP2_MOVPS_WpsVps, (RegisterID)src, base, index, scale, offset);
}
void movups_mr(int offset, RegisterID base, XMMRegisterID dst)
{
spew("movups %s0x%x(%s), %s",
PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst));
m_formatter.twoByteOp(OP2_MOVPS_VpsWps, (RegisterID)dst, base, offset);
}
void movups_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
{
spew("movups %d(%s,%s,%d), %s",
offset, nameIReg(base), nameIReg(index), 1<<scale, nameFPReg(dst));
m_formatter.twoByteOp(OP2_MOVPS_VpsWps, (RegisterID)dst, base, index, scale, offset);
}
void movapd_rr(XMMRegisterID src, XMMRegisterID dst)
{
spew("movapd %s, %s",

26
js/src/jit/shared/Assembler-x86-shared.h
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@ -439,6 +439,32 @@ class AssemblerX86Shared : public AssemblerShared
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
void movups(const Operand &src, FloatRegister dest) {
JS_ASSERT(HasSSE2());
switch (src.kind()) {
case Operand::MEM_REG_DISP:
masm.movups_mr(src.disp(), src.base(), dest.code());
break;
case Operand::MEM_SCALE:
masm.movups_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
break;
default:
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
void movups(FloatRegister src, const Operand &dest) {
JS_ASSERT(HasSSE2());
switch (dest.kind()) {
case Operand::MEM_REG_DISP:
masm.movups_rm(src.code(), dest.disp(), dest.base());
break;
case Operand::MEM_SCALE:
masm.movups_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
break;
default:
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
// movsd and movss are only provided in load/store form since the
// register-to-register form has different semantics (it doesn't clobber

6
js/src/jit/shared/MacroAssembler-x86-shared.h
View File

@ -492,6 +492,12 @@ class MacroAssemblerX86Shared : public Assembler
void moveAlignedFloat32x4(FloatRegister src, FloatRegister dest) {
movaps(src, dest);
}
void loadUnalignedFloat32x4(const Address &src, FloatRegister dest) {
movups(Operand(src), dest);
}
void storeUnalignedFloat32x4(FloatRegister src, const Address &dest) {
movups(src, Operand(dest));
}
void moveFloatAsDouble(Register src, FloatRegister dest) {
movd(src, dest);