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Bug 964797 - Odin ARM: Correct the VCVT instructions encoding of the fraction bits. r=mjrosenb
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@ -2169,7 +2169,7 @@ Assembler::as_vcvtFixed(VFPRegister vd, bool isSigned, uint32_t fixedPoint, bool
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int32_t imm5 = fixedPoint;
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imm5 = (sx ? 32 : 16) - imm5;
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JS_ASSERT(imm5 >= 0);
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imm5 = imm5 >> 1 | (imm5 & 1) << 6;
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imm5 = imm5 >> 1 | (imm5 & 1) << 5;
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return writeVFPInst(sf, 0x02BA0040 | VD(vd) | toFixed << 18 | sx << 7 |
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(!isSigned) << 16 | imm5 | c);
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}
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