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Bug 1421244: Remove more ARMv6 dead code; r=lth
MozReview-Commit-ID: FkeXdjIcffl --HG-- extra : rebase_source : eb168dfa352f94153f78616dfb1efa537c797ddb
This commit is contained in:
Benjamin Bouvier
parent
7c8fe68f05
commit
939fff3f0e
@ -4193,22 +4193,6 @@ MacroAssemblerARMCompat::computePointer<Address>(const Address& src, Register r)
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} // namespace jit
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} // namespace js
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template<typename T>
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void
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MacroAssemblerARMCompat::compareExchange(int nbytes, bool signExtend, const T& mem,
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Register oldval, Register newval, Register output)
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{
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// If LDREXB/H and STREXB/H are not available we use the
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// word-width operations with read-modify-add. That does not
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// abstract well, so fork.
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//
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// Bug 1077321: We may further optimize for ARMv8 (AArch32) here.
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if (nbytes < 4 && !HasLDSTREXBHD())
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compareExchangeARMv6(nbytes, signExtend, mem, oldval, newval, output);
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else
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compareExchangeARMv7(nbytes, signExtend, mem, oldval, newval, output);
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}
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// General algorithm:
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//
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// ... ptr, <addr> ; compute address of item
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@ -4232,8 +4216,8 @@ MacroAssemblerARMCompat::compareExchange(int nbytes, bool signExtend, const T& m
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template<typename T>
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void
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MacroAssemblerARMCompat::compareExchangeARMv7(int nbytes, bool signExtend, const T& mem,
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Register oldval, Register newval, Register output)
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MacroAssemblerARMCompat::compareExchange(int nbytes, bool signExtend, const T& mem,
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Register oldval, Register newval, Register output)
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{
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Label again;
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Label done;
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@ -4293,16 +4277,6 @@ MacroAssemblerARMCompat::compareExchangeARMv7(int nbytes, bool signExtend, const
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asMasm().memoryBarrier(MembarFull);
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}
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template<typename T>
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void
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MacroAssemblerARMCompat::compareExchangeARMv6(int nbytes, bool signExtend, const T& mem,
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Register oldval, Register newval, Register output)
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{
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// Bug 1077318: Must use read-modify-write with LDREX / STREX.
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MOZ_ASSERT(nbytes == 1 || nbytes == 2);
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MOZ_CRASH("NYI");
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}
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template void
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js::jit::MacroAssemblerARMCompat::compareExchange(int nbytes, bool signExtend,
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const Address& address, Register oldval,
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@ -4317,22 +4291,7 @@ void
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MacroAssemblerARMCompat::atomicExchange(int nbytes, bool signExtend, const T& mem,
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Register value, Register output)
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{
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// If LDREXB/H and STREXB/H are not available we use the
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// word-width operations with read-modify-add. That does not
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// abstract well, so fork.
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//
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// Bug 1077321: We may further optimize for ARMv8 (AArch32) here.
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if (nbytes < 4 && !HasLDSTREXBHD())
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atomicExchangeARMv6(nbytes, signExtend, mem, value, output);
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else
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atomicExchangeARMv7(nbytes, signExtend, mem, value, output);
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}
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template<typename T>
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void
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MacroAssemblerARMCompat::atomicExchangeARMv7(int nbytes, bool signExtend, const T& mem,
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Register value, Register output)
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{
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Label again;
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Label done;
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@ -4372,16 +4331,6 @@ MacroAssemblerARMCompat::atomicExchangeARMv7(int nbytes, bool signExtend, const
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asMasm().memoryBarrier(MembarFull);
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}
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template<typename T>
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void
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MacroAssemblerARMCompat::atomicExchangeARMv6(int nbytes, bool signExtend, const T& mem,
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Register value, Register output)
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{
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// Bug 1077318: Must use read-modify-write with LDREX / STREX.
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MOZ_ASSERT(nbytes == 1 || nbytes == 2);
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MOZ_CRASH("NYI");
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}
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template void
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js::jit::MacroAssemblerARMCompat::atomicExchange(int nbytes, bool signExtend,
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const Address& address, Register value,
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@ -4428,21 +4377,6 @@ void
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MacroAssemblerARMCompat::atomicFetchOp(int nbytes, bool signExtend, AtomicOp op,
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const Register& value, const T& mem, Register flagTemp,
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Register output)
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{
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// Fork for non-word operations on ARMv6.
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//
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// Bug 1077321: We may further optimize for ARMv8 (AArch32) here.
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if (nbytes < 4 && !HasLDSTREXBHD())
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atomicFetchOpARMv6(nbytes, signExtend, op, value, mem, flagTemp, output);
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else
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atomicFetchOpARMv7(nbytes, signExtend, op, value, mem, flagTemp, output);
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}
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template<typename T>
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void
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MacroAssemblerARMCompat::atomicFetchOpARMv7(int nbytes, bool signExtend, AtomicOp op,
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const Register& value, const T& mem, Register flagTemp,
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Register output)
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{
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MOZ_ASSERT(flagTemp != InvalidReg);
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MOZ_ASSERT(output != value);
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@ -4508,43 +4442,6 @@ MacroAssemblerARMCompat::atomicFetchOpARMv7(int nbytes, bool signExtend, AtomicO
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asMasm().memoryBarrier(MembarFull);
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}
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template<typename T>
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void
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MacroAssemblerARMCompat::atomicFetchOpARMv6(int nbytes, bool signExtend, AtomicOp op,
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const Register& value, const T& mem, Register flagTemp,
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Register output)
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{
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// Bug 1077318: Must use read-modify-write with LDREX / STREX.
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MOZ_ASSERT(nbytes == 1 || nbytes == 2);
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MOZ_CRASH("NYI");
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}
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template<typename T>
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void
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MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Register& value,
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const T& mem, Register flagTemp)
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{
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// Fork for non-word operations on ARMv6.
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//
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// Bug 1077321: We may further optimize for ARMv8 (AArch32) here.
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if (nbytes < 4 && !HasLDSTREXBHD())
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atomicEffectOpARMv6(nbytes, op, value, mem, flagTemp);
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else
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atomicEffectOpARMv7(nbytes, op, value, mem, flagTemp);
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}
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template<typename T>
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void
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MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Imm32& value,
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const T& mem, Register flagTemp)
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{
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// The Imm32 case is not needed yet because lowering always forces
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// the value into a register at present (bug 1077317).
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//
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// This would be useful for immediates small enough to fit into
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// add/sub/and/or/xor.
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MOZ_CRASH("NYI");
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}
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// Uses both scratch registers, one for the address and one for a temp,
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// but needs two temps for strex:
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//
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@ -4559,8 +4456,8 @@ MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Imm32& va
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template<typename T>
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void
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MacroAssemblerARMCompat::atomicEffectOpARMv7(int nbytes, AtomicOp op, const Register& value,
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const T& mem, Register flagTemp)
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MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Register& value,
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const T& mem, Register flagTemp)
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{
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MOZ_ASSERT(flagTemp != InvalidReg);
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@ -4622,11 +4519,14 @@ MacroAssemblerARMCompat::atomicEffectOpARMv7(int nbytes, AtomicOp op, const Regi
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template<typename T>
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void
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MacroAssemblerARMCompat::atomicEffectOpARMv6(int nbytes, AtomicOp op, const Register& value,
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const T& mem, Register flagTemp)
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MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Imm32& value,
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const T& mem, Register flagTemp)
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{
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// Bug 1077318: Must use read-modify-write with LDREX / STREX.
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MOZ_ASSERT(nbytes == 1 || nbytes == 2);
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// The Imm32 case is not needed yet because lowering always forces
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// the value into a register at present (bug 1077317).
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//
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// This would be useful for immediates small enough to fit into
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// add/sub/and/or/xor.
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MOZ_CRASH("NYI");
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}
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@ -1111,38 +1111,14 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
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template<typename T>
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Register computePointer(const T& src, Register r);
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template<typename T>
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void compareExchangeARMv6(int nbytes, bool signExtend, const T& mem, Register oldval,
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Register newval, Register output);
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template<typename T>
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void compareExchangeARMv7(int nbytes, bool signExtend, const T& mem, Register oldval,
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Register newval, Register output);
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template<typename T>
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void compareExchange(int nbytes, bool signExtend, const T& address, Register oldval,
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Register newval, Register output);
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template<typename T>
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void atomicExchangeARMv6(int nbytes, bool signExtend, const T& mem, Register value,
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Register output);
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template<typename T>
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void atomicExchangeARMv7(int nbytes, bool signExtend, const T& mem, Register value,
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Register output);
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template<typename T>
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void atomicExchange(int nbytes, bool signExtend, const T& address, Register value,
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Register output);
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template<typename T>
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void atomicFetchOpARMv6(int nbytes, bool signExtend, AtomicOp op, const Register& value,
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const T& mem, Register flagTemp, Register output);
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template<typename T>
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void atomicFetchOpARMv7(int nbytes, bool signExtend, AtomicOp op, const Register& value,
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const T& mem, Register flagTemp, Register output);
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template<typename T>
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void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, const Imm32& value,
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const T& address, Register flagTemp, Register output);
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@ -1151,14 +1127,6 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
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void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, const Register& value,
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const T& address, Register flagTemp, Register output);
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template<typename T>
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void atomicEffectOpARMv6(int nbytes, AtomicOp op, const Register& value, const T& address,
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Register flagTemp);
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template<typename T>
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void atomicEffectOpARMv7(int nbytes, AtomicOp op, const Register& value, const T& address,
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Register flagTemp);
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template<typename T>
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void atomicEffectOp(int nbytes, AtomicOp op, const Imm32& value, const T& address,
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Register flagTemp);
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