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https://github.com/mozilla/gecko-dev.git
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Bug 1436955 - ARM64 Simulator, bugfixes and wasm support. r=bbouvier
- fix a bug where the wrong register was picked up - support wasm out-of-bounds traps - support wasm illegal instruction traps - support (float,float)->float callout signature - support wait() and wake() callout signatures --HG-- extra : rebase_source : 9ec124e9e629da245360a80a4a6974d71c9a87c8 extra : source : ba2afb5aa6915b1112d0f58ab653949bec8d07fc
This commit is contained in:
Lars T Hansen
parent
b9354f830a
commit
9b260640e7
@ -33,15 +33,16 @@
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#include "threading/LockGuard.h"
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#include "vm/Runtime.h"
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#include "wasm/WasmInstance.h"
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#include "wasm/WasmProcess.h"
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#include "wasm/WasmSignalHandlers.h"
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js::jit::SimulatorProcess* js::jit::SimulatorProcess::singleton_ = nullptr;
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namespace vixl {
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using mozilla::DebugOnly;
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using js::jit::ABIFunctionType;
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using js::jit::JitActivation;
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using js::jit::SimulatorProcess;
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Simulator::Simulator(JSContext* cx, Decoder* decoder, FILE* stream)
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@ -218,13 +219,13 @@ uintptr_t* Simulator::addressOfStackLimit() {
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bool Simulator::overRecursed(uintptr_t newsp) const {
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if (newsp)
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newsp = xreg(31, Reg31IsStackPointer);
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newsp = get_sp();
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return newsp <= stackLimit();
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}
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bool Simulator::overRecursedWithExtra(uint32_t extra) const {
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uintptr_t newsp = xreg(31, Reg31IsStackPointer) - extra;
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uintptr_t newsp = get_sp() - extra;
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return newsp <= stackLimit();
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}
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@ -235,31 +236,91 @@ void Simulator::trigger_wasm_interrupt() {
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}
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static inline JitActivation*
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GetJitActivation(JSContext* cx)
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{
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if (!js::wasm::CodeExists)
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return nullptr;
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if (!cx->activation() || !cx->activation()->isJit())
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return nullptr;
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return cx->activation()->asJit();
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}
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JS::ProfilingFrameIterator::RegisterState
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Simulator::registerState()
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{
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JS::ProfilingFrameIterator::RegisterState state;
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state.pc = (uint8_t*) get_pc();
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state.fp = (uint8_t*) get_fp();
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state.lr = (uint8_t*) get_lr();
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state.sp = (uint8_t*) get_sp();
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return state;
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}
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// The signal handler only redirects the PC to the interrupt stub when the PC is
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// in function code. However, this guard is racy for the ARM simulator since the
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// signal handler samples PC in the middle of simulating an instruction and thus
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// the current PC may have advanced once since the signal handler's guard. So we
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// re-check here.
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void Simulator::handle_wasm_interrupt() {
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void Simulator::handle_wasm_interrupt()
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{
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if (!js::wasm::CodeExists)
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return;
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uint8_t* pc = (uint8_t*)get_pc();
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uint8_t* fp = (uint8_t*)xreg(30);
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const js::wasm::ModuleSegment* ms = nullptr;
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if (!js::wasm::InInterruptibleCode(cx_, pc, &ms))
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return;
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JS::ProfilingFrameIterator::RegisterState state;
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state.pc = pc;
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state.fp = fp;
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state.lr = (uint8_t*) xreg(30);
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state.sp = (uint8_t*) xreg(31);
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JitActivation* act = GetJitActivation(cx_);
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if (!act)
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return;
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if (!cx_->activation_->asJit()->startWasmInterrupt(state))
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if (!act->startWasmInterrupt(registerState()))
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return;
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set_pc((Instruction*)ms->interruptCode());
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}
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bool
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Simulator::handle_wasm_seg_fault(uintptr_t addr, unsigned numBytes)
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{
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JitActivation* act = GetJitActivation(cx_);
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if (!act)
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return false;
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uint8_t* pc = (uint8_t*)get_pc();
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uint8_t* fp = (uint8_t*)get_fp();
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const js::wasm::CodeSegment* segment = js::wasm::LookupCodeSegment(pc);
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if (!segment)
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return false;
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const js::wasm::ModuleSegment* moduleSegment = segment->asModule();
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js::wasm::Instance* instance = js::wasm::LookupFaultingInstance(*moduleSegment, pc, fp);
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if (!instance)
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return false;
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MOZ_RELEASE_ASSERT(&instance->code() == &moduleSegment->code());
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if (!instance->memoryAccessInGuardRegion((uint8_t*)addr, numBytes))
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return false;
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const js::wasm::MemoryAccess* memoryAccess = instance->code().lookupMemoryAccess(pc);
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if (!memoryAccess) {
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if (!act->startWasmInterrupt(registerState()))
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MOZ_CRASH("Cannot start interrupt");
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if (!instance->code().containsCodePC(pc))
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MOZ_CRASH("Cannot map PC to trap handler");
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set_pc((Instruction*)moduleSegment->outOfBoundsCode());
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return true;
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}
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MOZ_ASSERT(memoryAccess->hasTrapOutOfLineCode());
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set_pc((Instruction*)memoryAccess->trapOutOfLineCode(moduleSegment->base()));
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return true;
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}
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int64_t Simulator::call(uint8_t* entry, int argument_count, ...) {
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va_list parameters;
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@ -303,12 +364,12 @@ int64_t Simulator::call(uint8_t* entry, int argument_count, ...) {
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va_end(parameters);
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// Call must transition back to native code on exit.
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VIXL_ASSERT(xreg(30) == int64_t(kEndOfSimAddress));
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VIXL_ASSERT(get_lr() == int64_t(kEndOfSimAddress));
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// Execute the simulation.
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DebugOnly<int64_t> entryStack = xreg(31, Reg31IsStackPointer);
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DebugOnly<int64_t> entryStack = get_sp();
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RunFrom((Instruction*)entry);
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DebugOnly<int64_t> exitStack = xreg(31, Reg31IsStackPointer);
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DebugOnly<int64_t> exitStack = get_sp();
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VIXL_ASSERT(entryStack == exitStack);
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int64_t result = xreg(0);
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@ -403,6 +464,29 @@ void* Simulator::RedirectNativeFunction(void* nativeFunction, ABIFunctionType ty
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return redirection->addressOfSvcInstruction();
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}
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bool
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Simulator::handle_wasm_ill_fault()
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{
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JitActivation* act = GetJitActivation(cx_);
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if (!act)
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return false;
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uint8_t* pc = (uint8_t*)get_pc();
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const js::wasm::CodeSegment* segment = js::wasm::LookupCodeSegment(pc);
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if (!segment || !segment->isModule())
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return false;
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const js::wasm::ModuleSegment* moduleSegment = segment->asModule();
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js::wasm::Trap trap;
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js::wasm::BytecodeOffset bytecode;
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if (!moduleSegment->code().lookupTrap(pc, &trap, &bytecode))
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return false;
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act->startWasmTrap(trap, bytecode.offset, registerState());
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set_pc((Instruction*)moduleSegment->trapCode());
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return true;
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}
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void Simulator::VisitException(const Instruction* instr) {
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switch (instr->Mask(ExceptionMask)) {
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@ -415,7 +499,8 @@ void Simulator::VisitException(const Instruction* instr) {
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case HLT:
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switch (instr->ImmException()) {
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case kUnreachableOpcode:
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DoUnreachable(instr);
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if (!handle_wasm_ill_fault())
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DoUnreachable(instr);
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return;
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case kTraceOpcode:
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DoTrace(instr);
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@ -439,12 +524,12 @@ void Simulator::VisitException(const Instruction* instr) {
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return;
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case kMarkStackPointer: {
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js::AutoEnterOOMUnsafeRegion oomUnsafe;
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if (!spStack_.append(xreg(31, Reg31IsStackPointer)))
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if (!spStack_.append(get_sp()))
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oomUnsafe.crash("tracking stack for ARM64 simulator");
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return;
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}
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case kCheckStackPointer: {
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int64_t current = xreg(31, Reg31IsStackPointer);
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int64_t current = get_sp();
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int64_t expected = spStack_.popCopy();
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VIXL_ASSERT(current == expected);
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return;
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@ -492,6 +577,10 @@ typedef int64_t (*Prototype_General7)(int64_t arg0, int64_t arg1, int64_t arg2,
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int64_t arg4, int64_t arg5, int64_t arg6);
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typedef int64_t (*Prototype_General8)(int64_t arg0, int64_t arg1, int64_t arg2, int64_t arg3,
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int64_t arg4, int64_t arg5, int64_t arg6, int64_t arg7);
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typedef int64_t (*Prototype_GeneralGeneralGeneralInt64)(int64_t arg0, int32_t arg1, int32_t arg2,
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int64_t arg3);
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typedef int64_t (*Prototype_GeneralGeneralInt64Int64)(int64_t arg0, int32_t arg1, int64_t arg2,
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int64_t arg3);
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typedef int64_t (*Prototype_Int_Double)(double arg0);
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typedef int64_t (*Prototype_Int_IntDouble)(int32_t arg0, double arg1);
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@ -500,6 +589,7 @@ typedef int64_t (*Prototype_Int_IntDoubleIntInt)(uint64_t arg0, double arg1,
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uint64_t arg2, uint64_t arg3);
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typedef float (*Prototype_Float32_Float32)(float arg0);
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typedef float (*Prototype_Float32_Float32Float32)(float arg0, float arg1);
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typedef double (*Prototype_Double_None)();
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typedef double (*Prototype_Double_Double)(double arg0);
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@ -538,7 +628,7 @@ Simulator::VisitCallRedirection(const Instruction* instr)
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DebugOnly<int64_t> x27 = xreg(27);
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DebugOnly<int64_t> x28 = xreg(28);
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DebugOnly<int64_t> x29 = xreg(29);
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DebugOnly<int64_t> savedSP = xreg(31, Reg31IsStackPointer);
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DebugOnly<int64_t> savedSP = get_sp();
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// Remember LR for returning from the "call".
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int64_t savedLR = xreg(30);
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@ -561,6 +651,7 @@ Simulator::VisitCallRedirection(const Instruction* instr)
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double d2 = dreg(2);
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double d3 = dreg(3);
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float s0 = sreg(0);
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float s1 = sreg(1);
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// Dispatch the call and set the return value.
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switch (redir->type()) {
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@ -610,6 +701,16 @@ Simulator::VisitCallRedirection(const Instruction* instr)
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setGPR64Result(ret);
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break;
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}
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case js::jit::Args_Int_GeneralGeneralGeneralInt64: {
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int64_t ret = reinterpret_cast<Prototype_GeneralGeneralGeneralInt64>(nativeFn)(x0, x1, x2, x3);
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setGPR64Result(ret);
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break;
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}
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case js::jit::Args_Int_GeneralGeneralInt64Int64: {
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int64_t ret = reinterpret_cast<Prototype_GeneralGeneralInt64Int64>(nativeFn)(x0, x1, x2, x3);
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setGPR64Result(ret);
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break;
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}
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// Cases with GPR return type. This can be int32 or int64, but int64 is a safer assumption.
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case js::jit::Args_Int_Double: {
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@ -641,6 +742,11 @@ Simulator::VisitCallRedirection(const Instruction* instr)
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setFP32Result(ret);
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break;
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}
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case js::jit::Args_Float32_Float32Float32: {
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float ret = reinterpret_cast<Prototype_Float32_Float32Float32>(nativeFn)(s0, s1);
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setFP32Result(ret);
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break;
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}
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// Cases with double return type.
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case js::jit::Args_Double_None: {
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@ -705,7 +811,7 @@ Simulator::VisitCallRedirection(const Instruction* instr)
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VIXL_ASSERT(xreg(29) == x29);
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// Assert that the stack is unchanged.
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VIXL_ASSERT(savedSP == xreg(31, Reg31IsStackPointer));
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VIXL_ASSERT(savedSP == get_sp());
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// Simulate a return.
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set_lr(savedLR);
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@ -1012,7 +1012,38 @@ void Simulator::VisitLoadStoreRegisterOffset(const Instruction* instr) {
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LoadStoreHelper(instr, offset, Offset);
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}
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template<typename T>
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static T Faulted() {
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return ~0;
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}
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template<>
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Simulator::qreg_t Faulted() {
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static_assert(kQRegSizeInBytes == 16, "Known constraint");
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static Simulator::qreg_t dummy = { {
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255, 255, 255, 255, 255, 255, 255, 255,
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255, 255, 255, 255, 255, 255, 255, 255
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} };
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return dummy;
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}
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template<typename T> T
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Simulator::Read(uintptr_t address)
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{
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address = Memory::AddressUntag(address);
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if (handle_wasm_seg_fault(address, sizeof(T)))
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return Faulted<T>();
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return Memory::Read<T>(address);
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}
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template <typename T> void
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Simulator::Write(uintptr_t address, T value)
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{
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address = Memory::AddressUntag(address);
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if (handle_wasm_seg_fault(address, sizeof(T)))
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return;
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Memory::Write<T>(address, value);
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}
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void Simulator::LoadStoreHelper(const Instruction* instr,
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int64_t offset,
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@ -1023,43 +1054,43 @@ void Simulator::LoadStoreHelper(const Instruction* instr,
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LoadStoreOp op = static_cast<LoadStoreOp>(instr->Mask(LoadStoreMask));
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switch (op) {
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case LDRB_w:
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set_wreg(srcdst, Memory::Read<uint8_t>(address), NoRegLog); break;
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set_wreg(srcdst, Read<uint8_t>(address), NoRegLog); break;
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case LDRH_w:
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set_wreg(srcdst, Memory::Read<uint16_t>(address), NoRegLog); break;
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set_wreg(srcdst, Read<uint16_t>(address), NoRegLog); break;
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case LDR_w:
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set_wreg(srcdst, Memory::Read<uint32_t>(address), NoRegLog); break;
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set_wreg(srcdst, Read<uint32_t>(address), NoRegLog); break;
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case LDR_x:
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set_xreg(srcdst, Memory::Read<uint64_t>(address), NoRegLog); break;
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set_xreg(srcdst, Read<uint64_t>(address), NoRegLog); break;
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case LDRSB_w:
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set_wreg(srcdst, Memory::Read<int8_t>(address), NoRegLog); break;
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set_wreg(srcdst, Read<int8_t>(address), NoRegLog); break;
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case LDRSH_w:
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set_wreg(srcdst, Memory::Read<int16_t>(address), NoRegLog); break;
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set_wreg(srcdst, Read<int16_t>(address), NoRegLog); break;
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case LDRSB_x:
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set_xreg(srcdst, Memory::Read<int8_t>(address), NoRegLog); break;
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set_xreg(srcdst, Read<int8_t>(address), NoRegLog); break;
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case LDRSH_x:
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set_xreg(srcdst, Memory::Read<int16_t>(address), NoRegLog); break;
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set_xreg(srcdst, Read<int16_t>(address), NoRegLog); break;
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case LDRSW_x:
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set_xreg(srcdst, Memory::Read<int32_t>(address), NoRegLog); break;
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set_xreg(srcdst, Read<int32_t>(address), NoRegLog); break;
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case LDR_b:
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set_breg(srcdst, Memory::Read<uint8_t>(address), NoRegLog); break;
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set_breg(srcdst, Read<uint8_t>(address), NoRegLog); break;
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case LDR_h:
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set_hreg(srcdst, Memory::Read<uint16_t>(address), NoRegLog); break;
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set_hreg(srcdst, Read<uint16_t>(address), NoRegLog); break;
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case LDR_s:
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set_sreg(srcdst, Memory::Read<float>(address), NoRegLog); break;
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set_sreg(srcdst, Read<float>(address), NoRegLog); break;
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case LDR_d:
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set_dreg(srcdst, Memory::Read<double>(address), NoRegLog); break;
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set_dreg(srcdst, Read<double>(address), NoRegLog); break;
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case LDR_q:
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set_qreg(srcdst, Memory::Read<qreg_t>(address), NoRegLog); break;
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set_qreg(srcdst, Read<qreg_t>(address), NoRegLog); break;
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case STRB_w: Memory::Write<uint8_t>(address, wreg(srcdst)); break;
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case STRH_w: Memory::Write<uint16_t>(address, wreg(srcdst)); break;
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case STR_w: Memory::Write<uint32_t>(address, wreg(srcdst)); break;
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case STR_x: Memory::Write<uint64_t>(address, xreg(srcdst)); break;
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case STR_b: Memory::Write<uint8_t>(address, breg(srcdst)); break;
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case STR_h: Memory::Write<uint16_t>(address, hreg(srcdst)); break;
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case STR_s: Memory::Write<float>(address, sreg(srcdst)); break;
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case STR_d: Memory::Write<double>(address, dreg(srcdst)); break;
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case STR_q: Memory::Write<qreg_t>(address, qreg(srcdst)); break;
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case STRB_w: Write<uint8_t>(address, wreg(srcdst)); break;
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case STRH_w: Write<uint16_t>(address, wreg(srcdst)); break;
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case STR_w: Write<uint32_t>(address, wreg(srcdst)); break;
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case STR_x: Write<uint64_t>(address, xreg(srcdst)); break;
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case STR_b: Write<uint8_t>(address, breg(srcdst)); break;
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case STR_h: Write<uint16_t>(address, hreg(srcdst)); break;
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case STR_s: Write<float>(address, sreg(srcdst)); break;
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case STR_d: Write<double>(address, dreg(srcdst)); break;
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case STR_q: Write<qreg_t>(address, qreg(srcdst)); break;
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// Ignore prfm hint instructions.
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case PRFM: break;
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@ -1129,58 +1160,58 @@ void Simulator::LoadStorePairHelper(const Instruction* instr,
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// Use NoRegLog to suppress the register trace (LOG_REGS, LOG_FP_REGS). We
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// will print a more detailed log.
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case LDP_w: {
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set_wreg(rt, Memory::Read<uint32_t>(address), NoRegLog);
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set_wreg(rt2, Memory::Read<uint32_t>(address2), NoRegLog);
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set_wreg(rt, Read<uint32_t>(address), NoRegLog);
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set_wreg(rt2, Read<uint32_t>(address2), NoRegLog);
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break;
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}
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case LDP_s: {
|
||||
set_sreg(rt, Memory::Read<float>(address), NoRegLog);
|
||||
set_sreg(rt2, Memory::Read<float>(address2), NoRegLog);
|
||||
set_sreg(rt, Read<float>(address), NoRegLog);
|
||||
set_sreg(rt2, Read<float>(address2), NoRegLog);
|
||||
break;
|
||||
}
|
||||
case LDP_x: {
|
||||
set_xreg(rt, Memory::Read<uint64_t>(address), NoRegLog);
|
||||
set_xreg(rt2, Memory::Read<uint64_t>(address2), NoRegLog);
|
||||
set_xreg(rt, Read<uint64_t>(address), NoRegLog);
|
||||
set_xreg(rt2, Read<uint64_t>(address2), NoRegLog);
|
||||
break;
|
||||
}
|
||||
case LDP_d: {
|
||||
set_dreg(rt, Memory::Read<double>(address), NoRegLog);
|
||||
set_dreg(rt2, Memory::Read<double>(address2), NoRegLog);
|
||||
set_dreg(rt, Read<double>(address), NoRegLog);
|
||||
set_dreg(rt2, Read<double>(address2), NoRegLog);
|
||||
break;
|
||||
}
|
||||
case LDP_q: {
|
||||
set_qreg(rt, Memory::Read<qreg_t>(address), NoRegLog);
|
||||
set_qreg(rt2, Memory::Read<qreg_t>(address2), NoRegLog);
|
||||
set_qreg(rt, Read<qreg_t>(address), NoRegLog);
|
||||
set_qreg(rt2, Read<qreg_t>(address2), NoRegLog);
|
||||
break;
|
||||
}
|
||||
case LDPSW_x: {
|
||||
set_xreg(rt, Memory::Read<int32_t>(address), NoRegLog);
|
||||
set_xreg(rt2, Memory::Read<int32_t>(address2), NoRegLog);
|
||||
set_xreg(rt, Read<int32_t>(address), NoRegLog);
|
||||
set_xreg(rt2, Read<int32_t>(address2), NoRegLog);
|
||||
break;
|
||||
}
|
||||
case STP_w: {
|
||||
Memory::Write<uint32_t>(address, wreg(rt));
|
||||
Memory::Write<uint32_t>(address2, wreg(rt2));
|
||||
Write<uint32_t>(address, wreg(rt));
|
||||
Write<uint32_t>(address2, wreg(rt2));
|
||||
break;
|
||||
}
|
||||
case STP_s: {
|
||||
Memory::Write<float>(address, sreg(rt));
|
||||
Memory::Write<float>(address2, sreg(rt2));
|
||||
Write<float>(address, sreg(rt));
|
||||
Write<float>(address2, sreg(rt2));
|
||||
break;
|
||||
}
|
||||
case STP_x: {
|
||||
Memory::Write<uint64_t>(address, xreg(rt));
|
||||
Memory::Write<uint64_t>(address2, xreg(rt2));
|
||||
Write<uint64_t>(address, xreg(rt));
|
||||
Write<uint64_t>(address2, xreg(rt2));
|
||||
break;
|
||||
}
|
||||
case STP_d: {
|
||||
Memory::Write<double>(address, dreg(rt));
|
||||
Memory::Write<double>(address2, dreg(rt2));
|
||||
Write<double>(address, dreg(rt));
|
||||
Write<double>(address2, dreg(rt2));
|
||||
break;
|
||||
}
|
||||
case STP_q: {
|
||||
Memory::Write<qreg_t>(address, qreg(rt));
|
||||
Memory::Write<qreg_t>(address2, qreg(rt2));
|
||||
Write<qreg_t>(address, qreg(rt));
|
||||
Write<qreg_t>(address2, qreg(rt2));
|
||||
break;
|
||||
}
|
||||
default: VIXL_UNREACHABLE();
|
||||
@ -1276,32 +1307,32 @@ void Simulator::VisitLoadStoreExclusive(const Instruction* instr) {
|
||||
case LDXRB_w:
|
||||
case LDAXRB_w:
|
||||
case LDARB_w:
|
||||
set_wreg(rt, Memory::Read<uint8_t>(address), NoRegLog);
|
||||
set_wreg(rt, Read<uint8_t>(address), NoRegLog);
|
||||
break;
|
||||
case LDXRH_w:
|
||||
case LDAXRH_w:
|
||||
case LDARH_w:
|
||||
set_wreg(rt, Memory::Read<uint16_t>(address), NoRegLog);
|
||||
set_wreg(rt, Read<uint16_t>(address), NoRegLog);
|
||||
break;
|
||||
case LDXR_w:
|
||||
case LDAXR_w:
|
||||
case LDAR_w:
|
||||
set_wreg(rt, Memory::Read<uint32_t>(address), NoRegLog);
|
||||
set_wreg(rt, Read<uint32_t>(address), NoRegLog);
|
||||
break;
|
||||
case LDXR_x:
|
||||
case LDAXR_x:
|
||||
case LDAR_x:
|
||||
set_xreg(rt, Memory::Read<uint64_t>(address), NoRegLog);
|
||||
set_xreg(rt, Read<uint64_t>(address), NoRegLog);
|
||||
break;
|
||||
case LDXP_w:
|
||||
case LDAXP_w:
|
||||
set_wreg(rt, Memory::Read<uint32_t>(address), NoRegLog);
|
||||
set_wreg(rt2, Memory::Read<uint32_t>(address + element_size), NoRegLog);
|
||||
set_wreg(rt, Read<uint32_t>(address), NoRegLog);
|
||||
set_wreg(rt2, Read<uint32_t>(address + element_size), NoRegLog);
|
||||
break;
|
||||
case LDXP_x:
|
||||
case LDAXP_x:
|
||||
set_xreg(rt, Memory::Read<uint64_t>(address), NoRegLog);
|
||||
set_xreg(rt2, Memory::Read<uint64_t>(address + element_size), NoRegLog);
|
||||
set_xreg(rt, Read<uint64_t>(address), NoRegLog);
|
||||
set_xreg(rt2, Read<uint64_t>(address + element_size), NoRegLog);
|
||||
break;
|
||||
default:
|
||||
VIXL_UNREACHABLE();
|
||||
@ -1341,32 +1372,32 @@ void Simulator::VisitLoadStoreExclusive(const Instruction* instr) {
|
||||
case STXRB_w:
|
||||
case STLXRB_w:
|
||||
case STLRB_w:
|
||||
Memory::Write<uint8_t>(address, wreg(rt));
|
||||
Write<uint8_t>(address, wreg(rt));
|
||||
break;
|
||||
case STXRH_w:
|
||||
case STLXRH_w:
|
||||
case STLRH_w:
|
||||
Memory::Write<uint16_t>(address, wreg(rt));
|
||||
Write<uint16_t>(address, wreg(rt));
|
||||
break;
|
||||
case STXR_w:
|
||||
case STLXR_w:
|
||||
case STLR_w:
|
||||
Memory::Write<uint32_t>(address, wreg(rt));
|
||||
Write<uint32_t>(address, wreg(rt));
|
||||
break;
|
||||
case STXR_x:
|
||||
case STLXR_x:
|
||||
case STLR_x:
|
||||
Memory::Write<uint64_t>(address, xreg(rt));
|
||||
Write<uint64_t>(address, xreg(rt));
|
||||
break;
|
||||
case STXP_w:
|
||||
case STLXP_w:
|
||||
Memory::Write<uint32_t>(address, wreg(rt));
|
||||
Memory::Write<uint32_t>(address + element_size, wreg(rt2));
|
||||
Write<uint32_t>(address, wreg(rt));
|
||||
Write<uint32_t>(address + element_size, wreg(rt2));
|
||||
break;
|
||||
case STXP_x:
|
||||
case STLXP_x:
|
||||
Memory::Write<uint64_t>(address, xreg(rt));
|
||||
Memory::Write<uint64_t>(address + element_size, xreg(rt2));
|
||||
Write<uint64_t>(address, xreg(rt));
|
||||
Write<uint64_t>(address + element_size, xreg(rt2));
|
||||
break;
|
||||
default:
|
||||
VIXL_UNREACHABLE();
|
||||
@ -1393,27 +1424,27 @@ void Simulator::VisitLoadLiteral(const Instruction* instr) {
|
||||
// Use NoRegLog to suppress the register trace (LOG_REGS, LOG_VREGS), then
|
||||
// print a more detailed log.
|
||||
case LDR_w_lit:
|
||||
set_wreg(rt, Memory::Read<uint32_t>(address), NoRegLog);
|
||||
set_wreg(rt, Read<uint32_t>(address), NoRegLog);
|
||||
LogRead(address, rt, kPrintWReg);
|
||||
break;
|
||||
case LDR_x_lit:
|
||||
set_xreg(rt, Memory::Read<uint64_t>(address), NoRegLog);
|
||||
set_xreg(rt, Read<uint64_t>(address), NoRegLog);
|
||||
LogRead(address, rt, kPrintXReg);
|
||||
break;
|
||||
case LDR_s_lit:
|
||||
set_sreg(rt, Memory::Read<float>(address), NoRegLog);
|
||||
set_sreg(rt, Read<float>(address), NoRegLog);
|
||||
LogVRead(address, rt, kPrintSReg);
|
||||
break;
|
||||
case LDR_d_lit:
|
||||
set_dreg(rt, Memory::Read<double>(address), NoRegLog);
|
||||
set_dreg(rt, Read<double>(address), NoRegLog);
|
||||
LogVRead(address, rt, kPrintDReg);
|
||||
break;
|
||||
case LDR_q_lit:
|
||||
set_qreg(rt, Memory::Read<qreg_t>(address), NoRegLog);
|
||||
set_qreg(rt, Read<qreg_t>(address), NoRegLog);
|
||||
LogVRead(address, rt, kPrintReg1Q);
|
||||
break;
|
||||
case LDRSW_x_lit:
|
||||
set_xreg(rt, Memory::Read<int32_t>(address), NoRegLog);
|
||||
set_xreg(rt, Read<int32_t>(address), NoRegLog);
|
||||
LogRead(address, rt, kPrintWReg);
|
||||
break;
|
||||
|
||||
@ -2242,7 +2273,7 @@ void Simulator::SysOp_W(int op, int64_t val) {
|
||||
case CIVAC: {
|
||||
// Perform a dummy memory access to ensure that we have read access
|
||||
// to the specified address.
|
||||
volatile uint8_t y = Memory::Read<uint8_t>(val);
|
||||
volatile uint8_t y = Read<uint8_t>(val);
|
||||
USE(y);
|
||||
// TODO: Implement "case ZVA:".
|
||||
break;
|
||||
|
||||
@ -721,6 +721,9 @@ class Simulator : public DecoderVisitor {
|
||||
static bool supportsAtomics() {
|
||||
return true;
|
||||
}
|
||||
template<typename T> T Read(uintptr_t address);
|
||||
template <typename T> void Write(uintptr_t address_, T value);
|
||||
JS::ProfilingFrameIterator::RegisterState registerState();
|
||||
|
||||
void ResetState();
|
||||
|
||||
@ -731,6 +734,9 @@ class Simulator : public DecoderVisitor {
|
||||
// Simulation helpers.
|
||||
const Instruction* pc() const { return pc_; }
|
||||
const Instruction* get_pc() const { return pc_; }
|
||||
int64_t get_sp() const { return xreg(31, Reg31IsStackPointer); }
|
||||
int64_t get_lr() const { return xreg(30); }
|
||||
int64_t get_fp() const { return xreg(29); }
|
||||
|
||||
template <typename T>
|
||||
T get_pc_as() const { return reinterpret_cast<T>(const_cast<Instruction*>(pc())); }
|
||||
@ -742,6 +748,8 @@ class Simulator : public DecoderVisitor {
|
||||
|
||||
void trigger_wasm_interrupt();
|
||||
void handle_wasm_interrupt();
|
||||
bool handle_wasm_ill_fault();
|
||||
bool handle_wasm_seg_fault(uintptr_t addr, unsigned numBytes);
|
||||
|
||||
void increment_pc() {
|
||||
if (!pc_modified_) {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user