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Bug 1313336 - ARM64 integer masm instructions. r=jolesen

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--HG--
extra : rebase_source : 04acecb31e69d6a9a97c440947832394ae769b7d
extra : source : e7ee98d402228d9067228de881daceb8a14ced51
This commit is contained in:
Lars T Hansen 2018-01-16 14:00:36 +01:00
parent 35a182a852
commit a34d0087b4
1 changed files with 104 additions and 27 deletions
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131
js/src/jit/arm64/MacroAssembler-arm64-inl.h
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@ -164,7 +164,7 @@ MacroAssembler::and64(Imm64 imm, Register64 dest)
void
MacroAssembler::and64(Register64 src, Register64 dest)
{
MOZ_CRASH("NYI: and64");
And(ARMRegister(dest.reg, 64), ARMRegister(dest.reg, 64), ARMRegister(src.reg, 64));
}
void
@ -438,13 +438,13 @@ MacroAssembler::subPtr(const Address& addr, Register dest)
void
MacroAssembler::sub64(Register64 src, Register64 dest)
{
MOZ_CRASH("NYI: sub64");
Sub(ARMRegister(dest.reg, 64), ARMRegister(dest.reg, 64), ARMRegister(src.reg, 64));
}
void
MacroAssembler::sub64(Imm64 imm, Register64 dest)
{
MOZ_CRASH("NYI: sub64");
Sub(ARMRegister(dest.reg, 64), ARMRegister(dest.reg, 64), Operand(imm.value));
}
void
@ -462,7 +462,7 @@ MacroAssembler::subFloat32(FloatRegister src, FloatRegister dest)
void
MacroAssembler::mul32(Register rhs, Register srcDest)
{
MOZ_CRASH("NYI - mul32");
mul32(srcDest, rhs, srcDest, nullptr, nullptr);
}
void
@ -493,7 +493,8 @@ MacroAssembler::mul64(Imm64 imm, const Register64& dest)
void
MacroAssembler::mul64(const Register64& src, const Register64& dest, const Register temp)
{
MOZ_CRASH("NYI: mul64");
MOZ_ASSERT(temp == Register::Invalid());
Mul(ARMRegister(dest.reg, 64), ARMRegister(dest.reg, 64), ARMRegister(src.reg, 64));
}
void
@ -531,13 +532,26 @@ MacroAssembler::mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest)
void
MacroAssembler::quotient32(Register rhs, Register srcDest, bool isUnsigned)
{
MOZ_CRASH("NYI - quotient32");
if (isUnsigned)
Udiv(ARMRegister(srcDest, 32), ARMRegister(srcDest, 32), ARMRegister(rhs, 32));
else
Sdiv(ARMRegister(srcDest, 32), ARMRegister(srcDest, 32), ARMRegister(rhs, 32));
}
// This does not deal with x % 0 or INT_MIN % -1, the caller needs to filter
// those cases when they may occur.
void
MacroAssembler::remainder32(Register rhs, Register srcDest, bool isUnsigned)
{
MOZ_CRASH("NYI - remainder32");
vixl::UseScratchRegisterScope temps(this);
ARMRegister scratch = temps.AcquireW();
if (isUnsigned)
Udiv(scratch, ARMRegister(srcDest, 32), ARMRegister(rhs, 32));
else
Sdiv(scratch, ARMRegister(srcDest, 32), ARMRegister(rhs, 32));
Mul(scratch, scratch, ARMRegister(rhs, 32));
Sub(ARMRegister(srcDest, 32), ARMRegister(srcDest, 32), scratch);
}
void
@ -651,7 +665,7 @@ MacroAssembler::lshift64(Imm32 imm, Register64 dest)
void
MacroAssembler::lshift64(Register shift, Register64 srcDest)
{
MOZ_CRASH("NYI: lshift64");
Lsl(ARMRegister(srcDest.reg, 64), ARMRegister(srcDest.reg, 64), ARMRegister(shift, 64));
}
void
@ -724,19 +738,19 @@ MacroAssembler::rshift64(Imm32 imm, Register64 dest)
void
MacroAssembler::rshift64(Register shift, Register64 srcDest)
{
MOZ_CRASH("NYI: rshift64");
Lsr(ARMRegister(srcDest.reg, 64), ARMRegister(srcDest.reg, 64), ARMRegister(shift, 64));
}
void
MacroAssembler::rshift64Arithmetic(Imm32 imm, Register64 dest)
{
MOZ_CRASH("NYI: rshift64Arithmetic");
Asr(ARMRegister(dest.reg, 64), ARMRegister(dest.reg, 64), imm.value);
}
void
MacroAssembler::rshift64Arithmetic(Register shift, Register64 srcDest)
{
MOZ_CRASH("NYI: rshift64Arithmetic");
Asr(ARMRegister(srcDest.reg, 64), ARMRegister(srcDest.reg, 64), ARMRegister(shift, 64));
}
// ===============================================================
@ -764,49 +778,65 @@ MacroAssembler::cmpPtrSet(Condition cond, T1 lhs, T2 rhs, Register dest)
void
MacroAssembler::rotateLeft(Imm32 count, Register input, Register dest)
{
MOZ_CRASH("NYI: rotateLeft by immediate");
Ror(ARMRegister(dest, 32), ARMRegister(input, 32), (32 - count.value) & 31);
}
void
MacroAssembler::rotateLeft(Register count, Register input, Register dest)
{
MOZ_CRASH("NYI: rotateLeft by register");
vixl::UseScratchRegisterScope temps(this);
const ARMRegister scratch = temps.AcquireW();
// Really 32 - count, but the upper bits of the result are ignored.
Neg(scratch, ARMRegister(count, 32));
Ror(ARMRegister(dest, 32), ARMRegister(input, 32), scratch);
}
void
MacroAssembler::rotateRight(Imm32 count, Register input, Register dest)
{
MOZ_CRASH("NYI: rotateRight by immediate");
Ror(ARMRegister(dest, 32), ARMRegister(input, 32), count.value & 31);
}
void
MacroAssembler::rotateRight(Register count, Register input, Register dest)
{
MOZ_CRASH("NYI: rotateRight by register");
Ror(ARMRegister(dest, 32), ARMRegister(input, 32), ARMRegister(count, 32));
}
void
MacroAssembler::rotateLeft64(Register count, Register64 input, Register64 dest, Register temp)
{
MOZ_CRASH("NYI: rotateLeft64");
MOZ_ASSERT(temp == Register::Invalid());
vixl::UseScratchRegisterScope temps(this);
const ARMRegister scratch = temps.AcquireX();
// Really 64 - count, but the upper bits of the result are ignored.
Neg(scratch, ARMRegister(count, 64));
Ror(ARMRegister(dest.reg, 64), ARMRegister(input.reg, 64), scratch);
}
void
MacroAssembler::rotateLeft64(Imm32 count, Register64 input, Register64 dest, Register temp)
{
MOZ_CRASH("NYI: rotateLeft64");
MOZ_ASSERT(temp == Register::Invalid());
Ror(ARMRegister(dest.reg, 64), ARMRegister(input.reg, 64), (64 - count.value) & 63);
}
void
MacroAssembler::rotateRight64(Register count, Register64 input, Register64 dest, Register temp)
{
MOZ_CRASH("NYI: rotateRight64");
MOZ_ASSERT(temp == Register::Invalid());
Ror(ARMRegister(dest.reg, 64), ARMRegister(input.reg, 64), ARMRegister(count, 64));
}
void
MacroAssembler::rotateRight64(Imm32 count, Register64 input, Register64 dest, Register temp)
{
MOZ_CRASH("NYI: rotateRight64");
MOZ_ASSERT(temp == Register::Invalid());
Ror(ARMRegister(dest.reg, 64), ARMRegister(input.reg, 64), count.value & 63);
}
// ===============================================================
@ -815,37 +845,84 @@ MacroAssembler::rotateRight64(Imm32 count, Register64 input, Register64 dest, Re
void
MacroAssembler::clz32(Register src, Register dest, bool knownNotZero)
{
MOZ_CRASH("NYI: clz32");
Clz(ARMRegister(dest, 32), ARMRegister(src, 32));
}
void
MacroAssembler::ctz32(Register src, Register dest, bool knownNotZero)
{
MOZ_CRASH("NYI: ctz32");
Rbit(ARMRegister(dest, 32), ARMRegister(src, 32));
Clz(ARMRegister(dest, 32), ARMRegister(dest, 32));
}
void
MacroAssembler::clz64(Register64 src, Register dest)
{
MOZ_CRASH("NYI: clz64");
Clz(ARMRegister(dest, 64), ARMRegister(src.reg, 64));
}
void
MacroAssembler::ctz64(Register64 src, Register dest)
{
MOZ_CRASH("NYI: ctz64");
Rbit(ARMRegister(dest, 64), ARMRegister(src.reg, 64));
Clz(ARMRegister(dest, 64), ARMRegister(dest, 64));
}
void
MacroAssembler::popcnt32(Register src, Register dest, Register temp)
MacroAssembler::popcnt32(Register src_, Register dest_, Register tmp_)
{
MOZ_CRASH("NYI: popcnt32");
MOZ_ASSERT(tmp_ != Register::Invalid());
// Equivalent to mozilla::CountPopulation32().
ARMRegister src(src_, 32);
ARMRegister dest(dest_, 32);
ARMRegister tmp(tmp_, 32);
Mov(tmp, src);
if (src_ != dest_)
Mov(dest, src);
Lsr(dest, dest, 1);
And(dest, dest, 0x55555555);
Sub(dest, tmp, dest);
Lsr(tmp, dest, 2);
And(tmp, tmp, 0x33333333);
And(dest, dest, 0x33333333);
Add(dest, tmp, dest);
Add(dest, dest, Operand(dest, vixl::LSR, 4));
And(dest, dest, 0x0F0F0F0F);
Add(dest, dest, Operand(dest, vixl::LSL, 8));
Add(dest, dest, Operand(dest, vixl::LSL, 16));
Lsr(dest, dest, 24);
}
void
MacroAssembler::popcnt64(Register64 src, Register64 dest, Register temp)
MacroAssembler::popcnt64(Register64 src_, Register64 dest_, Register tmp_)
{
MOZ_CRASH("NYI: popcnt64");
MOZ_ASSERT(tmp_ != Register::Invalid());
// Equivalent to mozilla::CountPopulation64(), though likely more efficient.
ARMRegister src(src_.reg, 64);
ARMRegister dest(dest_.reg, 64);
ARMRegister tmp(tmp_, 64);
Mov(tmp, src);
if (src_ != dest_)
Mov(dest, src);
Lsr(dest, dest, 1);
And(dest, dest, 0x5555555555555555);
Sub(dest, tmp, dest);
Lsr(tmp, dest, 2);
And(tmp, tmp, 0x3333333333333333);
And(dest, dest, 0x3333333333333333);
Add(dest, tmp, dest);
Add(dest, dest, Operand(dest, vixl::LSR, 4));
And(dest, dest, 0x0F0F0F0F0F0F0F0F);
Add(dest, dest, Operand(dest, vixl::LSL, 8));
Add(dest, dest, Operand(dest, vixl::LSL, 16));
Add(dest, dest, Operand(dest, vixl::LSL, 32));
Lsr(dest, dest, 56);
}
// ===============================================================