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Bug 1499536 - Implement CodeGeneratorARM64::visitShiftI and visitUrshD. r=mgaudet
Fixes ion/bug1000960.js.
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@ -568,13 +568,82 @@ CodeGenerator::visitBitOpI(LBitOpI* ins)
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void
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CodeGenerator::visitShiftI(LShiftI* ins)
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{
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MOZ_CRASH("visitShiftI");
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const ARMRegister lhs = toWRegister(ins->lhs());
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const LAllocation* rhs = ins->rhs();
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const ARMRegister dest = toWRegister(ins->output());
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if (rhs->isConstant()) {
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int32_t shift = ToInt32(rhs) & 0x1F;
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switch (ins->bitop()) {
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case JSOP_LSH:
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masm.Lsl(dest, lhs, shift);
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break;
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case JSOP_RSH:
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masm.Asr(dest, lhs, shift);
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break;
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case JSOP_URSH:
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if (shift) {
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masm.Lsr(dest, lhs, shift);
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} else if (ins->mir()->toUrsh()->fallible()) {
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// x >>> 0 can overflow.
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masm.Ands(dest, lhs, Operand(0xFFFFFFFF));
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bailoutIf(Assembler::Signed, ins->snapshot());
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} else {
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masm.Mov(dest, lhs);
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}
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break;
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default:
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MOZ_CRASH("Unexpected shift op");
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}
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} else {
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const ARMRegister rhsreg = toWRegister(rhs);
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switch (ins->bitop()) {
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case JSOP_LSH:
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masm.Lsl(dest, lhs, rhsreg);
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break;
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case JSOP_RSH:
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masm.Asr(dest, lhs, rhsreg);
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break;
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case JSOP_URSH:
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masm.Lsr(dest, lhs, rhsreg);
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if (ins->mir()->toUrsh()->fallible()) {
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/// x >>> 0 can overflow.
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Label nonzero;
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masm.Cbnz(rhsreg, &nonzero);
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masm.Cmp(dest, Operand(0));
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bailoutIf(Assembler::LessThan, ins->snapshot());
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masm.bind(&nonzero);
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}
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break;
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default:
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MOZ_CRASH("Unexpected shift op");
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}
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}
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}
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void
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CodeGenerator::visitUrshD(LUrshD* ins)
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{
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MOZ_CRASH("visitUrshD");
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const ARMRegister lhs = toWRegister(ins->lhs());
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const LAllocation* rhs = ins->rhs();
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const FloatRegister out = ToFloatRegister(ins->output());
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const Register temp = ToRegister(ins->temp());
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const ARMRegister temp32 = toWRegister(ins->temp());
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if (rhs->isConstant()) {
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int32_t shift = ToInt32(rhs) & 0x1F;
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if (shift) {
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masm.Lsr(temp32, lhs, shift);
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masm.convertUInt32ToDouble(temp, out);
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} else {
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masm.convertUInt32ToDouble(ToRegister(ins->lhs()), out);
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}
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} else {
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masm.And(temp32, toWRegister(rhs), Operand(0x1F));
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masm.Lsr(temp32, lhs, temp32);
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masm.convertUInt32ToDouble(temp, out);
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}
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}
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void
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