b=479525; fix nanojit on Windows CE (calling conventions, disable regexp double-char optimization); r=dmandelin

js/src/jsregexp.cpp

@@ -2224,6 +2224,15 @@ class RegExpNativeCompiler {
         return pos;
     }
 
+#ifdef AVMPLUS_ARM
+/* We can't do this on ARM, since it relies on doing a 32-bit load from
+ * a pointer which is only 2-byte aligned.
+ */
+#undef USE_DOUBLE_CHAR_MATCH
+#else
+#define USE_DOUBLE_CHAR_MATCH
+#endif
+
     JSBool compileNode(RENode* node, LIns* pos, LInsList& fails) 
     {
         for (; node; node = node->next) {
@@ -2235,6 +2244,7 @@ class RegExpNativeCompiler {
                 pos = compileEmpty(node, pos, fails);
                 break;
             case REOP_FLAT:
+#ifdef USE_DOUBLE_CHAR_MATCH
                 if (node->u.flat.length == 1) {
                     if (node->next && node->next->op == REOP_FLAT && 
                         node->next->u.flat.length == 1) {
@@ -2258,6 +2268,14 @@ class RegExpNativeCompiler {
                    if (pos && i == node->u.flat.length - 1)
                        pos = compileFlatSingleChar(((jschar*) node->kid)[i], pos, fails);
                 }
+#else
+                for (size_t i = 0; i < node->u.flat.length; i++) {
+                    if (fragment->lirbuf->outOMem()) 
+                        return JS_FALSE;
+                    pos = compileFlatSingleChar(((jschar*) node->kid)[i], pos, fails);
+                    if (!pos) break;
+                }
+#endif
                 break;
             case REOP_ALT:
             case REOP_ALTPREREQ:

js/src/nanojit/NativeARM.cpp

@@ -178,6 +178,19 @@ Assembler::genEpilogue()
     return _nIns;
 }
 
+/* ARM EABI (used by gcc/linux) calling conventions differ from Windows CE; use these
+ * as the default.
+ *
+ * - double arg following an initial dword arg use r0 for the int arg
+ *   and r2/r3 for the double; r1 is skipped
+ * - 3 dword args followed by a double arg cause r3 to be skipped,
+ *   and the double to be stuck on the stack.
+ *
+ * Under Windows CE, the arguments are placed in r0-r3 and then the stack,
+ * one dword at a time, with the high order dword of a quad/double coming
+ * first.  No registers are skipped as they are in the EABI case.
+ */
+
 void
 Assembler::asm_call(LInsp ins)
 {
@@ -193,11 +206,12 @@ Assembler::asm_call(LInsp ins)
 #endif
     atypes >>= 2;
 
+    bool arg0IsInt32FollowedByFloat = false;
+#ifndef UNDER_CE
     // we need to detect if we have arg0 as LO followed by arg1 as F;
     // in that case, we need to skip using r1 -- the F needs to be
     // loaded in r2/r3, at least according to the ARM EABI and gcc 4.2's
     // generated code.
-    bool arg0IsInt32FollowedByFloat = false;
     while ((atypes & 3) != ARGSIZE_NONE) {
         if (((atypes >> 2) & 3) == ARGSIZE_LO &&
             ((atypes >> 0) & 3) == ARGSIZE_F &&
@@ -208,6 +222,7 @@ Assembler::asm_call(LInsp ins)
         }
         atypes >>= 2;
     }
+#endif
 
 #ifdef NJ_ARM_VFP
     if (rsize == ARGSIZE_F) {
@@ -244,6 +259,21 @@ Assembler::asm_call(LInsp ins)
         Register r = (i + roffset) < 4 ? argRegs[i+roffset] : UnknownReg;
 #ifdef NJ_ARM_VFP
         if (sz == ARGSIZE_F) {
+#ifdef UNDER_CE
+            if (r >= R0 && r <= R2) {
+                // we can use up r0/r1, r1/r2, r2/r3 without anything special
+                roffset++;
+                FMRRD(r, nextreg(r), sr);
+            } else if (r == R3) {
+                // to use R3 gets complicated; we need to move the high dword
+                // into R3, and the low dword on the stack.
+                STR_preindex(Scratch, SP, -4);
+                FMRDL(Scratch, sr);
+                FMRDH(r, sr);
+            } else {
+                asm_pusharg(arg);
+            }
+#else
             if (r == R0 || r == R2) {
                 roffset++;
             } else if (r == R1) {
@@ -263,6 +293,7 @@ Assembler::asm_call(LInsp ins)
             } else {
                 asm_pusharg(arg);
             }
+#endif
         } else {
             asm_arg(sz, arg, r);
         }
@@ -271,6 +302,7 @@ Assembler::asm_call(LInsp ins)
         asm_arg(sz, arg, r);
 #endif
 
+        // Under CE, arg0IsInt32FollowedByFloat will always be false
         if (i == 0 && arg0IsInt32FollowedByFloat)
             roffset = 1;
     }
@@ -1373,13 +1405,23 @@ Assembler::asm_ld(LInsp ins)
     Register rr = prepResultReg(ins, GpRegs);
     int d = disp->constval();
     Register ra = getBaseReg(base, d, GpRegs);
-    if (op == LIR_ld || op == LIR_ldc)
+
+    // these will always be 4-byte aligned
+    if (op == LIR_ld || op == LIR_ldc) {
         LD(rr, d, ra);
-    else if (op == LIR_ldcb)
-        LDRB(rr, d, ra);
-    else if (op == LIR_ldcs)
+        return;
+    }
+
+    // these will be 2 or 4-byte aligned
+    if (op == LIR_ldcs) {
         LDRH(rr, d, ra);
-    else
+    }
+
+    // aaand this is just any byte.
+    if (op == LIR_ldcb) {
+        LDRB(rr, d, ra);
+    }
+
     NanoAssertMsg(0, "Unsupported instruction in asm_ld");
 }
 

js/src/nanojit/NativeARM.h

@@ -793,6 +793,13 @@ typedef enum {
         asm_output("fmrrd %s,%s,%s", gpn(_Rd), gpn(_Rn), gpn(_Dm));    \
     } while (0)
 
+#define FMRDH(_Rd,_Dn) do {                                             \
+        underrunProtect(4);                                             \
+        NanoAssert(IsGpReg(_Rd) && IsFpReg(_Dm));                       \
+        *(--_nIns) = (NIns)( COND_AL | (0xE3<<20) | (FpRegNum(_Dn)<<16) | ((_Rd)<<12) | (0xB<<8) | (1<<4) ); \
+        asm_output("fmrdh %s,%s", gpn(_Rd), gpn(_Dn));                  \
+    } while (0)
+
 #define FSTD(_Dd,_Rn,_offs) do {                                        \
         underrunProtect(4);                                             \
         NanoAssert((((_offs) & 3) == 0) && isS8((_offs) >> 2));         \

modules/libpref/src/init/all.js

@@ -2705,8 +2705,5 @@ pref("network.tcp.sendbuffer", 131072);
 #endif
 
 #ifdef WINCE
-// Note that this overwrites an option set earlier, until
-// we can fix the jit on CE.
-pref("javascript.options.jit.content",      false);
 pref("mozilla.widget.disable-native-theme", true);
 #endif