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Bug 1004363 - Follow-up patch to fix a few more places that should ignore trivial blocks on ARM. r=me
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@ -1092,7 +1092,7 @@ CodeGeneratorARM::visitOutOfLineTableSwitch(OutOfLineTableSwitch *ool)
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size_t numCases = mir->numCases();
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for (size_t i = 0; i < numCases; i++) {
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LBlock *caseblock = mir->getCase(numCases - 1 - i)->lir();
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LBlock *caseblock = skipTrivialBlocks(mir->getCase(numCases - 1 - i))->lir();
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Label *caseheader = caseblock->label();
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uint32_t caseoffset = caseheader->offset();
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@ -1136,7 +1136,7 @@ CodeGeneratorARM::emitTableSwitchDispatch(MTableSwitch *mir, Register index, Reg
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// unhandled case is the default case (both out of range high and out of range low)
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// I then insert a branch to default case into the extra slot, which ensures
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// we don't attempt to execute the address table.
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Label *defaultcase = mir->getDefault()->lir()->label();
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Label *defaultcase = skipTrivialBlocks(mir->getDefault())->lir()->label();
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int32_t cases = mir->numCases();
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// Lower value with low value
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@ -1018,7 +1018,7 @@ CodeGeneratorMIPS::visitOutOfLineTableSwitch(OutOfLineTableSwitch *ool)
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return false;
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for (size_t i = 0; i < mir->numCases(); i++) {
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LBlock *caseblock = mir->getCase(i)->lir();
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LBlock *caseblock = skipTrivialBlocks(mir->getCase(i))->lir();
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Label *caseheader = caseblock->label();
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uint32_t caseoffset = caseheader->offset();
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@ -1039,7 +1039,7 @@ bool
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CodeGeneratorMIPS::emitTableSwitchDispatch(MTableSwitch *mir, Register index,
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Register address)
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{
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Label *defaultcase = mir->getDefault()->lir()->label();
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Label *defaultcase = skipTrivialBlocks(mir->getDefault())->lir()->label();
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// Lower value with low value
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if (mir->low() != 0)
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