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Push-and-pray to try to fix ARM build breaks. (r=red).
This commit is contained in:
Chris Leary
parent
3830538ae6
commit
cd014beba1
@ -278,13 +278,13 @@ void ARMAssembler::dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID bas
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} else {
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offset = -offset;
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if (offset <= 0xfff)
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dtr_d(isLoad, srcDst, base, offset);
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dtr_d(isLoad, srcDst, base, offset | transferFlag);
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else if (offset <= 0xfffff) {
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sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
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dtr_d(isLoad, srcDst, ARMRegisters::S0, offset & 0xfff);
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dtr_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);
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} else {
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ARMWord reg = getImm(offset, ARMRegisters::S0);
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dtr_dr(isLoad, srcDst, base, reg);
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dtr_dr(isLoad, srcDst, base, reg | transferFlag);
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}
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}
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}
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@ -356,10 +356,17 @@ void* ARMAssembler::executableCopy(ExecutablePool* allocator)
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// The last bit is set if the constant must be placed on constant pool.
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int pos = (*iter) & (~0x1);
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ARMWord* ldrAddr = reinterpret_cast<ARMWord*>(data + pos);
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ARMWord offset = *getLdrImmAddress(ldrAddr);
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if (offset != 0xffffffff) {
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JmpSrc jmpSrc(pos);
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linkBranch(data, jmpSrc, data + offset, ((*iter) & 1));
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ARMWord* addr = getLdrImmAddress(ldrAddr);
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if (*addr != InvalidBranchTarget) {
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if (!(*iter & 1)) {
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int diff = reinterpret_cast<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetching);
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if ((diff <= BOFFSET_MAX && diff >= BOFFSET_MIN)) {
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*ldrAddr = B | getConditionalField(*ldrAddr) | (diff & BRANCH_MASK);
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continue;
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}
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}
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*addr = reinterpret_cast<ARMWord>(data + *addr);
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}
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2009 University of Szeged
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* Copyright (C) 2009, 2010 University of Szeged
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -37,7 +37,6 @@
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#include "AssemblerBufferWithConstantPool.h"
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#include "assembler/wtf/Assertions.h"
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#define IPFX " "
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namespace JSC {
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@ -74,13 +73,46 @@ namespace JSC {
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d1,
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d2,
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d3,
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SD0 = d3
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SD0 = d3,
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d4,
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d5,
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d6,
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d7,
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d8,
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d9,
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d10,
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d11,
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d12,
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d13,
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d14,
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d15,
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d16,
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d17,
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d18,
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d19,
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d20,
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d21,
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d22,
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d23,
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d24,
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d25,
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d26,
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d27,
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d28,
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d29,
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d30,
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d31
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} FPRegisterID;
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} // namespace ARMRegisters
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class ARMAssembler {
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public:
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#ifdef DEBUG
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bool isOOLPath;
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#endif
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typedef ARMRegisters::RegisterID RegisterID;
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typedef ARMRegisters::FPRegisterID FPRegisterID;
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typedef AssemblerBufferWithConstantPool<2048, 4, 4, ARMAssembler> ARMBuffer;
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@ -88,6 +120,8 @@ namespace JSC {
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ARMAssembler() { }
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unsigned char *buffer() const { return m_buffer.buffer(); }
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// ARM conditional constants
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typedef enum {
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EQ = 0x00000000, // Zero
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@ -128,10 +162,12 @@ namespace JSC {
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MUL = 0x00000090,
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MULL = 0x00c00090,
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FADDD = 0x0e300b00,
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FNEGD = 0x0eb10b40,
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FDIVD = 0x0e800b00,
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FSUBD = 0x0e300b40,
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FMULD = 0x0e200b00,
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FCMPD = 0x0eb40b40,
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FSQRTD = 0x0eb10bc0,
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DTR = 0x05000000,
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LDRH = 0x00100090,
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STRH = 0x00000090,
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@ -139,11 +175,11 @@ namespace JSC {
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LDMIA = 0x08b00000,
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FDTR = 0x0d000b00,
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B = 0x0a000000,
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BL = 0x0b000000,
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#ifndef __ARM_ARCH_4__
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BX = 0x012fff10, // Only on ARMv4T+!
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BL = 0x0b000000
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#if WTF_ARM_ARCH_VERSION >= 5 || defined(__ARM_ARCH_4T__)
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,BX = 0x012fff10
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#endif
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FMSR = 0x0e000a10,
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,FMSR = 0x0e000a10,
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FMRS = 0x0e100a10,
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FSITOD = 0x0eb80bc0,
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FTOSID = 0x0ebd0b40,
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@ -151,7 +187,7 @@ namespace JSC {
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#if WTF_ARM_ARCH_VERSION >= 5
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,CLZ = 0x016f0f10,
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BKPT = 0xe120070,
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BLX_R = 0x012fff30
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BLX = 0x012fff30
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#endif
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#if WTF_ARM_ARCH_VERSION >= 7
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,MOVW = 0x03000000,
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@ -166,6 +202,7 @@ namespace JSC {
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SET_CC = (1 << 20),
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OP2_OFSREG = (1 << 25),
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DT_UP = (1 << 23),
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DT_BYTE = (1 << 22),
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DT_WB = (1 << 21),
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// This flag is inlcuded in LDR and STR
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DT_PRE = (1 << 24),
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@ -201,6 +238,8 @@ namespace JSC {
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} Shift;
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static const ARMWord INVALID_IMM = 0xf0000000;
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static const ARMWord InvalidBranchTarget = 0xffffffff;
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static const int DefaultPrefetching = 2;
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class JmpSrc {
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friend class ARMAssembler;
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@ -446,34 +485,36 @@ namespace JSC {
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void faddd_r(int dd, int dn, int dm, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FADDD, dd, dn, dm);
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}
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void fdivd_r(int dd, int dn, int dm, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FDIVD, dd, dn, dm);
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}
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void fsubd_r(int dd, int dn, int dm, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FSUBD, dd, dn, dm);
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}
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void fmuld_r(int dd, int dn, int dm, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FMULD, dd, dn, dm);
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}
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void fcmpd_r(int dd, int dm, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FCMPD, dd, 0, dm);
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}
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void fsqrtd_r(int dd, int dm, Condition cc = AL)
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{
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// TODO: emitInst doesn't work for VFP instructions, though it
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// seems to work for current usage.
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emitInst(static_cast<ARMWord>(cc) | FSQRTD, dd, 0, dm);
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}
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void ldr_imm(int rd, ARMWord imm, Condition cc = AL)
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{
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char mnemonic[16];
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@ -546,14 +587,12 @@ namespace JSC {
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void fdtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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ASSERT(op2 <= 0xff);
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emitInst(static_cast<ARMWord>(cc) | FDTR | DT_UP | (isLoad ? DT_LOAD : 0), rd, rb, op2);
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}
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void fdtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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ASSERT(op2 <= 0xff);
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emitInst(static_cast<ARMWord>(cc) | FDTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
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}
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@ -582,31 +621,26 @@ namespace JSC {
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void fmsr_r(int dd, int rn, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FMSR, rn, dd, 0);
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}
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void fmrs_r(int rd, int dn, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FMRS, rd, dn, 0);
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}
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void fsitod_r(int dd, int dm, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FSITOD, dd, 0, dm);
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}
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void ftosid_r(int fd, int dm, Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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emitInst(static_cast<ARMWord>(cc) | FTOSID, fd, 0, dm);
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}
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void fmstat(Condition cc = AL)
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{
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FIXME_INSN_PRINTING;
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m_buffer.putInt(static_cast<ARMWord>(cc) | FMSTAT);
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}
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@ -628,37 +662,28 @@ namespace JSC {
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#endif
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}
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// BX is emitted where possible, or an equivalent sequence on ARMv4.
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void bx_r(int rm, Condition cc = AL)
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void bx(int rm, Condition cc = AL)
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{
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#if (WTF_ARM_ARCH_VERSION >= 5) || defined(__ARM_ARCH_4T__)
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// ARMv4T+ has BX <reg>.
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m_buffer.putInt(static_cast<ARMWord>(cc) | BX | RM(rm));
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#else // defined(__ARM_ARCH_4__)
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// ARMv4 has to do "MOV pc, rm". This works on newer architectures
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// too, but breaks return stack prediction and doesn't interwork on
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// ARMv4T, so this becomes a special case of ARMv4.
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mov_r(ARMRegisters::pc, rm, cc);
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#if WTF_ARM_ARCH_VERSION >= 5 || defined(__ARM_ARCH_4T__)
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emitInst(static_cast<ARMWord>(cc) | BX, 0, 0, RM(rm));
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#else
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mov_r(ARMRegisters::pc, RM(rm), cc);
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#endif
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}
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// BLX is emitted where possible, or an equivalent (slower) sequence on
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// ARMv4 or ARMv4T.
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void blx_r(int rm, Condition cc = AL)
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JmpSrc blx(int rm, Condition cc = AL)
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{
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ASSERT((rm >= 0) && (rm <= 14));
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#if WTF_ARM_ARCH_VERSION >= 5
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// ARMv5+ is the ideal (fast) case, and can use a proper "BLX rm".
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m_buffer.putInt(static_cast<ARMWord>(cc) | BLX_R | RM(rm));
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#else // defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
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// ARMv4T must do "MOV lr, pc; BX rm".
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// ARMv4 must do "MOV lr, pc; MOV pc, rm".
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// Both cases are handled here and by bx_r.
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#if WTF_ARM_ARCH_AT_LEAST(5)
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int s = m_buffer.uncheckedSize();
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emitInst(static_cast<ARMWord>(cc) | BLX, 0, 0, RM(rm));
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#else
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ASSERT(rm != 14);
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ensureSpace(2 * sizeof(ARMWord), 0);
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mov_r(ARMRegisters::lr, ARMRegisters::pc, cc);
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bx_r(rm, cc);
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int s = m_buffer.uncheckedSize();
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bx(rm, cc);
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#endif
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return JmpSrc(s);
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}
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static ARMWord lsl(int reg, ARMWord value)
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@ -737,7 +762,7 @@ namespace JSC {
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{
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ensureSpace(sizeof(ARMWord), sizeof(ARMWord));
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int s = m_buffer.uncheckedSize();
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ldr_un_imm(rd, 0xffffffff, cc);
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ldr_un_imm(rd, InvalidBranchTarget, cc);
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m_jumps.append(s | (useConstantPool & 0x1));
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return JmpSrc(s);
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}
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@ -751,15 +776,40 @@ namespace JSC {
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// Patching helpers
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static ARMWord* getLdrImmAddress(ARMWord* insn, uint32_t* constPool = 0);
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static void linkBranch(void* code, JmpSrc from, void* to, int useConstantPool = 0);
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static ARMWord* getLdrImmAddress(ARMWord* insn)
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{
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#if WTF_ARM_ARCH_AT_LEAST(5)
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// Check for call
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if ((*insn & 0x0f7f0000) != 0x051f0000) {
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// Must be BLX
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ASSERT((*insn & 0x012fff30) == 0x012fff30);
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insn--;
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}
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#endif
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// Must be an ldr ..., [pc +/- imm]
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ASSERT((*insn & 0x0f7f0000) == 0x051f0000);
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ARMWord addr = reinterpret_cast<ARMWord>(insn) + DefaultPrefetching * sizeof(ARMWord);
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if (*insn & DT_UP)
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return reinterpret_cast<ARMWord*>(addr + (*insn & SDT_OFFSET_MASK));
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return reinterpret_cast<ARMWord*>(addr - (*insn & SDT_OFFSET_MASK));
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}
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static ARMWord* getLdrImmAddressOnPool(ARMWord* insn, uint32_t* constPool)
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{
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// Must be an ldr ..., [pc +/- imm]
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ASSERT((*insn & 0x0f7f0000) == 0x051f0000);
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if (*insn & 0x1)
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return reinterpret_cast<ARMWord*>(constPool + ((*insn & SDT_OFFSET_MASK) >> 1));
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return getLdrImmAddress(insn);
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}
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static void patchPointerInternal(intptr_t from, void* to)
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{
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ARMWord* insn = reinterpret_cast<ARMWord*>(from);
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ARMWord* addr = getLdrImmAddress(insn);
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*addr = reinterpret_cast<ARMWord>(to);
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ExecutableAllocator::cacheFlush(addr, sizeof(ARMWord));
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}
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static ARMWord patchConstantPoolLoad(ARMWord load, ARMWord value)
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@ -816,12 +866,13 @@ namespace JSC {
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void linkJump(JmpSrc from, JmpDst to)
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{
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ARMWord* insn = reinterpret_cast<ARMWord*>(m_buffer.data()) + (from.m_offset / sizeof(ARMWord));
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*getLdrImmAddress(insn, m_buffer.poolAddress()) = static_cast<ARMWord>(to.m_offset);
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ARMWord* addr = getLdrImmAddressOnPool(insn, m_buffer.poolAddress());
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*addr = static_cast<ARMWord>(to.m_offset);
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}
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static void linkJump(void* code, JmpSrc from, void* to)
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{
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linkBranch(code, from, to);
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patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
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}
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static void relinkJump(void* from, void* to)
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@ -831,12 +882,12 @@ namespace JSC {
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static void linkCall(void* code, JmpSrc from, void* to)
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{
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linkBranch(code, from, to, true);
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patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
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}
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static void relinkCall(void* from, void* to)
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{
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relinkJump(from, to);
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patchPointerInternal(reinterpret_cast<intptr_t>(from) - sizeof(ARMWord), to);
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}
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// Address operations
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@ -890,9 +941,18 @@ namespace JSC {
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void moveImm(ARMWord imm, int dest);
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ARMWord encodeComplexImm(ARMWord imm, int dest);
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ARMWord getOffsetForHalfwordDataTransfer(ARMWord imm, int tmpReg)
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{
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// Encode immediate data in the instruction if it is possible
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if (imm <= 0xff)
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return getOp2Byte(imm);
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// Otherwise, store the data in a temporary register
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return encodeComplexImm(imm, tmpReg);
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}
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// Memory load/store helpers
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void dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset);
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void dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset, bool bytes = false);
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void baseIndexTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
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void doubleTransfer(bool isLoad, FPRegisterID srcDst, RegisterID base, int32_t offset);
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@ -919,6 +979,23 @@ namespace JSC {
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return names[reg];
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}
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static char const * nameFpRegD(int reg)
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{
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ASSERT(reg <= 31);
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ASSERT(reg >= 0);
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static char const * names[] = {
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"d0", "d1", "d2", "d3",
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"d4", "d5", "d6", "d7",
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"d8", "d9", "d10", "d11",
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"d12", "d13", "d14", "d15",
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"d16", "d17", "d18", "d19",
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"d20", "d21", "d22", "d23",
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"d24", "d25", "d26", "d27",
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"d28", "d29", "d30", "d31"
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};
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return names[reg];
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}
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static char const * nameCC(Condition cc)
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{
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ASSERT(cc <= AL);
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@ -1046,6 +1123,27 @@ namespace JSC {
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return reg << 16;
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}
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ARMWord DD(int reg)
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{
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ASSERT(reg <= ARMRegisters::d31);
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// Endoded as bits [22,15:12].
|
||||
return ((reg << 12) | (reg << 18)) & 0x0040f000;
|
||||
}
|
||||
|
||||
ARMWord DN(int reg)
|
||||
{
|
||||
ASSERT(reg <= ARMRegisters::d31);
|
||||
// Endoded as bits [7,19:16].
|
||||
return ((reg << 16) | (reg << 3)) & 0x000f0080;
|
||||
}
|
||||
|
||||
ARMWord DM(int reg)
|
||||
{
|
||||
ASSERT(reg <= ARMRegisters::d31);
|
||||
// Encoded as bits [5,3:0].
|
||||
return ((reg << 1) & 0x20) | (reg & 0xf);
|
||||
}
|
||||
|
||||
static ARMWord getConditionalField(ARMWord i)
|
||||
{
|
||||
return i & 0xf0000000;
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
* Copyright (C) 2010 University of Szeged
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -33,6 +34,7 @@
|
||||
#include "AssemblerBuffer.h"
|
||||
#include "assembler/wtf/Assertions.h"
|
||||
#include "assembler/wtf/Vector.h"
|
||||
#include <stdint.h>
|
||||
|
||||
namespace JSC {
|
||||
|
||||
@ -581,11 +583,13 @@ private:
|
||||
OP_MOV_reg_T1 = 0x4600,
|
||||
OP_BLX = 0x4700,
|
||||
OP_BX = 0x4700,
|
||||
OP_LDRH_reg_T1 = 0x5A00,
|
||||
OP_STR_reg_T1 = 0x5000,
|
||||
OP_LDR_reg_T1 = 0x5800,
|
||||
OP_LDRH_reg_T1 = 0x5A00,
|
||||
OP_LDRB_reg_T1 = 0x5C00,
|
||||
OP_STR_imm_T1 = 0x6000,
|
||||
OP_LDR_imm_T1 = 0x6800,
|
||||
OP_LDRB_imm_T1 = 0x7800,
|
||||
OP_LDRH_imm_T1 = 0x8800,
|
||||
OP_STR_imm_T2 = 0x9000,
|
||||
OP_LDR_imm_T2 = 0x9800,
|
||||
@ -630,12 +634,15 @@ private:
|
||||
OP_SUB_imm_T4 = 0xF2A0,
|
||||
OP_MOVT = 0xF2C0,
|
||||
OP_NOP_T2a = 0xF3AF,
|
||||
OP_LDRB_imm_T3 = 0xF810,
|
||||
OP_LDRB_reg_T2 = 0xF810,
|
||||
OP_LDRH_reg_T2 = 0xF830,
|
||||
OP_LDRH_imm_T3 = 0xF830,
|
||||
OP_STR_imm_T4 = 0xF840,
|
||||
OP_STR_reg_T2 = 0xF840,
|
||||
OP_LDR_imm_T4 = 0xF850,
|
||||
OP_LDR_reg_T2 = 0xF850,
|
||||
OP_LDRB_imm_T2 = 0xF890,
|
||||
OP_LDRH_imm_T2 = 0xF8B0,
|
||||
OP_STR_imm_T3 = 0xF8C0,
|
||||
OP_LDR_imm_T3 = 0xF8D0,
|
||||
@ -1079,6 +1086,52 @@ public:
|
||||
m_formatter.twoWordOp12Reg4FourFours(OP_LDRH_reg_T2, rn, FourFours(rt, 0, shift, rm));
|
||||
}
|
||||
|
||||
void ldrb(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)
|
||||
{
|
||||
ASSERT(rn != ARMRegisters::pc); // LDR (literal)
|
||||
ASSERT(imm.isUInt12());
|
||||
|
||||
if (!((rt | rn) & 8) && imm.isUInt5())
|
||||
m_formatter.oneWordOp5Imm5Reg3Reg3(OP_LDRB_imm_T1, imm.getUInt5(), rn, rt);
|
||||
else
|
||||
m_formatter.twoWordOp12Reg4Reg4Imm12(OP_LDRB_imm_T2, rn, rt, imm.getUInt12());
|
||||
}
|
||||
|
||||
void ldrb(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)
|
||||
{
|
||||
ASSERT(rt != ARMRegisters::pc);
|
||||
ASSERT(rn != ARMRegisters::pc);
|
||||
ASSERT(index || wback);
|
||||
ASSERT(!wback | (rt != rn));
|
||||
|
||||
bool add = true;
|
||||
if (offset < 0) {
|
||||
add = false;
|
||||
offset = -offset;
|
||||
}
|
||||
|
||||
ASSERT(!(offset & ~0xff));
|
||||
|
||||
offset |= (wback << 8);
|
||||
offset |= (add << 9);
|
||||
offset |= (index << 10);
|
||||
offset |= (1 << 11);
|
||||
|
||||
m_formatter.twoWordOp12Reg4Reg4Imm12(OP_LDRB_imm_T3, rn, rt, offset);
|
||||
}
|
||||
|
||||
void ldrb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0)
|
||||
{
|
||||
ASSERT(rn != ARMRegisters::pc); // LDR (literal)
|
||||
ASSERT(!BadReg(rm));
|
||||
ASSERT(shift <= 3);
|
||||
|
||||
if (!shift && !((rt | rn | rm) & 8))
|
||||
m_formatter.oneWordOp7Reg3Reg3Reg3(OP_LDRB_reg_T1, rm, rn, rt);
|
||||
else
|
||||
m_formatter.twoWordOp12Reg4FourFours(OP_LDRB_reg_T2, rn, FourFours(rt, 0, shift, rm));
|
||||
}
|
||||
|
||||
void lsl(RegisterID rd, RegisterID rm, int32_t shiftAmount)
|
||||
{
|
||||
ASSERT(!BadReg(rd));
|
||||
@ -1717,7 +1770,20 @@ private:
|
||||
|| (isNOP_T1(instruction - 5) && isNOP_T2(instruction - 4) && isB(instruction - 2)) );
|
||||
|
||||
intptr_t relative = reinterpret_cast<intptr_t>(target) - (reinterpret_cast<intptr_t>(instruction));
|
||||
if (((relative << 7) >> 7) == relative) {
|
||||
|
||||
// From Cortex-A8 errata:
|
||||
// If the 32-bit Thumb-2 branch instruction spans two 4KiB regions and
|
||||
// the target of the branch falls within the first region it is
|
||||
// possible for the processor to incorrectly determine the branch
|
||||
// instruction, and it is also possible in some cases for the processor
|
||||
// to enter a deadlock state.
|
||||
// The instruction is spanning two pages if it ends at an address ending 0x002
|
||||
bool spansTwo4K = ((reinterpret_cast<intptr_t>(instruction) & 0xfff) == 0x002);
|
||||
// The target is in the first page if the jump branch back by [3..0x1002] bytes
|
||||
bool targetInFirstPage = (relative >= -0x1002) && (relative < -2);
|
||||
bool wouldTriggerA8Errata = spansTwo4K && targetInFirstPage;
|
||||
|
||||
if (((relative << 7) >> 7) == relative && !wouldTriggerA8Errata) {
|
||||
// ARM encoding for the top two bits below the sign bit is 'peculiar'.
|
||||
if (relative >= 0)
|
||||
relative ^= 0xC00000;
|
||||
|
||||
@ -53,6 +53,12 @@ public:
|
||||
typedef typename AssemblerType::JmpSrc JmpSrc;
|
||||
typedef typename AssemblerType::JmpDst JmpDst;
|
||||
|
||||
#ifdef DEBUG
|
||||
void setSpewPath(bool isOOLPath)
|
||||
{
|
||||
m_assembler.isOOLPath = isOOLPath;
|
||||
}
|
||||
#endif
|
||||
|
||||
// Section 1: MacroAssembler operand types
|
||||
//
|
||||
|
||||
@ -188,6 +188,20 @@ public:
|
||||
m_assembler.movs_r(dest, m_assembler.asr(dest, imm.m_value & 0x1f));
|
||||
}
|
||||
|
||||
void urshift32(RegisterID shift_amount, RegisterID dest)
|
||||
{
|
||||
ARMWord w = ARMAssembler::getOp2(0x1f);
|
||||
ASSERT(w != ARMAssembler::INVALID_IMM);
|
||||
m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
|
||||
|
||||
m_assembler.movs_r(dest, m_assembler.lsr_r(dest, ARMRegisters::S0));
|
||||
}
|
||||
|
||||
void urshift32(Imm32 imm, RegisterID dest)
|
||||
{
|
||||
m_assembler.movs_r(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
|
||||
}
|
||||
|
||||
void sub32(RegisterID src, RegisterID dest)
|
||||
{
|
||||
m_assembler.subs_r(dest, dest, src);
|
||||
@ -227,6 +241,17 @@ public:
|
||||
m_assembler.eors_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
|
||||
}
|
||||
|
||||
void xor32(Address src, RegisterID dest)
|
||||
{
|
||||
load32(src, ARMRegisters::S1);
|
||||
m_assembler.eors_r(dest, dest, ARMRegisters::S1);
|
||||
}
|
||||
|
||||
void load8(ImplicitAddress address, RegisterID dest)
|
||||
{
|
||||
m_assembler.dataTransfer32(true, dest, address.base, address.offset, true);
|
||||
}
|
||||
|
||||
void load32(ImplicitAddress address, RegisterID dest)
|
||||
{
|
||||
m_assembler.dataTransfer32(true, dest, address.base, address.offset);
|
||||
@ -263,11 +288,16 @@ public:
|
||||
|
||||
void load16(BaseIndex address, RegisterID dest)
|
||||
{
|
||||
m_assembler.add_r(ARMRegisters::S0, address.base, m_assembler.lsl(address.index, address.scale));
|
||||
if (address.offset>=0)
|
||||
m_assembler.ldrh_u(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(address.offset));
|
||||
m_assembler.add_r(ARMRegisters::S1, address.base, m_assembler.lsl(address.index, address.scale));
|
||||
load16(Address(ARMRegisters::S1, address.offset), dest);
|
||||
}
|
||||
|
||||
void load16(ImplicitAddress address, RegisterID dest)
|
||||
{
|
||||
if (address.offset >= 0)
|
||||
m_assembler.ldrh_u(dest, address.base, m_assembler.getOffsetForHalfwordDataTransfer(address.offset, ARMRegisters::S0));
|
||||
else
|
||||
m_assembler.ldrh_d(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(-address.offset));
|
||||
m_assembler.ldrh_d(dest, address.base, m_assembler.getOffsetForHalfwordDataTransfer(-address.offset, ARMRegisters::S0));
|
||||
}
|
||||
|
||||
DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
|
||||
@ -381,6 +411,12 @@ public:
|
||||
move(src, dest);
|
||||
}
|
||||
|
||||
Jump branch8(Condition cond, Address left, Imm32 right)
|
||||
{
|
||||
load8(left, ARMRegisters::S1);
|
||||
return branch32(cond, ARMRegisters::S1, right);
|
||||
}
|
||||
|
||||
Jump branch32(Condition cond, RegisterID left, RegisterID right, int useConstantPool = 0)
|
||||
{
|
||||
m_assembler.cmp_r(left, right);
|
||||
@ -444,6 +480,12 @@ public:
|
||||
return m_assembler.jmp(ARMCondition(cond));
|
||||
}
|
||||
|
||||
Jump branchTest8(Condition cond, Address address, Imm32 mask = Imm32(-1))
|
||||
{
|
||||
load8(address, ARMRegisters::S1);
|
||||
return branchTest32(cond, ARMRegisters::S1, mask);
|
||||
}
|
||||
|
||||
Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask)
|
||||
{
|
||||
ASSERT((cond == Zero) || (cond == NonZero));
|
||||
@ -481,7 +523,7 @@ public:
|
||||
|
||||
void jump(RegisterID target)
|
||||
{
|
||||
m_assembler.bx_r(target);
|
||||
m_assembler.bx(target);
|
||||
}
|
||||
|
||||
void jump(Address address)
|
||||
@ -503,6 +545,13 @@ public:
|
||||
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
||||
}
|
||||
|
||||
Jump branchAdd32(Condition cond, Address src, RegisterID dest)
|
||||
{
|
||||
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
||||
add32(src, dest);
|
||||
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
||||
}
|
||||
|
||||
void mull32(RegisterID src1, RegisterID src2, RegisterID dest)
|
||||
{
|
||||
if (src1 == dest) {
|
||||
@ -552,6 +601,20 @@ public:
|
||||
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
||||
}
|
||||
|
||||
Jump branchSub32(Condition cond, Address src, RegisterID dest)
|
||||
{
|
||||
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
||||
sub32(src, dest);
|
||||
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
||||
}
|
||||
|
||||
Jump branchNeg32(Condition cond, RegisterID srcDest)
|
||||
{
|
||||
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
||||
neg32(srcDest);
|
||||
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
||||
}
|
||||
|
||||
Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
|
||||
{
|
||||
ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
|
||||
@ -568,7 +631,7 @@ public:
|
||||
{
|
||||
#if WTF_ARM_ARCH_VERSION >= 5
|
||||
Call call(m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true), Call::LinkableNear);
|
||||
m_assembler.blx_r(ARMRegisters::S1);
|
||||
m_assembler.blx(ARMRegisters::S1);
|
||||
return call;
|
||||
#else
|
||||
prepareCall();
|
||||
@ -578,7 +641,7 @@ public:
|
||||
|
||||
Call call(RegisterID target)
|
||||
{
|
||||
m_assembler.blx_r(target);
|
||||
m_assembler.blx(target);
|
||||
JmpSrc jmpSrc;
|
||||
return Call(jmpSrc, Call::None);
|
||||
}
|
||||
@ -590,7 +653,7 @@ public:
|
||||
|
||||
void ret()
|
||||
{
|
||||
m_assembler.bx_r(linkRegister);
|
||||
m_assembler.bx(linkRegister);
|
||||
}
|
||||
|
||||
void set32(Condition cond, Address left, RegisterID right, RegisterID dest)
|
||||
@ -619,6 +682,12 @@ public:
|
||||
m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
|
||||
}
|
||||
|
||||
void set32(Condition cond, Address left, Imm32 right, RegisterID dest)
|
||||
{
|
||||
load32(left, ARMRegisters::S1);
|
||||
set32(cond, ARMRegisters::S1, right, dest);
|
||||
}
|
||||
|
||||
void set8(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
|
||||
{
|
||||
// ARM doesn't have byte registers
|
||||
@ -717,7 +786,7 @@ public:
|
||||
{
|
||||
#if WTF_ARM_ARCH_VERSION >= 5
|
||||
Call call(m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true), Call::Linkable);
|
||||
m_assembler.blx_r(ARMRegisters::S1);
|
||||
m_assembler.blx(ARMRegisters::S1);
|
||||
return call;
|
||||
#else
|
||||
prepareCall();
|
||||
@ -780,12 +849,17 @@ public:
|
||||
return false;
|
||||
}
|
||||
|
||||
bool supportsFloatingPointSqrt() const
|
||||
{
|
||||
return s_isVFPPresent;
|
||||
}
|
||||
|
||||
void loadDouble(ImplicitAddress address, FPRegisterID dest)
|
||||
{
|
||||
m_assembler.doubleTransfer(true, dest, address.base, address.offset);
|
||||
}
|
||||
|
||||
void loadDouble(void* address, FPRegisterID dest)
|
||||
void loadDouble(const void* address, FPRegisterID dest)
|
||||
{
|
||||
m_assembler.ldr_un_imm(ARMRegisters::S0, (ARMWord)address);
|
||||
m_assembler.fdtr_u(true, dest, ARMRegisters::S0, 0);
|
||||
@ -841,6 +915,16 @@ public:
|
||||
mulDouble(ARMRegisters::SD0, dest);
|
||||
}
|
||||
|
||||
void negDouble(FPRegisterID src, FPRegisterID dest)
|
||||
{
|
||||
m_assembler.fnegd_r(dest, src);
|
||||
}
|
||||
|
||||
void sqrtDouble(FPRegisterID src, FPRegisterID dest)
|
||||
{
|
||||
m_assembler.fsqrtd_r(dest, src);
|
||||
}
|
||||
|
||||
void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
|
||||
{
|
||||
m_assembler.fmsr_r(dest, src);
|
||||
@ -927,46 +1011,58 @@ protected:
|
||||
#if WTF_ARM_ARCH_VERSION < 5
|
||||
void prepareCall()
|
||||
{
|
||||
#if WTF_ARM_ARCH_VERSION < 5
|
||||
ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord));
|
||||
|
||||
m_assembler.mov_r(linkRegister, ARMRegisters::pc);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WTF_ARM_ARCH_VERSION < 5
|
||||
void call32(RegisterID base, int32_t offset)
|
||||
{
|
||||
#if WTF_ARM_ARCH_VERSION >= 5
|
||||
int targetReg = ARMRegisters::S1;
|
||||
#else
|
||||
int targetReg = ARMRegisters::pc;
|
||||
#endif
|
||||
int tmpReg = ARMRegisters::S1;
|
||||
|
||||
if (base == ARMRegisters::sp)
|
||||
offset += 4;
|
||||
|
||||
if (offset >= 0) {
|
||||
if (offset <= 0xfff) {
|
||||
prepareCall();
|
||||
m_assembler.dtr_u(true, ARMRegisters::pc, base, offset);
|
||||
m_assembler.dtr_u(true, targetReg, base, offset);
|
||||
} else if (offset <= 0xfffff) {
|
||||
m_assembler.add_r(ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
|
||||
m_assembler.add_r(tmpReg, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
|
||||
prepareCall();
|
||||
m_assembler.dtr_u(true, ARMRegisters::pc, ARMRegisters::S0, offset & 0xfff);
|
||||
m_assembler.dtr_u(true, targetReg, tmpReg, offset & 0xfff);
|
||||
} else {
|
||||
ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);
|
||||
ARMWord reg = m_assembler.getImm(offset, tmpReg);
|
||||
prepareCall();
|
||||
m_assembler.dtr_ur(true, ARMRegisters::pc, base, reg);
|
||||
m_assembler.dtr_ur(true, targetReg, base, reg);
|
||||
}
|
||||
} else {
|
||||
offset = -offset;
|
||||
if (offset <= 0xfff) {
|
||||
prepareCall();
|
||||
m_assembler.dtr_d(true, ARMRegisters::pc, base, offset);
|
||||
m_assembler.dtr_d(true, targetReg, base, offset);
|
||||
} else if (offset <= 0xfffff) {
|
||||
m_assembler.sub_r(ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
|
||||
m_assembler.sub_r(tmpReg, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
|
||||
prepareCall();
|
||||
m_assembler.dtr_d(true, ARMRegisters::pc, ARMRegisters::S0, offset & 0xfff);
|
||||
m_assembler.dtr_d(true, targetReg, tmpReg, offset & 0xfff);
|
||||
} else {
|
||||
ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);
|
||||
ARMWord reg = m_assembler.getImm(offset, tmpReg);
|
||||
prepareCall();
|
||||
m_assembler.dtr_dr(true, ARMRegisters::pc, base, reg);
|
||||
m_assembler.dtr_dr(true, targetReg, base, reg);
|
||||
}
|
||||
}
|
||||
#if WTF_ARM_ARCH_VERSION >= 5
|
||||
m_assembler.blx(targetReg);
|
||||
#endif
|
||||
}
|
||||
#else
|
||||
void call32(RegisterID base, int32_t offset)
|
||||
@ -1011,7 +1107,7 @@ protected:
|
||||
m_assembler.dtr_dr(true, ARMRegisters::S0, base, reg);
|
||||
}
|
||||
}
|
||||
m_assembler.blx_r(ARMRegisters::S0);
|
||||
m_assembler.blx(ARMRegisters::S0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -260,6 +260,21 @@ public:
|
||||
m_assembler.asr(dest, dest, imm.m_value & 0x1f);
|
||||
}
|
||||
|
||||
void urshift32(RegisterID shift_amount, RegisterID dest)
|
||||
{
|
||||
// Clamp the shift to the range 0..31
|
||||
ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f);
|
||||
ASSERT(armImm.isValid());
|
||||
m_assembler.ARM_and(dataTempRegister, shift_amount, armImm);
|
||||
|
||||
m_assembler.lsr(dest, dest, dataTempRegister);
|
||||
}
|
||||
|
||||
void urshift32(Imm32 imm, RegisterID dest)
|
||||
{
|
||||
m_assembler.lsr(dest, dest, imm.m_value & 0x1f);
|
||||
}
|
||||
|
||||
void sub32(RegisterID src, RegisterID dest)
|
||||
{
|
||||
m_assembler.sub(dest, dest, src);
|
||||
@ -369,6 +384,20 @@ private:
|
||||
}
|
||||
}
|
||||
|
||||
void load8(ArmAddress address, RegisterID dest)
|
||||
{
|
||||
if (address.type == ArmAddress::HasIndex)
|
||||
m_assembler.ldrb(dest, address.base, address.u.index, address.u.scale);
|
||||
else if (address.u.offset >= 0) {
|
||||
ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset);
|
||||
ASSERT(armImm.isValid());
|
||||
m_assembler.ldrb(dest, address.base, armImm);
|
||||
} else {
|
||||
ASSERT(address.u.offset >= -255);
|
||||
m_assembler.ldrb(dest, address.base, address.u.offset, true, false);
|
||||
}
|
||||
}
|
||||
|
||||
void store32(RegisterID src, ArmAddress address)
|
||||
{
|
||||
if (address.type == ArmAddress::HasIndex)
|
||||
@ -405,6 +434,11 @@ public:
|
||||
m_assembler.ldr(dest, addressTempRegister, ARMThumbImmediate::makeUInt16(0));
|
||||
}
|
||||
|
||||
void load8(ImplicitAddress address, RegisterID dest)
|
||||
{
|
||||
load8(setupArmAddress(address), dest);
|
||||
}
|
||||
|
||||
DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
|
||||
{
|
||||
DataLabel32 label = moveWithPatch(Imm32(address.offset), dataTempRegister);
|
||||
@ -425,6 +459,11 @@ public:
|
||||
m_assembler.ldrh(dest, makeBaseIndexBase(address), address.index, address.scale);
|
||||
}
|
||||
|
||||
void load16(ImplicitAddress address, RegisterID dest)
|
||||
{
|
||||
m_assembler.ldrh(dest, address.base, address.offset);
|
||||
}
|
||||
|
||||
DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
|
||||
{
|
||||
DataLabel32 label = moveWithPatch(Imm32(address.offset), dataTempRegister);
|
||||
@ -477,6 +516,11 @@ public:
|
||||
// In short, FIXME:.
|
||||
bool supportsFloatingPointTruncate() const { return false; }
|
||||
|
||||
bool supportsFloatingPointSqrt() const
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void loadDouble(ImplicitAddress address, FPRegisterID dest)
|
||||
{
|
||||
RegisterID base = address.base;
|
||||
@ -540,6 +584,11 @@ public:
|
||||
mulDouble(fpTempRegister, dest);
|
||||
}
|
||||
|
||||
void sqrtDouble(FPRegisterID, FPRegisterID)
|
||||
{
|
||||
ASSERT_NOT_REACHED();
|
||||
}
|
||||
|
||||
void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
|
||||
{
|
||||
m_assembler.vmov(fpTempRegister, src);
|
||||
@ -794,6 +843,19 @@ public:
|
||||
return branch32(cond, addressTempRegister, Imm32(right.m_value << 16));
|
||||
}
|
||||
|
||||
Jump branch8(Condition cond, RegisterID left, Imm32 right)
|
||||
{
|
||||
compare32(left, right);
|
||||
return Jump(makeBranch(cond));
|
||||
}
|
||||
|
||||
Jump branch8(Condition cond, Address left, Imm32 right)
|
||||
{
|
||||
// use addressTempRegister incase the branch8 we call uses dataTempRegister. :-/
|
||||
load8(left, addressTempRegister);
|
||||
return branch8(cond, addressTempRegister, right);
|
||||
}
|
||||
|
||||
Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask)
|
||||
{
|
||||
ASSERT((cond == Zero) || (cond == NonZero));
|
||||
@ -824,6 +886,21 @@ public:
|
||||
return branchTest32(cond, addressTempRegister, mask);
|
||||
}
|
||||
|
||||
Jump branchTest8(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1))
|
||||
{
|
||||
ASSERT((cond == Zero) || (cond == NonZero));
|
||||
test32(reg, mask);
|
||||
return Jump(makeBranch(cond));
|
||||
}
|
||||
|
||||
Jump branchTest8(Condition cond, Address address, Imm32 mask = Imm32(-1))
|
||||
{
|
||||
ASSERT((cond == Zero) || (cond == NonZero));
|
||||
// use addressTempRegister incase the branchTest8 we call uses dataTempRegister. :-/
|
||||
load8(address, addressTempRegister);
|
||||
return branchTest8(cond, addressTempRegister, mask);
|
||||
}
|
||||
|
||||
Jump jump()
|
||||
{
|
||||
return Jump(makeJump());
|
||||
@ -974,6 +1051,14 @@ public:
|
||||
m_assembler.mov(dest, ARMThumbImmediate::makeUInt16(0));
|
||||
}
|
||||
|
||||
void setTest8(Condition cond, Address address, Imm32 mask, RegisterID dest)
|
||||
{
|
||||
load8(address, dataTempRegister);
|
||||
test32(dataTempRegister, mask);
|
||||
m_assembler.it(armV7Condition(cond), false);
|
||||
m_assembler.mov(dest, ARMThumbImmediate::makeUInt16(1));
|
||||
m_assembler.mov(dest, ARMThumbImmediate::makeUInt16(0));
|
||||
}
|
||||
|
||||
DataLabel32 moveWithPatch(Imm32 imm, RegisterID dst)
|
||||
{
|
||||
|
||||
@ -69,3 +69,6 @@ private:
|
||||
};
|
||||
|
||||
} // namespace JSC
|
||||
|
||||
#endif /* _include_assembler_moco_stubs_h_ */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user