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Bug 1136226 - Wasm: Add opcodes for small integer SIMD types. r=sunfish
This commit is contained in:
Jakob Stoklund Olesen
parent
d512bedc76
commit
d12579deb1
@ -289,6 +289,40 @@ enum class Expr
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// SIMD
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#define SIMD_OPCODE(TYPE, OP) TYPE##OP,
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#define _(OP) SIMD_OPCODE(I8x16, OP)
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FORALL_INT8X16_ASMJS_OP(_)
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I8x16Constructor,
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I8x16Const,
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#undef _
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// Unsigned I8x16 operations. These are the SIMD.Uint8x16 operations that
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// behave differently from their SIMD.Int8x16 counterparts.
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I8x16extractLaneU,
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I8x16addSaturateU,
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I8x16subSaturateU,
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I8x16shiftRightByScalarU,
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I8x16lessThanU,
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I8x16lessThanOrEqualU,
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I8x16greaterThanU,
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I8x16greaterThanOrEqualU,
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#define SIMD_OPCODE(TYPE, OP) TYPE##OP,
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#define _(OP) SIMD_OPCODE(I16x8, OP)
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FORALL_INT16X8_ASMJS_OP(_)
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I16x8Constructor,
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I16x8Const,
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#undef _
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// Unsigned I16x8 operations. These are the SIMD.Uint16x8 operations that
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// behave differently from their SIMD.Int16x8 counterparts.
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I16x8extractLaneU,
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I16x8addSaturateU,
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I16x8subSaturateU,
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I16x8shiftRightByScalarU,
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I16x8lessThanU,
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I16x8lessThanOrEqualU,
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I16x8greaterThanU,
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I16x8greaterThanOrEqualU,
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#define SIMD_OPCODE(TYPE, OP) TYPE##OP,
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#define _(OP) SIMD_OPCODE(I32x4, OP)
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FORALL_INT32X4_ASMJS_OP(_)
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I32x4Constructor,
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@ -307,6 +341,21 @@ enum class Expr
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F32x4Constructor,
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F32x4Const,
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#undef _
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#define _(OP) SIMD_OPCODE(B8x16, OP)
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FORALL_BOOL_SIMD_OP(_)
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B8x16Constructor,
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B8x16Const,
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#undef _
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#undef OPCODE
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#define _(OP) SIMD_OPCODE(B16x8, OP)
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FORALL_BOOL_SIMD_OP(_)
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B16x8Constructor,
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B16x8Const,
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#undef _
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#undef OPCODE
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#define _(OP) SIMD_OPCODE(B32x4, OP)
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FORALL_BOOL_SIMD_OP(_)
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B32x4Constructor,
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@ -41,8 +41,16 @@ wasm::Classify(Expr expr)
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return ExprKind::F32;
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case Expr::F64Const:
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return ExprKind::F64;
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case Expr::I8x16Const:
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return ExprKind::I8x16;
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case Expr::I16x8Const:
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return ExprKind::I16x8;
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case Expr::I32x4Const:
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return ExprKind::I32x4;
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case Expr::B8x16Const:
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return ExprKind::B8x16;
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case Expr::B16x8Const:
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return ExprKind::B16x8;
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case Expr::B32x4Const:
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return ExprKind::B32x4;
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case Expr::F32x4Const:
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@ -82,6 +90,10 @@ wasm::Classify(Expr expr)
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case Expr::F64Exp:
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case Expr::F64Log:
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case Expr::I32Neg:
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case Expr::I8x16neg:
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case Expr::I8x16not:
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case Expr::I16x8neg:
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case Expr::I16x8not:
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case Expr::I32x4neg:
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case Expr::I32x4not:
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case Expr::F32x4neg:
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@ -89,6 +101,8 @@ wasm::Classify(Expr expr)
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case Expr::F32x4abs:
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case Expr::F32x4reciprocalApproximation:
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case Expr::F32x4reciprocalSqrtApproximation:
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case Expr::B8x16not:
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case Expr::B16x8not:
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case Expr::B32x4not:
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return ExprKind::Unary;
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case Expr::I32Add:
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@ -140,6 +154,26 @@ wasm::Classify(Expr expr)
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case Expr::F64Mod:
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case Expr::F64Pow:
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case Expr::F64Atan2:
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case Expr::I8x16add:
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case Expr::I8x16sub:
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case Expr::I8x16mul:
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case Expr::I8x16addSaturate:
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case Expr::I8x16subSaturate:
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case Expr::I8x16addSaturateU:
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case Expr::I8x16subSaturateU:
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case Expr::I8x16and:
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case Expr::I8x16or:
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case Expr::I8x16xor:
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case Expr::I16x8add:
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case Expr::I16x8sub:
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case Expr::I16x8mul:
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case Expr::I16x8addSaturate:
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case Expr::I16x8subSaturate:
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case Expr::I16x8addSaturateU:
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case Expr::I16x8subSaturateU:
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case Expr::I16x8and:
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case Expr::I16x8or:
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case Expr::I16x8xor:
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case Expr::I32x4add:
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case Expr::I32x4sub:
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case Expr::I32x4mul:
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@ -154,6 +188,12 @@ wasm::Classify(Expr expr)
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case Expr::F32x4max:
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case Expr::F32x4minNum:
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case Expr::F32x4maxNum:
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case Expr::B8x16and:
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case Expr::B8x16or:
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case Expr::B8x16xor:
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case Expr::B16x8and:
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case Expr::B16x8or:
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case Expr::B16x8xor:
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case Expr::B32x4and:
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case Expr::B32x4or:
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case Expr::B32x4xor:
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@ -240,6 +280,8 @@ wasm::Classify(Expr expr)
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case Expr::I64Load:
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case Expr::F32Load:
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case Expr::F64Load:
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case Expr::I8x16load:
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case Expr::I16x8load:
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case Expr::I32x4load:
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case Expr::I32x4load1:
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case Expr::I32x4load2:
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@ -260,6 +302,8 @@ wasm::Classify(Expr expr)
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case Expr::F64Store:
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case Expr::F32StoreF64:
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case Expr::F64StoreF32:
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case Expr::I8x16store:
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case Expr::I16x8store:
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case Expr::I32x4store:
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case Expr::I32x4store1:
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case Expr::I32x4store2:
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@ -303,41 +347,99 @@ wasm::Classify(Expr expr)
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return ExprKind::AtomicCompareExchange;
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case Expr::I32AtomicsExchange:
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return ExprKind::AtomicExchange;
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case Expr::I8x16extractLane:
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case Expr::I8x16extractLaneU:
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case Expr::I16x8extractLane:
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case Expr::I16x8extractLaneU:
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case Expr::I32x4extractLane:
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case Expr::F32x4extractLane:
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case Expr::B8x16extractLane:
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case Expr::B16x8extractLane:
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case Expr::B32x4extractLane:
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return ExprKind::ExtractLane;
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case Expr::I8x16replaceLane:
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case Expr::I16x8replaceLane:
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case Expr::I32x4replaceLane:
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case Expr::F32x4replaceLane:
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case Expr::B8x16replaceLane:
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case Expr::B16x8replaceLane:
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case Expr::B32x4replaceLane:
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return ExprKind::ReplaceLane;
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case Expr::I8x16swizzle:
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case Expr::I16x8swizzle:
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case Expr::I32x4swizzle:
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case Expr::F32x4swizzle:
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return ExprKind::Swizzle;
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case Expr::I8x16shuffle:
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case Expr::I16x8shuffle:
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case Expr::I32x4shuffle:
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case Expr::F32x4shuffle:
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return ExprKind::Shuffle;
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case Expr::I32x4splat:
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case Expr::F32x4splat:
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case Expr::B32x4splat:
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case Expr::I16x8check:
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case Expr::I16x8splat:
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case Expr::I32x4check:
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case Expr::I32x4splat:
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case Expr::I8x16check:
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case Expr::I8x16splat:
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case Expr::F32x4check:
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case Expr::F32x4splat:
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case Expr::B16x8check:
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case Expr::B16x8splat:
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case Expr::B32x4check:
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case Expr::B32x4splat:
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case Expr::B8x16check:
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case Expr::B8x16splat:
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return ExprKind::Splat;
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case Expr::I8x16select:
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case Expr::I16x8select:
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case Expr::I32x4select:
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case Expr::F32x4select:
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return ExprKind::SimdSelect;
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case Expr::I8x16Constructor:
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case Expr::I16x8Constructor:
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case Expr::I32x4Constructor:
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case Expr::F32x4Constructor:
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case Expr::B8x16Constructor:
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case Expr::B16x8Constructor:
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case Expr::B32x4Constructor:
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return ExprKind::SimdCtor;
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case Expr::B32x4anyTrue:
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case Expr::B8x16allTrue:
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case Expr::B8x16anyTrue:
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case Expr::B16x8allTrue:
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case Expr::B16x8anyTrue:
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case Expr::B32x4allTrue:
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case Expr::B32x4anyTrue:
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return ExprKind::SimdBooleanReduction;
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case Expr::I8x16shiftLeftByScalar:
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case Expr::I8x16shiftRightByScalar:
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case Expr::I8x16shiftRightByScalarU:
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case Expr::I16x8shiftLeftByScalar:
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case Expr::I16x8shiftRightByScalar:
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case Expr::I16x8shiftRightByScalarU:
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case Expr::I32x4shiftLeftByScalar:
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case Expr::I32x4shiftRightByScalar:
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case Expr::I32x4shiftRightByScalarU:
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return ExprKind::SimdShiftByScalar;
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case Expr::I8x16equal:
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case Expr::I8x16notEqual:
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case Expr::I8x16greaterThan:
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case Expr::I8x16greaterThanOrEqual:
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case Expr::I8x16lessThan:
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case Expr::I8x16lessThanOrEqual:
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case Expr::I8x16greaterThanU:
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case Expr::I8x16greaterThanOrEqualU:
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case Expr::I8x16lessThanU:
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case Expr::I8x16lessThanOrEqualU:
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case Expr::I16x8equal:
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case Expr::I16x8notEqual:
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case Expr::I16x8greaterThan:
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case Expr::I16x8greaterThanOrEqual:
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case Expr::I16x8lessThan:
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case Expr::I16x8lessThanOrEqual:
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case Expr::I16x8greaterThanU:
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case Expr::I16x8greaterThanOrEqualU:
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case Expr::I16x8lessThanU:
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case Expr::I16x8lessThanOrEqualU:
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case Expr::I32x4equal:
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case Expr::I32x4notEqual:
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case Expr::I32x4greaterThan:
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@ -3119,24 +3119,52 @@ EmitExpr(FunctionCompiler& f)
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#define CASE(TYPE, OP, SIGN) \
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case Expr::TYPE##OP: \
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return EmitSimdOp(f, ValType::TYPE, SimdOperation::Fn_##OP, SIGN);
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#define I32CASE(OP) CASE(I32x4, OP, SimdSign::Signed)
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#define F32CASE(OP) CASE(F32x4, OP, SimdSign::NotApplicable)
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#define B32CASE(OP) CASE(B32x4, OP, SimdSign::NotApplicable)
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#define I8x16CASE(OP) CASE(I8x16, OP, SimdSign::Signed)
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#define I16x8CASE(OP) CASE(I16x8, OP, SimdSign::Signed)
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#define I32x4CASE(OP) CASE(I32x4, OP, SimdSign::Signed)
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#define F32x4CASE(OP) CASE(F32x4, OP, SimdSign::NotApplicable)
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#define B8x16CASE(OP) CASE(B8x16, OP, SimdSign::NotApplicable)
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#define B16x8CASE(OP) CASE(B16x8, OP, SimdSign::NotApplicable)
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#define B32x4CASE(OP) CASE(B32x4, OP, SimdSign::NotApplicable)
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#define ENUMERATE(TYPE, FORALL, DO) \
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case Expr::TYPE##Constructor: \
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return EmitSimdOp(f, ValType::TYPE, SimdOperation::Constructor, SimdSign::NotApplicable); \
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FORALL(DO)
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ENUMERATE(I32x4, FORALL_INT32X4_ASMJS_OP, I32CASE)
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ENUMERATE(F32x4, FORALL_FLOAT32X4_ASMJS_OP, F32CASE)
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ENUMERATE(B32x4, FORALL_BOOL_SIMD_OP, B32CASE)
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ENUMERATE(I8x16, FORALL_INT8X16_ASMJS_OP, I8x16CASE)
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ENUMERATE(I16x8, FORALL_INT16X8_ASMJS_OP, I16x8CASE)
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ENUMERATE(I32x4, FORALL_INT32X4_ASMJS_OP, I32x4CASE)
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ENUMERATE(F32x4, FORALL_FLOAT32X4_ASMJS_OP, F32x4CASE)
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ENUMERATE(B8x16, FORALL_BOOL_SIMD_OP, B8x16CASE)
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ENUMERATE(B16x8, FORALL_BOOL_SIMD_OP, B16x8CASE)
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ENUMERATE(B32x4, FORALL_BOOL_SIMD_OP, B32x4CASE)
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#undef CASE
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#undef I32CASE
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#undef F32CASE
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#undef B32CASE
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#undef I8x16CASE
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#undef I16x8CASE
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#undef I32x4CASE
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#undef F32x4CASE
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#undef B8x16CASE
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#undef B16x8CASE
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#undef B32x4CASE
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#undef ENUMERATE
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case Expr::I8x16Const: {
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I8x16 i8x16;
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if (!f.iter().readI8x16Const(&i8x16))
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return false;
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f.iter().setResult(f.constant(SimdConstant::CreateX16(i8x16), MIRType::Int8x16));
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return true;
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}
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case Expr::I16x8Const: {
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I16x8 i16x8;
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if (!f.iter().readI16x8Const(&i16x8))
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return false;
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f.iter().setResult(f.constant(SimdConstant::CreateX8(i16x8), MIRType::Int16x8));
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return true;
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}
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case Expr::I32x4Const: {
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I32x4 i32x4;
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if (!f.iter().readI32x4Const(&i32x4))
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@ -3153,6 +3181,22 @@ EmitExpr(FunctionCompiler& f)
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f.iter().setResult(f.constant(SimdConstant::CreateX4(f32x4), MIRType::Float32x4));
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return true;
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}
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case Expr::B8x16Const: {
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I8x16 i8x16;
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if (!f.iter().readB8x16Const(&i8x16))
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return false;
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f.iter().setResult(f.constant(SimdConstant::CreateX16(i8x16), MIRType::Bool8x16));
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return true;
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}
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case Expr::B16x8Const: {
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I16x8 i16x8;
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if (!f.iter().readB16x8Const(&i16x8))
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return false;
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f.iter().setResult(f.constant(SimdConstant::CreateX8(i16x8), MIRType::Bool16x8));
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return true;
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}
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case Expr::B32x4Const: {
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I32x4 i32x4;
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if (!f.iter().readB32x4Const(&i32x4))
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@ -3163,6 +3207,40 @@ EmitExpr(FunctionCompiler& f)
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}
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// SIMD unsigned integer operations.
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case Expr::I8x16addSaturateU:
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return EmitSimdOp(f, ValType::I8x16, SimdOperation::Fn_addSaturate, SimdSign::Unsigned);
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case Expr::I8x16subSaturateU:
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return EmitSimdOp(f, ValType::I8x16, SimdOperation::Fn_subSaturate, SimdSign::Unsigned);
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case Expr::I8x16shiftRightByScalarU:
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return EmitSimdOp(f, ValType::I8x16, SimdOperation::Fn_shiftRightByScalar, SimdSign::Unsigned);
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case Expr::I8x16lessThanU:
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return EmitSimdOp(f, ValType::I8x16, SimdOperation::Fn_lessThan, SimdSign::Unsigned);
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case Expr::I8x16lessThanOrEqualU:
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return EmitSimdOp(f, ValType::I8x16, SimdOperation::Fn_lessThanOrEqual, SimdSign::Unsigned);
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case Expr::I8x16greaterThanU:
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return EmitSimdOp(f, ValType::I8x16, SimdOperation::Fn_greaterThan, SimdSign::Unsigned);
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case Expr::I8x16greaterThanOrEqualU:
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return EmitSimdOp(f, ValType::I8x16, SimdOperation::Fn_greaterThanOrEqual, SimdSign::Unsigned);
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case Expr::I8x16extractLaneU:
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return EmitSimdOp(f, ValType::I8x16, SimdOperation::Fn_extractLane, SimdSign::Unsigned);
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case Expr::I16x8addSaturateU:
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return EmitSimdOp(f, ValType::I16x8, SimdOperation::Fn_addSaturate, SimdSign::Unsigned);
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case Expr::I16x8subSaturateU:
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return EmitSimdOp(f, ValType::I16x8, SimdOperation::Fn_subSaturate, SimdSign::Unsigned);
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case Expr::I16x8shiftRightByScalarU:
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return EmitSimdOp(f, ValType::I16x8, SimdOperation::Fn_shiftRightByScalar, SimdSign::Unsigned);
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case Expr::I16x8lessThanU:
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return EmitSimdOp(f, ValType::I16x8, SimdOperation::Fn_lessThan, SimdSign::Unsigned);
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case Expr::I16x8lessThanOrEqualU:
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return EmitSimdOp(f, ValType::I16x8, SimdOperation::Fn_lessThanOrEqual, SimdSign::Unsigned);
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case Expr::I16x8greaterThanU:
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return EmitSimdOp(f, ValType::I16x8, SimdOperation::Fn_greaterThan, SimdSign::Unsigned);
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case Expr::I16x8greaterThanOrEqualU:
|
||||
return EmitSimdOp(f, ValType::I16x8, SimdOperation::Fn_greaterThanOrEqual, SimdSign::Unsigned);
|
||||
case Expr::I16x8extractLaneU:
|
||||
return EmitSimdOp(f, ValType::I16x8, SimdOperation::Fn_extractLane, SimdSign::Unsigned);
|
||||
|
||||
case Expr::I32x4shiftRightByScalarU:
|
||||
return EmitSimdOp(f, ValType::I32x4, SimdOperation::Fn_shiftRightByScalar, SimdSign::Unsigned);
|
||||
case Expr::I32x4lessThanU:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user