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Bug 1205167 - IonMonkey: MIPS: Import MIPS64 support into Assembler-mips-shared. r=froydnj f=rankov

Browse Source 
---
 js/src/jit/mips-shared/Assembler-mips-shared.cpp | 280 +++++++++++++++++++++++
 js/src/jit/mips-shared/Assembler-mips-shared.h   | 105 ++++++++-
 2 files changed, 379 insertions(+), 6 deletions(-)
This commit is contained in:
Heiher 2015-10-13 17:15:46 +08:00
parent 6e137587df
commit d4381dd681
2 changed files with 379 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

280
js/src/jit/mips-shared/Assembler-mips-shared.cpp
View File

@ -480,12 +480,31 @@ AssemblerMIPSShared::as_addiu(Register rd, Register rs, int32_t j)
return writeInst(InstImm(op_addiu, rs, rd, Imm16(j)).encode());
}
BufferOffset
AssemblerMIPSShared::as_daddu(Register rd, Register rs, Register rt)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_daddu).encode());
}
BufferOffset
AssemblerMIPSShared::as_daddiu(Register rd, Register rs, int32_t j)
{
MOZ_ASSERT(Imm16::IsInSignedRange(j));
return writeInst(InstImm(op_daddiu, rs, rd, Imm16(j)).encode());
}
BufferOffset
AssemblerMIPSShared::as_subu(Register rd, Register rs, Register rt)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_subu).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsubu(Register rd, Register rs, Register rt)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_dsubu).encode());
}
BufferOffset
AssemblerMIPSShared::as_mult(Register rs, Register rt)
{
@ -498,6 +517,18 @@ AssemblerMIPSShared::as_multu(Register rs, Register rt)
return writeInst(InstReg(op_special, rs, rt, ff_multu).encode());
}
BufferOffset
AssemblerMIPSShared::as_dmult(Register rs, Register rt)
{
return writeInst(InstReg(op_special, rs, rt, ff_dmult).encode());
}
BufferOffset
AssemblerMIPSShared::as_dmultu(Register rs, Register rt)
{
return writeInst(InstReg(op_special, rs, rt, ff_dmultu).encode());
}
BufferOffset
AssemblerMIPSShared::as_div(Register rs, Register rt)
{
@ -510,6 +541,18 @@ AssemblerMIPSShared::as_divu(Register rs, Register rt)
return writeInst(InstReg(op_special, rs, rt, ff_divu).encode());
}
BufferOffset
AssemblerMIPSShared::as_ddiv(Register rs, Register rt)
{
return writeInst(InstReg(op_special, rs, rt, ff_ddiv).encode());
}
BufferOffset
AssemblerMIPSShared::as_ddivu(Register rs, Register rt)
{
return writeInst(InstReg(op_special, rs, rt, ff_ddivu).encode());
}
BufferOffset
AssemblerMIPSShared::as_mul(Register rd, Register rs, Register rt)
{
@ -531,12 +574,32 @@ AssemblerMIPSShared::as_sll(Register rd, Register rt, uint16_t sa)
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_sll).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsll(Register rd, Register rt, uint16_t sa)
{
MOZ_ASSERT(sa < 32);
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_dsll).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsll32(Register rd, Register rt, uint16_t sa)
{
MOZ_ASSERT(31 < sa && sa < 64);
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa - 32, ff_dsll32).encode());
}
BufferOffset
AssemblerMIPSShared::as_sllv(Register rd, Register rt, Register rs)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_sllv).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsllv(Register rd, Register rt, Register rs)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_dsllv).encode());
}
BufferOffset
AssemblerMIPSShared::as_srl(Register rd, Register rt, uint16_t sa)
{
@ -544,12 +607,32 @@ AssemblerMIPSShared::as_srl(Register rd, Register rt, uint16_t sa)
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_srl).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsrl(Register rd, Register rt, uint16_t sa)
{
MOZ_ASSERT(sa < 32);
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_dsrl).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsrl32(Register rd, Register rt, uint16_t sa)
{
MOZ_ASSERT(31 < sa && sa < 64);
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa - 32, ff_dsrl32).encode());
}
BufferOffset
AssemblerMIPSShared::as_srlv(Register rd, Register rt, Register rs)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_srlv).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsrlv(Register rd, Register rt, Register rs)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_dsrlv).encode());
}
BufferOffset
AssemblerMIPSShared::as_sra(Register rd, Register rt, uint16_t sa)
{
@ -557,12 +640,32 @@ AssemblerMIPSShared::as_sra(Register rd, Register rt, uint16_t sa)
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_sra).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsra(Register rd, Register rt, uint16_t sa)
{
MOZ_ASSERT(sa < 32);
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_dsra).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsra32(Register rd, Register rt, uint16_t sa)
{
MOZ_ASSERT(31 < sa && sa < 64);
return writeInst(InstReg(op_special, rs_zero, rt, rd, sa - 32, ff_dsra32).encode());
}
BufferOffset
AssemblerMIPSShared::as_srav(Register rd, Register rt, Register rs)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_srav).encode());
}
BufferOffset
AssemblerMIPSShared::as_dsrav(Register rd, Register rt, Register rs)
{
return writeInst(InstReg(op_special, rs, rt, rd, ff_dsrav).encode());
}
BufferOffset
AssemblerMIPSShared::as_rotr(Register rd, Register rt, uint16_t sa)
{
@ -570,12 +673,32 @@ AssemblerMIPSShared::as_rotr(Register rd, Register rt, uint16_t sa)
return writeInst(InstReg(op_special, rs_one, rt, rd, sa, ff_srl).encode());
}
BufferOffset
AssemblerMIPSShared::as_drotr(Register rd, Register rt, uint16_t sa)
{
MOZ_ASSERT(sa < 32);
return writeInst(InstReg(op_special, rs_one, rt, rd, sa, ff_dsrl).encode());
}
BufferOffset
AssemblerMIPSShared::as_drotr32(Register rd, Register rt, uint16_t sa)
{
MOZ_ASSERT(31 < sa && sa < 64);
return writeInst(InstReg(op_special, rs_one, rt, rd, sa - 32, ff_dsrl32).encode());
}
BufferOffset
AssemblerMIPSShared::as_rotrv(Register rd, Register rt, Register rs)
{
return writeInst(InstReg(op_special, rs, rt, rd, 1, ff_srlv).encode());
}
BufferOffset
AssemblerMIPSShared::as_drotrv(Register rd, Register rt, Register rs)
{
return writeInst(InstReg(op_special, rs, rt, rd, 1, ff_dsrlv).encode());
}
// Load and store instructions
BufferOffset
AssemblerMIPSShared::as_lb(Register rd, Register rs, int16_t off)
@ -607,6 +730,12 @@ AssemblerMIPSShared::as_lw(Register rd, Register rs, int16_t off)
return writeInst(InstImm(op_lw, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_lwu(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_lwu, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_lwl(Register rd, Register rs, int16_t off)
{
@ -619,6 +748,30 @@ AssemblerMIPSShared::as_lwr(Register rd, Register rs, int16_t off)
return writeInst(InstImm(op_lwr, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_ll(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_ll, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_ld(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_ld, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_ldl(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_ldl, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_ldr(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_ldr, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_sb(Register rd, Register rs, int16_t off)
{
@ -649,6 +802,30 @@ AssemblerMIPSShared::as_swr(Register rd, Register rs, int16_t off)
return writeInst(InstImm(op_swr, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_sc(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_sc, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_sd(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_sd, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_sdl(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_sdl, rs, rd, Imm16(off)).encode());
}
BufferOffset
AssemblerMIPSShared::as_sdr(Register rd, Register rs, int16_t off)
{
return writeInst(InstImm(op_sdr, rs, rd, Imm16(off)).encode());
}
// Move from HI/LO register.
BufferOffset
AssemblerMIPSShared::as_mfhi(Register rd)
@ -725,6 +902,12 @@ AssemblerMIPSShared::as_clz(Register rd, Register rs)
return writeInst(InstReg(op_special2, rs, rd, rd, ff_clz).encode());
}
BufferOffset
AssemblerMIPSShared::as_dclz(Register rd, Register rs)
{
return writeInst(InstReg(op_special2, rs, rd, rd, ff_dclz).encode());
}
BufferOffset
AssemblerMIPSShared::as_ins(Register rt, Register rs, uint16_t pos, uint16_t size)
{
@ -734,6 +917,33 @@ AssemblerMIPSShared::as_ins(Register rt, Register rs, uint16_t pos, uint16_t siz
return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_ins).encode());
}
BufferOffset
AssemblerMIPSShared::as_dins(Register rt, Register rs, uint16_t pos, uint16_t size)
{
MOZ_ASSERT(pos < 32 && size != 0 && size <= 32 && pos + size != 0 && pos + size <= 32);
Register rd;
rd = Register::FromCode(pos + size - 1);
return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_dins).encode());
}
BufferOffset
AssemblerMIPSShared::as_dinsm(Register rt, Register rs, uint16_t pos, uint16_t size)
{
MOZ_ASSERT(pos < 32 && size >= 2 && size <= 64 && pos + size > 32 && pos + size <= 64);
Register rd;
rd = Register::FromCode(pos + size - 1 - 32);
return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_dinsm).encode());
}
BufferOffset
AssemblerMIPSShared::as_dinsu(Register rt, Register rs, uint16_t pos, uint16_t size)
{
MOZ_ASSERT(pos >= 32 && pos < 64 && size >= 1 && size <= 32 && pos + size > 32 && pos + size <= 64);
Register rd;
rd = Register::FromCode(pos + size - 1 - 32);
return writeInst(InstReg(op_special3, rs, rt, rd, pos - 32, ff_dinsu).encode());
}
BufferOffset
AssemblerMIPSShared::as_ext(Register rt, Register rs, uint16_t pos, uint16_t size)
{
@ -743,6 +953,46 @@ AssemblerMIPSShared::as_ext(Register rt, Register rs, uint16_t pos, uint16_t siz
return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_ext).encode());
}
// Sign extend
BufferOffset
AssemblerMIPSShared::as_seb(Register rd, Register rt)
{
return writeInst(InstReg(op_special3, zero, rt, rd, 16, ff_bshfl).encode());
}
BufferOffset
AssemblerMIPSShared::as_seh(Register rd, Register rt)
{
return writeInst(InstReg(op_special3, zero, rt, rd, 24, ff_bshfl).encode());
}
BufferOffset
AssemblerMIPSShared::as_dext(Register rt, Register rs, uint16_t pos, uint16_t size)
{
MOZ_ASSERT(pos < 32 && size != 0 && size <= 32 && pos + size != 0 && pos + size <= 63);
Register rd;
rd = Register::FromCode(size - 1);
return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_dext).encode());
}
BufferOffset
AssemblerMIPSShared::as_dextm(Register rt, Register rs, uint16_t pos, uint16_t size)
{
MOZ_ASSERT(pos < 32 && size > 32 && size <= 64 && pos + size > 32 && pos + size <= 64);
Register rd;
rd = Register::FromCode(size - 1 - 32);
return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_dextm).encode());
}
BufferOffset
AssemblerMIPSShared::as_dextu(Register rt, Register rs, uint16_t pos, uint16_t size)
{
MOZ_ASSERT(pos >= 32 && pos < 64 && size != 0 && size <= 32 && pos + size > 32 && pos + size <= 64);
Register rd;
rd = Register::FromCode(size - 1);
return writeInst(InstReg(op_special3, rs, rt, rd, pos - 32, ff_dextu).encode());
}
// FP instructions
BufferOffset
AssemblerMIPSShared::as_ld(FloatRegister fd, Register base, int32_t off)
@ -796,6 +1046,30 @@ AssemblerMIPSShared::as_mfc1(Register rt, FloatRegister fs)
return writeInst(InstReg(op_cop1, rs_mfc1, rt, fs).encode());
}
BufferOffset
AssemblerMIPSShared::as_mthc1(Register rt, FloatRegister fs)
{
return writeInst(InstReg(op_cop1, rs_mthc1, rt, fs).encode());
}
BufferOffset
AssemblerMIPSShared::as_mfhc1(Register rt, FloatRegister fs)
{
return writeInst(InstReg(op_cop1, rs_mfhc1, rt, fs).encode());
}
BufferOffset
AssemblerMIPSShared::as_dmtc1(Register rt, FloatRegister fs)
{
return writeInst(InstReg(op_cop1, rs_dmtc1, rt, fs).encode());
}
BufferOffset
AssemblerMIPSShared::as_dmfc1(Register rt, FloatRegister fs)
{
return writeInst(InstReg(op_cop1, rs_dmfc1, rt, fs).encode());
}
// FP convert instructions
BufferOffset
AssemblerMIPSShared::as_ceilws(FloatRegister fd, FloatRegister fs)
@ -845,6 +1119,12 @@ AssemblerMIPSShared::as_truncwd(FloatRegister fd, FloatRegister fs)
return writeInst(InstReg(op_cop1, rs_d, zero, fs, fd, ff_trunc_w_fmt).encode());
}
BufferOffset
AssemblerMIPSShared::as_cvtdl(FloatRegister fd, FloatRegister fs)
{
return writeInst(InstReg(op_cop1, rs_l, zero, fs, fd, ff_cvt_d_fmt).encode());
}
BufferOffset
AssemblerMIPSShared::as_cvtds(FloatRegister fd, FloatRegister fs)
{

105
js/src/jit/mips-shared/Assembler-mips-shared.h
View File

@ -30,14 +30,18 @@ static MOZ_CONSTEXPR_VAR Register a0 = { Registers::a0 };
static MOZ_CONSTEXPR_VAR Register a1 = { Registers::a1 };
static MOZ_CONSTEXPR_VAR Register a2 = { Registers::a2 };
static MOZ_CONSTEXPR_VAR Register a3 = { Registers::a3 };
static MOZ_CONSTEXPR_VAR Register a4 = { Registers::ta0 };
static MOZ_CONSTEXPR_VAR Register a5 = { Registers::ta1 };
static MOZ_CONSTEXPR_VAR Register a6 = { Registers::ta2 };
static MOZ_CONSTEXPR_VAR Register a7 = { Registers::ta3 };
static MOZ_CONSTEXPR_VAR Register t0 = { Registers::t0 };
static MOZ_CONSTEXPR_VAR Register t1 = { Registers::t1 };
static MOZ_CONSTEXPR_VAR Register t2 = { Registers::t2 };
static MOZ_CONSTEXPR_VAR Register t3 = { Registers::t3 };
static MOZ_CONSTEXPR_VAR Register t4 = { Registers::t4 };
static MOZ_CONSTEXPR_VAR Register t5 = { Registers::t5 };
static MOZ_CONSTEXPR_VAR Register t6 = { Registers::t6 };
static MOZ_CONSTEXPR_VAR Register t7 = { Registers::t7 };
static MOZ_CONSTEXPR_VAR Register t4 = { Registers::ta0 };
static MOZ_CONSTEXPR_VAR Register t5 = { Registers::ta1 };
static MOZ_CONSTEXPR_VAR Register t6 = { Registers::ta2 };
static MOZ_CONSTEXPR_VAR Register t7 = { Registers::ta3 };
static MOZ_CONSTEXPR_VAR Register s0 = { Registers::s0 };
static MOZ_CONSTEXPR_VAR Register s1 = { Registers::s1 };
static MOZ_CONSTEXPR_VAR Register s2 = { Registers::s2 };
@ -85,6 +89,10 @@ static MOZ_CONSTEXPR_VAR Register IntArgReg0 = a0;
static MOZ_CONSTEXPR_VAR Register IntArgReg1 = a1;
static MOZ_CONSTEXPR_VAR Register IntArgReg2 = a2;
static MOZ_CONSTEXPR_VAR Register IntArgReg3 = a3;
static MOZ_CONSTEXPR_VAR Register IntArgReg4 = a4;
static MOZ_CONSTEXPR_VAR Register IntArgReg5 = a5;
static MOZ_CONSTEXPR_VAR Register IntArgReg6 = a6;
static MOZ_CONSTEXPR_VAR Register IntArgReg7 = a7;
static MOZ_CONSTEXPR_VAR Register GlobalReg = s6; // used by Odin
static MOZ_CONSTEXPR_VAR Register HeapReg = s7; // used by Odin
static MOZ_CONSTEXPR_VAR Register CallTempNonArgRegs[] = CALL_TEMP_NON_ARG_REGS;
@ -246,6 +254,12 @@ enum Opcode {
op_blezl = 22 << OpcodeShift,
op_bgtzl = 23 << OpcodeShift,
op_daddi = 24 << OpcodeShift,
op_daddiu = 25 << OpcodeShift,
op_ldl = 26 << OpcodeShift,
op_ldr = 27 << OpcodeShift,
op_special2 = 28 << OpcodeShift,
op_special3 = 31 << OpcodeShift,
@ -256,17 +270,24 @@ enum Opcode {
op_lbu = 36 << OpcodeShift,
op_lhu = 37 << OpcodeShift,
op_lwr = 38 << OpcodeShift,
op_lwu = 39 << OpcodeShift,
op_sb = 40 << OpcodeShift,
op_sh = 41 << OpcodeShift,
op_swl = 42 << OpcodeShift,
op_sw = 43 << OpcodeShift,
op_sdl = 44 << OpcodeShift,
op_sdr = 45 << OpcodeShift,
op_swr = 46 << OpcodeShift,
op_ll = 48 << OpcodeShift,
op_lwc1 = 49 << OpcodeShift,
op_ldc1 = 53 << OpcodeShift,
op_ld = 55 << OpcodeShift,
op_sc = 56 << OpcodeShift,
op_swc1 = 57 << OpcodeShift,
op_sdc1 = 61 << OpcodeShift
op_sdc1 = 61 << OpcodeShift,
op_sd = 63 << OpcodeShift,
};
enum RSField {
@ -274,9 +295,11 @@ enum RSField {
// cop1 encoding of RS field.
rs_mfc1 = 0 << RSShift,
rs_one = 1 << RSShift,
rs_dmfc1 = 1 << RSShift,
rs_cfc1 = 2 << RSShift,
rs_mfhc1 = 3 << RSShift,
rs_mtc1 = 4 << RSShift,
rs_dmtc1 = 5 << RSShift,
rs_ctc1 = 6 << RSShift,
rs_mthc1 = 7 << RSShift,
rs_bc1 = 8 << RSShift,
@ -316,10 +339,18 @@ enum FunctionField {
ff_mfhi = 16,
ff_mflo = 18,
ff_dsllv = 20,
ff_dsrlv = 22,
ff_dsrav = 23,
ff_mult = 24,
ff_multu = 25,
ff_div = 26,
ff_divu = 27,
ff_dmult = 28,
ff_dmultu = 29,
ff_ddiv = 30,
ff_ddivu = 31,
ff_add = 32,
ff_addu = 33,
@ -332,6 +363,10 @@ enum FunctionField {
ff_slt = 42,
ff_sltu = 43,
ff_dadd = 44,
ff_daddu = 45,
ff_dsub = 46,
ff_dsubu = 47,
ff_tge = 48,
ff_tgeu = 49,
@ -339,15 +374,29 @@ enum FunctionField {
ff_tltu = 51,
ff_teq = 52,
ff_tne = 54,
ff_dsll = 56,
ff_dsrl = 58,
ff_dsra = 59,
ff_dsll32 = 60,
ff_dsrl32 = 62,
ff_dsra32 = 63,
// special2 encoding of function field.
ff_mul = 2,
ff_clz = 32,
ff_clo = 33,
ff_dclz = 36,
// special3 encoding of function field.
ff_ext = 0,
ff_dextm = 1,
ff_dextu = 2,
ff_dext = 3,
ff_ins = 4,
ff_dinsm = 5,
ff_dinsu = 6,
ff_dins = 7,
ff_bshfl = 32,
// cop1 encoding of function field.
ff_add_fmt = 0,
@ -812,12 +861,19 @@ class AssemblerMIPSShared : public AssemblerShared
// Arithmetic instructions
BufferOffset as_addu(Register rd, Register rs, Register rt);
BufferOffset as_addiu(Register rd, Register rs, int32_t j);
BufferOffset as_daddu(Register rd, Register rs, Register rt);
BufferOffset as_daddiu(Register rd, Register rs, int32_t j);
BufferOffset as_subu(Register rd, Register rs, Register rt);
BufferOffset as_dsubu(Register rd, Register rs, Register rt);
BufferOffset as_mult(Register rs, Register rt);
BufferOffset as_multu(Register rs, Register rt);
BufferOffset as_dmult(Register rs, Register rt);
BufferOffset as_dmultu(Register rs, Register rt);
BufferOffset as_div(Register rs, Register rt);
BufferOffset as_divu(Register rs, Register rt);
BufferOffset as_mul(Register rd, Register rs, Register rt);
BufferOffset as_ddiv(Register rs, Register rt);
BufferOffset as_ddivu(Register rs, Register rt);
// Logical instructions
BufferOffset as_and(Register rd, Register rs, Register rt);
@ -833,13 +889,25 @@ class AssemblerMIPSShared : public AssemblerShared
// Shift instructions
// as_sll(zero, zero, x) instructions are reserved as nop
BufferOffset as_sll(Register rd, Register rt, uint16_t sa);
BufferOffset as_dsll(Register rd, Register rt, uint16_t sa);
BufferOffset as_dsll32(Register rd, Register rt, uint16_t sa);
BufferOffset as_sllv(Register rd, Register rt, Register rs);
BufferOffset as_dsllv(Register rd, Register rt, Register rs);
BufferOffset as_srl(Register rd, Register rt, uint16_t sa);
BufferOffset as_dsrl(Register rd, Register rt, uint16_t sa);
BufferOffset as_dsrl32(Register rd, Register rt, uint16_t sa);
BufferOffset as_srlv(Register rd, Register rt, Register rs);
BufferOffset as_dsrlv(Register rd, Register rt, Register rs);
BufferOffset as_sra(Register rd, Register rt, uint16_t sa);
BufferOffset as_dsra(Register rd, Register rt, uint16_t sa);
BufferOffset as_dsra32(Register rd, Register rt, uint16_t sa);
BufferOffset as_srav(Register rd, Register rt, Register rs);
BufferOffset as_rotr(Register rd, Register rt, uint16_t sa);
BufferOffset as_rotrv(Register rd, Register rt, Register rs);
BufferOffset as_dsrav(Register rd, Register rt, Register rs);
BufferOffset as_drotr(Register rd, Register rt, uint16_t sa);
BufferOffset as_drotr32(Register rd, Register rt, uint16_t sa);
BufferOffset as_drotrv(Register rd, Register rt, Register rs);
// Load and store instructions
BufferOffset as_lb(Register rd, Register rs, int16_t off);
@ -847,13 +915,22 @@ class AssemblerMIPSShared : public AssemblerShared
BufferOffset as_lh(Register rd, Register rs, int16_t off);
BufferOffset as_lhu(Register rd, Register rs, int16_t off);
BufferOffset as_lw(Register rd, Register rs, int16_t off);
BufferOffset as_lwu(Register rd, Register rs, int16_t off);
BufferOffset as_lwl(Register rd, Register rs, int16_t off);
BufferOffset as_lwr(Register rd, Register rs, int16_t off);
BufferOffset as_ll(Register rd, Register rs, int16_t off);
BufferOffset as_ld(Register rd, Register rs, int16_t off);
BufferOffset as_ldl(Register rd, Register rs, int16_t off);
BufferOffset as_ldr(Register rd, Register rs, int16_t off);
BufferOffset as_sb(Register rd, Register rs, int16_t off);
BufferOffset as_sh(Register rd, Register rs, int16_t off);
BufferOffset as_sw(Register rd, Register rs, int16_t off);
BufferOffset as_swl(Register rd, Register rs, int16_t off);
BufferOffset as_swr(Register rd, Register rs, int16_t off);
BufferOffset as_sc(Register rd, Register rs, int16_t off);
BufferOffset as_sd(Register rd, Register rs, int16_t off);
BufferOffset as_sdl(Register rd, Register rs, int16_t off);
BufferOffset as_sdr(Register rd, Register rs, int16_t off);
// Move from HI/LO register.
BufferOffset as_mfhi(Register rd);
@ -873,8 +950,19 @@ class AssemblerMIPSShared : public AssemblerShared
// Bit twiddling.
BufferOffset as_clz(Register rd, Register rs);
BufferOffset as_dclz(Register rd, Register rs);
BufferOffset as_ins(Register rt, Register rs, uint16_t pos, uint16_t size);
BufferOffset as_dins(Register rt, Register rs, uint16_t pos, uint16_t size);
BufferOffset as_dinsm(Register rt, Register rs, uint16_t pos, uint16_t size);
BufferOffset as_dinsu(Register rt, Register rs, uint16_t pos, uint16_t size);
BufferOffset as_ext(Register rt, Register rs, uint16_t pos, uint16_t size);
BufferOffset as_dext(Register rt, Register rs, uint16_t pos, uint16_t size);
BufferOffset as_dextm(Register rt, Register rs, uint16_t pos, uint16_t size);
BufferOffset as_dextu(Register rt, Register rs, uint16_t pos, uint16_t size);
// Sign extend
BufferOffset as_seb(Register rd, Register rt);
BufferOffset as_seh(Register rd, Register rt);
// FP instructions
@ -892,6 +980,10 @@ class AssemblerMIPSShared : public AssemblerShared
BufferOffset as_mtc1(Register rt, FloatRegister fs);
BufferOffset as_mfc1(Register rt, FloatRegister fs);
BufferOffset as_mthc1(Register rt, FloatRegister fs);
BufferOffset as_mfhc1(Register rt, FloatRegister fs);
BufferOffset as_dmtc1(Register rt, FloatRegister fs);
BufferOffset as_dmfc1(Register rt, FloatRegister fs);
public:
// FP convert instructions
@ -972,7 +1064,8 @@ class AssemblerMIPSShared : public AssemblerShared
public:
static bool SupportsFloatingPoint() {
#if (defined(__mips_hard_float) && !defined(__mips_single_float)) || defined(JS_SIMULATOR_MIPS32)
#if (defined(__mips_hard_float) && !defined(__mips_single_float)) || \
defined(JS_SIMULATOR_MIPS32) || defined(JS_SIMULATOR_MIPS64)
return true;
#else
return false;