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Bug 1278283
- Expose many simple operations in the MacroAssembler. r=nbp
--HG-- extra : rebase_source : 099c3f1cf33cb1f34929499bac241e741dc68f48
This commit is contained in:
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27fb1d56c1
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@ -443,7 +443,7 @@ class MacroAssembler : public MacroAssemblerSpecific
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void Pop(const Operand op) DEFINED_ON(x86_shared);
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void Pop(Register reg) PER_SHARED_ARCH;
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void Pop(FloatRegister t) DEFINED_ON(x86_shared);
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void Pop(FloatRegister t) DEFINED_ON(x86_shared, arm, arm64);
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void Pop(const ValueOperand& val) PER_SHARED_ARCH;
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void popRooted(VMFunction::RootType rootType, Register cellReg, const ValueOperand& valueReg);
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@ -691,6 +691,9 @@ class MacroAssembler : public MacroAssemblerSpecific
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inline void move64(Imm64 imm, Register64 dest) PER_ARCH;
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inline void move64(Register64 src, Register64 dest) PER_ARCH;
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inline void moveFloat32ToGPR(FloatRegister src, Register dest) DEFINED_ON(arm, arm64, x86_shared);
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inline void moveGPRToFloat32(Register src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
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// ===============================================================
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// Logical instructions
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@ -719,7 +722,7 @@ class MacroAssembler : public MacroAssemblerSpecific
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inline void or64(Register64 src, Register64 dest) PER_ARCH;
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inline void xor64(Register64 src, Register64 dest) PER_ARCH;
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inline void xor32(Register src, Register dest) DEFINED_ON(x86_shared);
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inline void xor32(Register src, Register dest) DEFINED_ON(x86_shared, arm, arm64);
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inline void xor32(Imm32 imm, Register dest) PER_SHARED_ARCH;
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inline void xorPtr(Register src, Register dest) PER_ARCH;
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@ -746,7 +749,7 @@ class MacroAssembler : public MacroAssemblerSpecific
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inline void add64(Register64 src, Register64 dest) PER_ARCH;
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inline void add64(Imm32 imm, Register64 dest) PER_ARCH;
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inline void addFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared);
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inline void addFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared, arm, arm64);
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inline void addDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
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inline void addConstantDouble(double d, FloatRegister dest) DEFINED_ON(x86);
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@ -761,18 +764,39 @@ class MacroAssembler : public MacroAssemblerSpecific
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inline void subPtr(ImmWord imm, Register dest) DEFINED_ON(x64);
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inline void subPtr(const Address& addr, Register dest) DEFINED_ON(mips_shared, arm, arm64, x86, x64);
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inline void subFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared, arm, arm64);
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inline void subDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
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// On x86-shared, srcDest must be eax and edx will be clobbered.
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inline void mul32(Register rhs, Register srcDest) DEFINED_ON(arm, arm64, x86_shared);
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inline void mul32(Register src1, Register src2, Register dest, Label* onOver, Label* onZero) DEFINED_ON(arm64);
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inline void mul64(Imm64 imm, const Register64& dest) PER_ARCH;
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inline void mulBy3(Register src, Register dest) PER_ARCH;
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inline void mulFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared, arm, arm64);
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inline void mulDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
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inline void mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest) DEFINED_ON(mips_shared, arm, arm64, x86, x64);
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// Perform an integer division, returning the integer part rounded toward zero.
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// rhs must not be zero, and the division must not overflow.
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//
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// On x86_shared, srcDest must be eax and edx will be clobbered.
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// On ARM, the chip must have hardware division instructions.
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inline void quotient32(Register rhs, Register srcDest, bool isUnsigned) DEFINED_ON(x86_shared, arm, arm64);
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// Perform an integer division, returning the remainder part.
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// rhs must not be zero, and the division must not overflow.
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//
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// On x86_shared, srcDest must be eax and edx will be clobbered.
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// On ARM, the chip must have hardware division instructions.
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inline void remainder32(Register rhs, Register srcDest, bool isUnsigned) DEFINED_ON(x86_shared, arm, arm64);
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inline void divFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared, arm, arm64);
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inline void divDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
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inline void inc32(RegisterOrInt32Constant* key);
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@ -782,13 +806,27 @@ class MacroAssembler : public MacroAssemblerSpecific
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inline void neg32(Register reg) PER_SHARED_ARCH;
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inline void negateFloat(FloatRegister reg) DEFINED_ON(arm64, x86_shared);
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inline void negateFloat(FloatRegister reg) DEFINED_ON(arm, arm64, x86_shared);
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inline void negateDouble(FloatRegister reg) PER_SHARED_ARCH;
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inline void absFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
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inline void absDouble(FloatRegister src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
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inline void sqrtFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
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inline void sqrtDouble(FloatRegister src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
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// ===============================================================
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// Shift functions
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// For shift-by-register there may be platform-specific
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// variations, for example, x86 will perform the shift mod 32 but
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// ARM will perform the shift mod 256.
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//
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// For shift-by-immediate the platform assembler may restrict the
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// immediate, for example, the ARM assembler requires the count
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// for 32-bit shifts to be in the range [0,31].
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inline void lshiftPtr(Imm32 imm, Register dest) PER_ARCH;
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inline void lshift64(Imm32 imm, Register64 dest) PER_ARCH;
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@ -801,9 +839,13 @@ class MacroAssembler : public MacroAssemblerSpecific
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inline void rshift64(Imm32 imm, Register64 dest) PER_ARCH;
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// On x86_shared these have the constraint that shift must be in CL.
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inline void lshift32(Register shift, Register srcDest) DEFINED_ON(x86_shared);
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inline void rshift32(Register shift, Register srcDest) DEFINED_ON(x86_shared);
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inline void rshift32Arithmetic(Register shift, Register srcDest) DEFINED_ON(x86_shared);
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inline void lshift32(Register shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
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inline void rshift32(Register shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
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inline void rshift32Arithmetic(Register shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
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inline void lshift32(Imm32 shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
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inline void rshift32(Imm32 shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
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inline void rshift32Arithmetic(Imm32 shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
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// ===============================================================
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// Rotation functions
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@ -816,8 +858,8 @@ class MacroAssembler : public MacroAssemblerSpecific
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// Bit counting functions
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// knownNotZero may be true only if the src is known not to be zero.
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inline void clz32(Register src, Register dest, bool knownNotZero) DEFINED_ON(x86_shared);
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inline void ctz32(Register src, Register dest, bool knownNotZero) DEFINED_ON(x86_shared);
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inline void clz32(Register src, Register dest, bool knownNotZero) DEFINED_ON(x86_shared, arm, arm64);
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inline void ctz32(Register src, Register dest, bool knownNotZero) DEFINED_ON(x86_shared, arm, arm64);
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inline void clz64(Register64 src, Register64 dest) DEFINED_ON(x64);
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inline void ctz64(Register64 src, Register64 dest) DEFINED_ON(x64);
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@ -1911,6 +1911,7 @@ Assembler::as_udiv(Register rd, Register rn, Register rm, Condition c)
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BufferOffset
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Assembler::as_clz(Register dest, Register src, Condition c)
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{
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MOZ_ASSERT(src != pc && dest != pc);
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return writeInst(RD(dest) | src.code() | c | 0x016f0f10);
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}
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@ -28,6 +28,18 @@ MacroAssembler::move64(Imm64 imm, Register64 dest)
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move32(Imm32((imm.value >> 32) & 0xFFFFFFFFL), dest.high);
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}
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void
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MacroAssembler::moveFloat32ToGPR(FloatRegister src, Register dest)
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{
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ma_vxfer(src, dest);
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}
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void
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MacroAssembler::moveGPRToFloat32(Register src, FloatRegister dest)
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{
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ma_vxfer(src, dest);
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}
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// ===============================================================
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// Logical instructions
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@ -146,6 +158,12 @@ MacroAssembler::xor64(Register64 src, Register64 dest)
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ma_eor(src.high, dest.high);
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}
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void
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MacroAssembler::xor32(Register src, Register dest)
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{
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ma_eor(src, dest, SetCC);
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}
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void
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MacroAssembler::xor32(Imm32 imm, Register dest)
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{
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@ -243,6 +261,12 @@ MacroAssembler::addDouble(FloatRegister src, FloatRegister dest)
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ma_vadd(dest, src, dest);
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}
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void
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MacroAssembler::addFloat32(FloatRegister src, FloatRegister dest)
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{
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ma_vadd_f32(dest, src, dest);
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}
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void
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MacroAssembler::sub32(Register src, Register dest)
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{
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@ -298,6 +322,18 @@ MacroAssembler::subDouble(FloatRegister src, FloatRegister dest)
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ma_vsub(dest, src, dest);
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}
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void
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MacroAssembler::subFloat32(FloatRegister src, FloatRegister dest)
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{
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ma_vsub_f32(dest, src, dest);
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}
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void
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MacroAssembler::mul32(Register rhs, Register srcDest)
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{
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as_mul(srcDest, srcDest, rhs);
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}
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void
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MacroAssembler::mul64(Imm64 imm, const Register64& dest)
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{
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@ -333,6 +369,12 @@ MacroAssembler::mulBy3(Register src, Register dest)
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as_add(dest, src, lsl(src, 1));
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}
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void
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MacroAssembler::mulFloat32(FloatRegister src, FloatRegister dest)
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{
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ma_vmul_f32(dest, src, dest);
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}
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void
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MacroAssembler::mulDouble(FloatRegister src, FloatRegister dest)
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{
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@ -347,6 +389,32 @@ MacroAssembler::mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest)
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mulDouble(ScratchDoubleReg, dest);
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}
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void
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MacroAssembler::quotient32(Register rhs, Register srcDest, bool isUnsigned)
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{
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MOZ_ASSERT(HasIDIV());
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if (isUnsigned)
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ma_udiv(srcDest, rhs, srcDest);
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else
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ma_sdiv(srcDest, rhs, srcDest);
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}
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void
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MacroAssembler::remainder32(Register rhs, Register srcDest, bool isUnsigned)
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{
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MOZ_ASSERT(HasIDIV());
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if (isUnsigned)
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ma_umod(srcDest, rhs, srcDest);
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else
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ma_smod(srcDest, rhs, srcDest);
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}
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void
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MacroAssembler::divFloat32(FloatRegister src, FloatRegister dest)
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{
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ma_vdiv_f32(dest, src, dest);
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}
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void
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MacroAssembler::divDouble(FloatRegister src, FloatRegister dest)
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{
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@ -382,6 +450,40 @@ MacroAssembler::negateDouble(FloatRegister reg)
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ma_vneg(reg, reg);
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}
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void
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MacroAssembler::negateFloat(FloatRegister reg)
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{
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ma_vneg_f32(reg, reg);
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}
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void
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MacroAssembler::absFloat32(FloatRegister src, FloatRegister dest)
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{
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if (src != dest)
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ma_vmov_f32(src, dest);
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ma_vabs_f32(dest, dest);
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}
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void
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MacroAssembler::absDouble(FloatRegister src, FloatRegister dest)
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{
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if (src != dest)
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ma_vmov(src, dest);
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ma_vabs(dest, dest);
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}
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void
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MacroAssembler::sqrtFloat32(FloatRegister src, FloatRegister dest)
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{
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ma_vsqrt_f32(src, dest);
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}
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void
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MacroAssembler::sqrtDouble(FloatRegister src, FloatRegister dest)
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{
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ma_vsqrt(src, dest);
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}
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// ===============================================================
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// Shift functions
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@ -399,18 +501,54 @@ MacroAssembler::lshift64(Imm32 imm, Register64 dest)
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as_mov(dest.low, lsl(dest.low, imm.value));
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}
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void
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MacroAssembler::lshift32(Register src, Register dest)
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{
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ma_lsl(src, dest, dest);
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}
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void
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MacroAssembler::lshift32(Imm32 imm, Register dest)
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{
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lshiftPtr(imm, dest);
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}
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void
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MacroAssembler::rshiftPtr(Imm32 imm, Register dest)
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{
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ma_lsr(imm, dest, dest);
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}
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void
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MacroAssembler::rshift32(Register src, Register dest)
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{
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ma_lsr(src, dest, dest);
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}
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void
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MacroAssembler::rshift32(Imm32 imm, Register dest)
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{
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rshiftPtr(imm, dest);
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}
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void
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MacroAssembler::rshiftPtrArithmetic(Imm32 imm, Register dest)
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{
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ma_asr(imm, dest, dest);
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}
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void
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MacroAssembler::rshift32Arithmetic(Register src, Register dest)
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{
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ma_asr(src, dest, dest);
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}
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void
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MacroAssembler::rshift32Arithmetic(Imm32 imm, Register dest)
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{
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rshiftPtrArithmetic(imm, dest);
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}
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void
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MacroAssembler::rshift64(Imm32 imm, Register64 dest)
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{
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@ -451,6 +589,21 @@ MacroAssembler::rotateRight(Register count, Register input, Register dest)
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ma_ror(count, input, dest);
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}
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// ===============================================================
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// Bit counting functions
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void
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MacroAssembler::clz32(Register src, Register dest, bool knownNotZero)
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{
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ma_clz(src, dest);
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}
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void
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MacroAssembler::ctz32(Register src, Register dest, bool knownNotZero)
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{
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ma_ctz(src, dest);
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}
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// ===============================================================
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// Branch functions
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@ -1009,6 +1009,19 @@ MacroAssemblerARM::ma_clz(Register src, Register dest, Condition cond)
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as_clz(dest, src, cond);
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}
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void
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MacroAssemblerARM::ma_ctz(Register src, Register dest)
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{
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// int c = __clz(a & -a);
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// return a ? 31 - c : c;
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ScratchRegisterScope scratch(asMasm());
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as_rsb(scratch, src, Imm8(0), SetCC);
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as_and(dest, src, O2Reg(scratch), LeaveCC);
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as_clz(dest, dest);
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as_rsb(dest, dest, Imm8(0x1F), LeaveCC, Assembler::NotEqual);
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}
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// Memory.
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// Shortcut for when we know we're transferring 32 bits of data.
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void
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@ -4670,6 +4683,13 @@ MacroAssembler::Pop(Register reg)
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adjustFrame(-sizeof(intptr_t));
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}
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void
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MacroAssembler::Pop(FloatRegister reg)
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{
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ma_vpop(reg);
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adjustFrame(-reg.size());
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}
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void
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MacroAssembler::Pop(const ValueOperand& val)
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{
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@ -277,6 +277,7 @@ class MacroAssemblerARM : public Assembler
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void ma_udiv(Register num, Register div, Register dest, Condition cond = Always);
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// Misc operations
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void ma_clz(Register src, Register dest, Condition cond = Always);
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void ma_ctz(Register src, Register dest);
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// Memory:
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// Shortcut for when we know we're transferring 32 bits of data.
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void ma_dtr(LoadStore ls, Register rn, Imm32 offset, Register rt,
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@ -26,6 +26,18 @@ MacroAssembler::move64(Imm64 imm, Register64 dest)
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movePtr(ImmWord(imm.value), dest.reg);
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}
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void
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MacroAssembler::moveFloat32ToGPR(FloatRegister src, Register dest)
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{
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MOZ_CRASH("NYI: moveFloat32ToGPR");
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}
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void
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MacroAssembler::moveGPRToFloat32(Register src, FloatRegister dest)
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{
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MOZ_CRASH("NYI: moveGPRToFloat32");
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}
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// ===============================================================
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// Logical instructions
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@ -160,6 +172,12 @@ MacroAssembler::xor64(Register64 src, Register64 dest)
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xorPtr(src.reg, dest.reg);
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}
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void
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MacroAssembler::xor32(Register src, Register dest)
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{
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Eor(ARMRegister(dest, 32), ARMRegister(dest, 32), Operand(ARMRegister(src, 32)));
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}
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void
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MacroAssembler::xor32(Imm32 imm, Register dest)
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{
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@ -276,6 +294,12 @@ MacroAssembler::addDouble(FloatRegister src, FloatRegister dest)
|
||||
fadd(ARMFPRegister(dest, 64), ARMFPRegister(dest, 64), ARMFPRegister(src, 64));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::addFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
fadd(ARMFPRegister(dest, 32), ARMFPRegister(dest, 32), ARMFPRegister(src, 32));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::sub32(Imm32 imm, Register dest)
|
||||
{
|
||||
@ -339,6 +363,18 @@ MacroAssembler::subDouble(FloatRegister src, FloatRegister dest)
|
||||
fsub(ARMFPRegister(dest, 64), ARMFPRegister(dest, 64), ARMFPRegister(src, 64));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::subFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
fsub(ARMFPRegister(dest, 32), ARMFPRegister(dest, 32), ARMFPRegister(src, 32));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::mul32(Register rhs, Register srcDest)
|
||||
{
|
||||
MOZ_CRASH("NYI - mul32");
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::mul32(Register src1, Register src2, Register dest, Label* onOver, Label* onZero)
|
||||
{
|
||||
@ -372,6 +408,12 @@ MacroAssembler::mulBy3(Register src, Register dest)
|
||||
Add(xdest, xsrc, Operand(xsrc, vixl::LSL, 1));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::mulFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
fmul(ARMFPRegister(dest, 32), ARMFPRegister(dest, 32), ARMFPRegister(src, 32));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::mulDouble(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
@ -390,6 +432,24 @@ MacroAssembler::mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest)
|
||||
fmul(ARMFPRegister(dest, 64), ARMFPRegister(dest, 64), scratchDouble);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::quotient32(Register rhs, Register srcDest, bool isUnsigned)
|
||||
{
|
||||
MOZ_CRASH("NYI - quotient32");
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::remainder32(Register rhs, Register srcDest, bool isUnsigned)
|
||||
{
|
||||
MOZ_CRASH("NYI - remainder32");
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::divFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
fdiv(ARMFPRegister(dest, 32), ARMFPRegister(dest, 32), ARMFPRegister(src, 32));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::divDouble(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
@ -427,6 +487,30 @@ MacroAssembler::negateDouble(FloatRegister reg)
|
||||
fneg(ARMFPRegister(reg, 64), ARMFPRegister(reg, 64));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::absFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
MOZ_CRASH("NYI - absFloat32");
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::absDouble(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
MOZ_CRASH("NYI - absDouble");
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::sqrtFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
MOZ_CRASH("NYI - sqrtFloat32");
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::sqrtDouble(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
MOZ_CRASH("NYI - sqrtDouble");
|
||||
}
|
||||
|
||||
// ===============================================================
|
||||
// Shift functions
|
||||
|
||||
@ -442,6 +526,18 @@ MacroAssembler::lshift64(Imm32 imm, Register64 dest)
|
||||
lshiftPtr(imm, dest.reg);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::lshift32(Register shift, Register dest)
|
||||
{
|
||||
Lsl(ARMRegister(dest, 32), ARMRegister(dest, 32), ARMRegister(shift, 32));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::lshift32(Imm32 imm, Register dest)
|
||||
{
|
||||
Lsl(ARMRegister(dest, 32), ARMRegister(dest, 32), imm.value);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshiftPtr(Imm32 imm, Register dest)
|
||||
{
|
||||
@ -454,12 +550,36 @@ MacroAssembler::rshiftPtr(Imm32 imm, Register src, Register dest)
|
||||
Lsr(ARMRegister(dest, 64), ARMRegister(src, 64), imm.value);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshift32(Register shift, Register dest)
|
||||
{
|
||||
Lsr(ARMRegister(dest, 32), ARMRegister(dest, 32), ARMRegister(shift, 32));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshift32(Imm32 imm, Register dest)
|
||||
{
|
||||
Lsr(ARMRegister(dest, 32), ARMRegister(dest, 32), imm.value);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshiftPtrArithmetic(Imm32 imm, Register dest)
|
||||
{
|
||||
Asr(ARMRegister(dest, 64), ARMRegister(dest, 64), imm.value);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshift32Arithmetic(Register shift, Register dest)
|
||||
{
|
||||
Asr(ARMRegister(dest, 32), ARMRegister(dest, 32), ARMRegister(shift, 32));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshift32Arithmetic(Imm32 imm, Register dest)
|
||||
{
|
||||
Asr(ARMRegister(dest, 32), ARMRegister(dest, 32), imm.value);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshift64(Imm32 imm, Register64 dest)
|
||||
{
|
||||
@ -471,22 +591,37 @@ MacroAssembler::rshift64(Imm32 imm, Register64 dest)
|
||||
void
|
||||
MacroAssembler::rotateLeft(Imm32 count, Register input, Register dest)
|
||||
{
|
||||
MOZ_CRASH("NYI");
|
||||
MOZ_CRASH("NYI: rotateLeft by immediate");
|
||||
}
|
||||
void
|
||||
MacroAssembler::rotateLeft(Register count, Register input, Register dest)
|
||||
{
|
||||
MOZ_CRASH("NYI");
|
||||
MOZ_CRASH("NYI: rotateLeft by register");
|
||||
}
|
||||
void
|
||||
MacroAssembler::rotateRight(Imm32 count, Register input, Register dest)
|
||||
{
|
||||
MOZ_CRASH("NYI");
|
||||
MOZ_CRASH("NYI: rotateRight by immediate");
|
||||
}
|
||||
void
|
||||
MacroAssembler::rotateRight(Register count, Register input, Register dest)
|
||||
{
|
||||
MOZ_CRASH("NYI");
|
||||
MOZ_CRASH("NYI: rotateRight by register");
|
||||
}
|
||||
|
||||
// ===============================================================
|
||||
// Bit counting functions
|
||||
|
||||
void
|
||||
MacroAssembler::clz32(Register src, Register dest, bool knownNotZero)
|
||||
{
|
||||
MOZ_CRASH("NYI: clz32");
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::ctz32(Register src, Register dest, bool knownNotZero)
|
||||
{
|
||||
MOZ_CRASH("NYI: ctz32");
|
||||
}
|
||||
|
||||
// ===============================================================
|
||||
|
@ -457,6 +457,12 @@ MacroAssembler::Pop(Register reg)
|
||||
adjustFrame(-1 * int64_t(sizeof(int64_t)));
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::Pop(FloatRegister f)
|
||||
{
|
||||
MOZ_CRASH("NYI: Pop(FloatRegister)");
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::Pop(const ValueOperand& val)
|
||||
{
|
||||
|
@ -1512,7 +1512,7 @@ class MacroAssemblerCompat : public vixl::MacroAssembler
|
||||
Mov(ScratchReg64, immediate);
|
||||
Eor(ScratchReg64, ScratchReg2_64, ScratchReg64);
|
||||
}
|
||||
Tst(ScratchReg64, Operand(-1ll << JSVAL_TAG_SHIFT));
|
||||
Tst(ScratchReg64, Operand((unsigned long long)(-1ll) << JSVAL_TAG_SHIFT));
|
||||
return cond;
|
||||
}
|
||||
|
||||
|
@ -13,6 +13,21 @@ namespace js {
|
||||
namespace jit {
|
||||
|
||||
//{{{ check_macroassembler_style
|
||||
// ===============================================================
|
||||
// Move instructions
|
||||
|
||||
void
|
||||
MacroAssembler::moveFloat32ToGPR(FloatRegister src, Register dest)
|
||||
{
|
||||
vmovd(src, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::moveGPRToFloat32(Register src, FloatRegister dest)
|
||||
{
|
||||
vmovd(src, dest);
|
||||
}
|
||||
|
||||
// ===============================================================
|
||||
// Logical instructions
|
||||
|
||||
@ -199,12 +214,68 @@ MacroAssembler::subDouble(FloatRegister src, FloatRegister dest)
|
||||
vsubsd(src, dest, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::subFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
vsubss(src, dest, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::mul32(Register rhs, Register srcDest)
|
||||
{
|
||||
MOZ_ASSERT(srcDest == eax);
|
||||
imull(rhs, srcDest); // Clobbers edx
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::mulFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
vmulss(src, dest, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::mulDouble(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
vmulsd(src, dest, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::quotient32(Register rhs, Register srcDest, bool isUnsigned)
|
||||
{
|
||||
MOZ_ASSERT(srcDest == eax);
|
||||
|
||||
// Sign extend eax into edx to make (edx:eax): idiv/udiv are 64-bit.
|
||||
if (isUnsigned) {
|
||||
mov(ImmWord(0), edx);
|
||||
udiv(rhs);
|
||||
} else {
|
||||
cdq();
|
||||
idiv(rhs);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::remainder32(Register rhs, Register srcDest, bool isUnsigned)
|
||||
{
|
||||
MOZ_ASSERT(srcDest == eax);
|
||||
|
||||
// Sign extend eax into edx to make (edx:eax): idiv/udiv are 64-bit.
|
||||
if (isUnsigned) {
|
||||
mov(ImmWord(0), edx);
|
||||
udiv(rhs);
|
||||
} else {
|
||||
cdq();
|
||||
idiv(rhs);
|
||||
}
|
||||
mov(edx, eax);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::divFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
vdivss(src, dest, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::divDouble(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
@ -240,6 +311,34 @@ MacroAssembler::negateDouble(FloatRegister reg)
|
||||
vxorpd(scratch, reg, reg); // s ^ 0x80000000000000
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::absFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
ScratchFloat32Scope scratch(*this);
|
||||
loadConstantFloat32(mozilla::SpecificNaN<float>(0, mozilla::FloatingPoint<float>::kSignificandBits), scratch);
|
||||
vandps(scratch, src, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::absDouble(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
ScratchDoubleScope scratch(*this);
|
||||
loadConstantDouble(mozilla::SpecificNaN<double>(0, mozilla::FloatingPoint<double>::kSignificandBits), scratch);
|
||||
vandpd(scratch, src, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::sqrtFloat32(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
vsqrtss(src, src, dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::sqrtDouble(FloatRegister src, FloatRegister dest)
|
||||
{
|
||||
vsqrtsd(src, src, dest);
|
||||
}
|
||||
|
||||
// ===============================================================
|
||||
// Rotation instructions
|
||||
void
|
||||
@ -298,6 +397,24 @@ MacroAssembler::rshift32Arithmetic(Register shift, Register srcDest)
|
||||
sarl_cl(srcDest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::lshift32(Imm32 shift, Register srcDest)
|
||||
{
|
||||
shll(shift, srcDest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshift32(Imm32 shift, Register srcDest)
|
||||
{
|
||||
shrl(shift, srcDest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssembler::rshift32Arithmetic(Imm32 shift, Register srcDest)
|
||||
{
|
||||
sarl(shift, srcDest);
|
||||
}
|
||||
|
||||
// ===============================================================
|
||||
// Branch instructions
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user