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Bug 1403635 - MIPS: Add MIPS R1 support. r=bbouvier
Many tests fail on MIPS R1 boards because R2 instructions are emitted. This patch adds architecture detection for R2, along existing one for Loongson. Instruction sequences that are emitted for R1 instead of R2 instructions are added to macro assembler.
This commit is contained in:
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@ -13,6 +13,7 @@
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#define HWCAP_MIPS (1 << 28)
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#define HWCAP_LOONGSON (1 << 27)
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#define HWCAP_R2 (1 << 26)
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#define HWCAP_FPU (1 << 0)
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namespace js {
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@ -25,6 +26,7 @@ get_mips_flags()
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#if defined(JS_SIMULATOR_MIPS32) || defined(JS_SIMULATOR_MIPS64)
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flags |= HWCAP_FPU;
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flags |= HWCAP_R2;
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#else
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# ifdef __linux__
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FILE* fp = fopen("/proc/cpuinfo", "r");
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@ -39,6 +41,8 @@ get_mips_flags()
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flags |= HWCAP_FPU;
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if (strstr(buf, "Loongson"))
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flags |= HWCAP_LOONGSON;
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if (strstr(buf, "mips32r2") || strstr(buf, "mips64r2"))
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flags |= HWCAP_R2;
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# endif
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#endif // JS_SIMULATOR_MIPS32 || JS_SIMULATOR_MIPS64
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return flags;
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@ -54,11 +58,17 @@ static bool check_loongson()
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return mips_private::Flags & HWCAP_LOONGSON;
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}
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static bool check_r2()
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{
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return mips_private::Flags & HWCAP_R2;
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}
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namespace mips_private {
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// Cache a local copy so we only have to read /proc/cpuinfo once.
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uint32_t Flags = get_mips_flags();
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bool hasFPU = check_fpu();;
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bool isLoongson = check_loongson();
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bool hasR2 = check_r2();
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}
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Registers::Code
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@ -314,11 +314,13 @@ namespace mips_private {
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extern uint32_t Flags;
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extern bool hasFPU;
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extern bool isLoongson;
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extern bool hasR2;
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}
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inline uint32_t GetMIPSFlags() { return mips_private::Flags; }
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inline bool hasFPU() { return mips_private::hasFPU; }
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inline bool isLoongson() { return mips_private::isLoongson; }
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inline bool hasR2() { return mips_private::hasR2; }
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// MIPS doesn't have double registers that can NOT be treated as float32.
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inline bool
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@ -714,6 +714,7 @@ AssemblerMIPSShared::as_rotr(Register rd, Register rt, uint16_t sa)
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{
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MOZ_ASSERT(sa < 32);
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spew("rotr %3s,%3s, 0x%x", rd.name(), rt.name(), sa);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special, rs_one, rt, rd, sa, ff_srl).encode());
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}
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@ -722,6 +723,7 @@ AssemblerMIPSShared::as_drotr(Register rd, Register rt, uint16_t sa)
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{
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MOZ_ASSERT(sa < 32);
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spew("drotr %3s,%3s, 0x%x", rd.name(), rt.name(), sa);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special, rs_one, rt, rd, sa, ff_dsrl).encode());
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}
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@ -730,6 +732,7 @@ AssemblerMIPSShared::as_drotr32(Register rd, Register rt, uint16_t sa)
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{
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MOZ_ASSERT(31 < sa && sa < 64);
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spew("drotr32%3s,%3s, 0x%x", rd.name(), rt.name(), sa - 32);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special, rs_one, rt, rd, sa - 32, ff_dsrl32).encode());
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}
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@ -737,6 +740,7 @@ BufferOffset
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AssemblerMIPSShared::as_rotrv(Register rd, Register rt, Register rs)
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{
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spew("rotrv %3s,%3s,%3s", rd.name(), rt.name(), rs.name());
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special, rs, rt, rd, 1, ff_srlv).encode());
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}
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@ -744,6 +748,7 @@ BufferOffset
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AssemblerMIPSShared::as_drotrv(Register rd, Register rt, Register rs)
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{
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spew("drotrv %3s,%3s,%3s", rd.name(), rt.name(), rs.name());
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special, rs, rt, rd, 1, ff_dsrlv).encode());
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}
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@ -1076,6 +1081,7 @@ AssemblerMIPSShared::as_ins(Register rt, Register rs, uint16_t pos, uint16_t siz
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Register rd;
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rd = Register::FromCode(pos + size - 1);
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spew("ins %3s,%3s, %d, %d", rt.name(), rs.name(), pos, size);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_ins).encode());
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}
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@ -1086,6 +1092,7 @@ AssemblerMIPSShared::as_dins(Register rt, Register rs, uint16_t pos, uint16_t si
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Register rd;
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rd = Register::FromCode(pos + size - 1);
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spew("dins %3s,%3s, %d, %d", rt.name(), rs.name(), pos, size);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_dins).encode());
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}
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@ -1096,6 +1103,7 @@ AssemblerMIPSShared::as_dinsm(Register rt, Register rs, uint16_t pos, uint16_t s
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Register rd;
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rd = Register::FromCode(pos + size - 1 - 32);
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spew("dinsm %3s,%3s, %d, %d", rt.name(), rs.name(), pos, size);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_dinsm).encode());
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}
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@ -1106,6 +1114,7 @@ AssemblerMIPSShared::as_dinsu(Register rt, Register rs, uint16_t pos, uint16_t s
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Register rd;
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rd = Register::FromCode(pos + size - 1 - 32);
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spew("dinsu %3s,%3s, %d, %d", rt.name(), rs.name(), pos, size);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, rs, rt, rd, pos - 32, ff_dinsu).encode());
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}
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@ -1116,6 +1125,7 @@ AssemblerMIPSShared::as_ext(Register rt, Register rs, uint16_t pos, uint16_t siz
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Register rd;
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rd = Register::FromCode(size - 1);
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spew("ext %3s,%3s, %d, %d", rt.name(), rs.name(), pos, size);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_ext).encode());
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}
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@ -1124,6 +1134,7 @@ BufferOffset
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AssemblerMIPSShared::as_seb(Register rd, Register rt)
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{
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spew("seb %3s,%3s", rd.name(), rt.name());
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, zero, rt, rd, 16, ff_bshfl).encode());
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}
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@ -1131,6 +1142,7 @@ BufferOffset
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AssemblerMIPSShared::as_seh(Register rd, Register rt)
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{
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spew("seh %3s,%3s", rd.name(), rt.name());
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, zero, rt, rd, 24, ff_bshfl).encode());
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}
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@ -1141,6 +1153,7 @@ AssemblerMIPSShared::as_dext(Register rt, Register rs, uint16_t pos, uint16_t si
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Register rd;
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rd = Register::FromCode(size - 1);
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spew("dext %3s,%3s, %d, %d", rt.name(), rs.name(), pos, size);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_dext).encode());
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}
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@ -1151,6 +1164,7 @@ AssemblerMIPSShared::as_dextm(Register rt, Register rs, uint16_t pos, uint16_t s
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Register rd;
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rd = Register::FromCode(size - 1 - 32);
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spew("dextm %3s,%3s, %d, %d", rt.name(), rs.name(), pos, size);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_dextm).encode());
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}
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@ -1161,6 +1175,7 @@ AssemblerMIPSShared::as_dextu(Register rt, Register rs, uint16_t pos, uint16_t s
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Register rd;
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rd = Register::FromCode(size - 1);
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spew("dextu %3s,%3s, %d, %d", rt.name(), rs.name(), pos, size);
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_special3, rs, rt, rd, pos - 32, ff_dextu).encode());
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}
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@ -1412,6 +1427,7 @@ BufferOffset
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AssemblerMIPSShared::as_truncls(FloatRegister fd, FloatRegister fs)
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{
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spew("trunc.l.s%3s,%3s", fd.name(), fs.name());
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_cop1, rs_s, zero, fs, fd, ff_trunc_l_fmt).encode());
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}
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@ -1447,6 +1463,7 @@ BufferOffset
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AssemblerMIPSShared::as_truncld(FloatRegister fd, FloatRegister fs)
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{
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spew("trunc.l.d%3s,%3s", fd.name(), fs.name());
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_cop1, rs_d, zero, fs, fd, ff_trunc_l_fmt).encode());
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}
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@ -1454,6 +1471,7 @@ BufferOffset
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AssemblerMIPSShared::as_cvtdl(FloatRegister fd, FloatRegister fs)
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{
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spew("cvt.d.l%3s,%3s", fd.name(), fs.name());
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_cop1, rs_l, zero, fs, fd, ff_cvt_d_fmt).encode());
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}
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@ -1482,6 +1500,7 @@ BufferOffset
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AssemblerMIPSShared::as_cvtsl(FloatRegister fd, FloatRegister fs)
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{
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spew("cvt.s.l%3s,%3s", fd.name(), fs.name());
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MOZ_ASSERT(hasR2());
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return writeInst(InstReg(op_cop1, rs_l, zero, fs, fd, ff_cvt_s_fmt).encode());
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}
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@ -1580,7 +1580,7 @@ CodeGeneratorMIPSShared::visitCopySignF(LCopySignF* ins)
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masm.moveFromFloat32(rhs, rhsi);
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// Combine.
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masm.as_ins(rhsi, lhsi, 0, 31);
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masm.ma_ins(rhsi, lhsi, 0, 31);
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masm.moveToFloat32(rhsi, output);
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}
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@ -1600,7 +1600,7 @@ CodeGeneratorMIPSShared::visitCopySignD(LCopySignD* ins)
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masm.moveFromDoubleHi(rhs, rhsi);
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// Combine.
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masm.as_ins(rhsi, lhsi, 0, 31);
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masm.ma_ins(rhsi, lhsi, 0, 31);
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masm.moveToDoubleHi(rhsi, output);
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}
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@ -29,13 +29,13 @@ MacroAssembler::moveGPRToFloat32(Register src, FloatRegister dest)
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void
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MacroAssembler::move8SignExtend(Register src, Register dest)
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{
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as_seb(dest, src);
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ma_seb(dest, src);
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}
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void
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MacroAssembler::move16SignExtend(Register src, Register dest)
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{
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as_seh(dest, src);
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ma_seh(dest, src);
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}
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// ===============================================================
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@ -71,13 +71,27 @@ MacroAssemblerMIPSShared::ma_sra(Register rd, Register rt, Imm32 shift)
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void
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MacroAssemblerMIPSShared::ma_ror(Register rd, Register rt, Imm32 shift)
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{
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if (hasR2()) {
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as_rotr(rd, rt, shift.value % 32);
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} else {
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ScratchRegisterScope scratch(asMasm());
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as_srl(scratch, rt, shift.value % 32);
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as_sll(rd, rt, (32 - (shift.value % 32)) % 32);
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as_or(rd, rd, scratch);
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}
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}
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void
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MacroAssemblerMIPSShared::ma_rol(Register rd, Register rt, Imm32 shift)
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{
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as_rotr(rd, rt, 32 - (shift.value % 32));
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if (hasR2()) {
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as_rotr(rd, rt, (32 - (shift.value % 32)) % 32);
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} else {
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ScratchRegisterScope scratch(asMasm());
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as_srl(scratch, rt, (32 - (shift.value % 32)) % 32);
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as_sll(rd, rt, shift.value % 32);
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as_or(rd, rd, scratch);
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}
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}
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void
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@ -101,14 +115,29 @@ MacroAssemblerMIPSShared::ma_sra(Register rd, Register rt, Register shift)
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void
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MacroAssemblerMIPSShared::ma_ror(Register rd, Register rt, Register shift)
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{
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if (hasR2()) {
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as_rotrv(rd, rt, shift);
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} else {
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ScratchRegisterScope scratch(asMasm());
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ma_negu(scratch, shift);
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as_sllv(scratch, rt, scratch);
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as_srlv(rd, rt, shift);
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as_or(rd, rd, scratch);
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}
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}
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void
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MacroAssemblerMIPSShared::ma_rol(Register rd, Register rt, Register shift)
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{
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ma_negu(ScratchRegister, shift);
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as_rotrv(rd, rt, ScratchRegister);
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ScratchRegisterScope scratch(asMasm());
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ma_negu(scratch, shift);
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if (hasR2()) {
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as_rotrv(rd, rt, scratch);
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} else {
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as_srlv(rd, rt, scratch);
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as_sllv(scratch, rt, shift);
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as_or(rd, rd, scratch);
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}
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}
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void
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@ -123,6 +152,69 @@ MacroAssemblerMIPSShared::ma_not(Register rd, Register rs)
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as_nor(rd, rs, zero);
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}
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// Bit extract/insert
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void
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MacroAssemblerMIPSShared::ma_ext(Register rt, Register rs, uint16_t pos, uint16_t size) {
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MOZ_ASSERT(pos < 32);
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MOZ_ASSERT(pos + size < 33);
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if (hasR2()) {
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as_ext(rt, rs, pos, size);
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} else {
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int shift_left = 32 - (pos + size);
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as_sll(rt, rs, shift_left);
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int shift_right = 32 - size;
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if (shift_right > 0) {
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as_srl(rt, rt, shift_right);
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}
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}
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}
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void
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MacroAssemblerMIPSShared::ma_ins(Register rt, Register rs, uint16_t pos, uint16_t size) {
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MOZ_ASSERT(pos < 32);
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MOZ_ASSERT(pos + size <= 32);
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MOZ_ASSERT(size != 0);
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if (hasR2()) {
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as_ins(rt, rs, pos, size);
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} else {
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ScratchRegisterScope scratch(asMasm());
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SecondScratchRegisterScope scratch2(asMasm());
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ma_subu(scratch, zero, Imm32(1));
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as_srl(scratch, scratch, 32 - size);
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as_and(scratch2, rs, scratch);
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as_sll(scratch2, scratch2, pos);
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as_sll(scratch, scratch, pos);
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as_nor(scratch, scratch, zero);
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as_and(scratch, rt, scratch);
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as_or(rt, scratch2, scratch);
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}
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}
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// Sign extend
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void
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MacroAssemblerMIPSShared::ma_seb(Register rd, Register rt)
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{
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if (hasR2()) {
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as_seb(rd, rt);
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} else {
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as_sll(rd, rt, 24);
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as_sra(rd, rd, 24);
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}
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}
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void
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MacroAssemblerMIPSShared::ma_seh(Register rd, Register rt)
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{
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if (hasR2()) {
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as_seh(rd, rt);
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} else {
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as_sll(rd, rt, 16);
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as_sra(rd, rd, 16);
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}
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}
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// And.
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void
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MacroAssemblerMIPSShared::ma_and(Register rd, Register rs)
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@ -484,7 +576,7 @@ MacroAssemblerMIPSShared::ma_load_unaligned(Register dest, const BaseIndex& src,
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as_lbu(temp, base, hiOffset);
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else
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as_lb(temp, base, hiOffset);
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as_ins(dest, temp, 8, 24);
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ma_ins(dest, temp, 8, 24);
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break;
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case SizeWord:
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as_lwl(dest, base, hiOffset);
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@ -627,7 +719,7 @@ MacroAssemblerMIPSShared::ma_store_unaligned(Register data, const BaseIndex& des
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switch (size) {
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case SizeHalfWord:
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as_sb(data, base, lowOffset);
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as_ext(temp, data, 8, 8);
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ma_ext(temp, data, 8, 8);
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as_sb(temp, base, hiOffset);
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break;
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case SizeWord:
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@ -1243,10 +1335,10 @@ MacroAssemblerMIPSShared::atomicFetchOpMIPSr2(int nbytes, bool signExtend, Atomi
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if (signExtend) {
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switch (nbytes) {
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case 1:
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as_seb(output, output);
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ma_seb(output, output);
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break;
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case 2:
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as_seh(output, output);
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ma_seh(output, output);
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break;
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case 4:
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break;
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@ -1418,10 +1510,10 @@ MacroAssemblerMIPSShared::compareExchangeMIPSr2(int nbytes, bool signExtend, con
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if (signExtend) {
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switch (nbytes) {
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case 1:
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as_seb(output, output);
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ma_seb(output, output);
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break;
|
||||
case 2:
|
||||
as_seh(output, output);
|
||||
ma_seh(output, output);
|
||||
break;
|
||||
case 4:
|
||||
break;
|
||||
@ -1769,7 +1861,7 @@ MacroAssembler::wasmTruncateDoubleToInt32(FloatRegister input, Register output,
|
||||
as_truncwd(ScratchFloat32Reg, input);
|
||||
as_cfc1(ScratchRegister, Assembler::FCSR);
|
||||
moveFromFloat32(ScratchFloat32Reg, output);
|
||||
as_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
ma_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
ma_b(ScratchRegister, Imm32(0), oolEntry, Assembler::NotEqual);
|
||||
}
|
||||
|
||||
@ -1780,7 +1872,7 @@ MacroAssembler::wasmTruncateFloat32ToInt32(FloatRegister input, Register output,
|
||||
as_truncws(ScratchFloat32Reg, input);
|
||||
as_cfc1(ScratchRegister, Assembler::FCSR);
|
||||
moveFromFloat32(ScratchFloat32Reg, output);
|
||||
as_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
ma_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
ma_b(ScratchRegister, Imm32(0), oolEntry, Assembler::NotEqual);
|
||||
}
|
||||
|
||||
|
@ -85,6 +85,14 @@ class MacroAssemblerMIPSShared : public Assembler
|
||||
|
||||
void ma_not(Register rd, Register rs);
|
||||
|
||||
// Bit extract/insert
|
||||
void ma_ext(Register rt, Register rs, uint16_t pos, uint16_t size);
|
||||
void ma_ins(Register rt, Register rs, uint16_t pos, uint16_t size);
|
||||
|
||||
// Sign extend
|
||||
void ma_seb(Register rd, Register rt);
|
||||
void ma_seh(Register rd, Register rt);
|
||||
|
||||
// and
|
||||
void ma_and(Register rd, Register rs);
|
||||
void ma_and(Register rd, Imm32 imm);
|
||||
|
@ -683,7 +683,7 @@ CodeGeneratorMIPS64::visitWasmTruncateToInt64(LWasmTruncateToInt64* lir)
|
||||
masm.moveFromDouble(ScratchDoubleReg, output);
|
||||
masm.as_cfc1(ScratchRegister, Assembler::FCSR);
|
||||
// extract invalid operation flag (bit 6) from FCSR
|
||||
masm.as_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
masm.ma_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
masm.ma_dsrl(SecondScratchReg, output, Imm32(63));
|
||||
masm.ma_or(SecondScratchReg, ScratchRegister);
|
||||
masm.ma_b(SecondScratchReg, Imm32(0), ool->entry(), Assembler::NotEqual);
|
||||
@ -703,7 +703,7 @@ CodeGeneratorMIPS64::visitWasmTruncateToInt64(LWasmTruncateToInt64* lir)
|
||||
// Check that the result is in the uint64_t range.
|
||||
masm.moveFromDouble(ScratchDoubleReg, output);
|
||||
masm.as_cfc1(ScratchRegister, Assembler::FCSR);
|
||||
masm.as_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
masm.ma_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
masm.ma_dsrl(SecondScratchReg, output, Imm32(63));
|
||||
masm.ma_or(SecondScratchReg, ScratchRegister);
|
||||
masm.ma_b(SecondScratchReg, Imm32(0), ool->entry(), Assembler::NotEqual);
|
||||
@ -724,7 +724,7 @@ CodeGeneratorMIPS64::visitWasmTruncateToInt64(LWasmTruncateToInt64* lir)
|
||||
|
||||
// Check that the result is in the int64_t range.
|
||||
masm.as_cfc1(output, Assembler::FCSR);
|
||||
masm.as_ext(output, output, 6, 1);
|
||||
masm.ma_ext(output, output, 6, 1);
|
||||
masm.ma_b(output, Imm32(0), ool->entry(), Assembler::NotEqual);
|
||||
|
||||
masm.bind(ool->rejoin());
|
||||
|
@ -2578,7 +2578,7 @@ MacroAssembler::wasmTruncateDoubleToUInt32(FloatRegister input, Register output,
|
||||
as_truncld(ScratchDoubleReg, input);
|
||||
moveFromDoubleHi(ScratchDoubleReg, output);
|
||||
as_cfc1(ScratchRegister, Assembler::FCSR);
|
||||
as_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
ma_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
ma_or(ScratchRegister, output);
|
||||
moveFromFloat32(ScratchDoubleReg, output);
|
||||
ma_b(ScratchRegister, Imm32(0), oolEntry, Assembler::NotEqual);
|
||||
@ -2592,7 +2592,7 @@ MacroAssembler::wasmTruncateFloat32ToUInt32(FloatRegister input, Register output
|
||||
as_truncls(ScratchDoubleReg, input);
|
||||
moveFromDoubleHi(ScratchDoubleReg, output);
|
||||
as_cfc1(ScratchRegister, Assembler::FCSR);
|
||||
as_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
ma_ext(ScratchRegister, ScratchRegister, 6, 1);
|
||||
ma_or(ScratchRegister, output);
|
||||
moveFromFloat32(ScratchDoubleReg, output);
|
||||
ma_b(ScratchRegister, Imm32(0), oolEntry, Assembler::NotEqual);
|
||||
|
Loading…
Reference in New Issue
Block a user