No more passing a 2nd return value back through a mutable 1-element array.
MozReview-Commit-ID: IUcyrq93KXT
--HG--
extra : rebase_source : 2f822b79ae81af55c0bdd372a8cf8e087bba2b7a
extra : source : c6615c7b00838e1d212c6007b4a54b20d71f7ae0
Previously, this mostly "worked" purely by chance -- it started gathering method definitions at the 'csu' variable, which JS helpfully hoisted up to the toplevel. It had the last value assigned to csu within the loop, which would have been the basest base class (don't think too hard about the case of multiple inheritance, it was wrong). Then we find all descendants, which was *too* much, but it ended up just making the analysis conservative.
MozReview-Commit-ID: 2Ps8gJpztw2
--HG--
extra : rebase_source : c12e58594e7d21dc035b2e669c53808629d5beae
extra : source : 196ac1f813f9a9489d24ba0c70c1dfb20b404489
Also create accessors on gc::Zone for a nicer API to ZoneCellIters.
MozReview-Commit-ID: AxRTTUfWrND
--HG--
extra : rebase_source : cf32560db5a123bdc64178a7567ed36e1ecb5b2b
No more passing a 2nd return value back through a mutable 1-element array.
MozReview-Commit-ID: IUcyrq93KXT
--HG--
extra : rebase_source : 8485a1816bd888aada033e10dff062ec32d4d4f1
Previously, this mostly "worked" purely by chance -- it started gathering method definitions at the 'csu' variable, which JS helpfully hoisted up to the toplevel. It had the last value assigned to csu within the loop, which would have been the basest base class (don't think too hard about the case of multiple inheritance, it was wrong). Then we find all descendants, which was *too* much, but it ended up just making the analysis conservative.
MozReview-Commit-ID: 2Ps8gJpztw2
--HG--
extra : rebase_source : b52ccf514e70fd00e5e73cdef59df379efb32487
Some MIR instructions have an AddLegalized() static function which much be used
when creating new instructions. This ensures that the proper expansions are
generated.
Make the New() factory method in those instructions private so it isn't used
inadvertently.
De-templatize the inlineSimdBinary<> function since it was only used for two
MIR instructions which are now created differently.
Add a new asm.js test later which exercises all the possible bitcast operations
as well as all possible load and store operations, except the partial ones.
This commit prepares for that test case.
Add new Scalar::I8x16, I16x8 enumerators.
Remove the fromUintXXX opcodes from the *_ASMJS macros. This avoids gerating
unwanted wasm opcodes. Include the relevant unsigned bit-casts explicitly where
needed.
Since SSE doesn't have unsigned comparisons, add a bias vector and use the
signed comparisons instead, just like we do for the 32x4 unsigned vectors.
Use 'defineReuseInput' even when SIMD input and output types differ. This is
fine now since the register allocator uses a single Simd128 class for all SIMD
registers.
This instruction is used when the shuffle indexes are not compile time
constants.
Give the register allocator permission to spill the index arguments to
GeneralShuffle instructions. There can be up to 16 of them, and they can't all
be registers.
Move visitSimdGeneralShuffle into the x86-specific lowering code since it has
special register allocation requirements for 8-bit lanes.
When SSSE3 is available, two pshufb instructions can be combined to form any
shuffle.
Old machines without SSSE3 bounce the two vectors through the stack.
When we have SSSE3 available, the pshufb instruction can perform any byte-wise
swizzle.
Without SSSE3, fall back to using byte-wise loads and stores to simulate the
swizzle. This applies to CPUs from before 2006.
The scalar argument to this operation is expanded into MIR as either -1 or 0 in
an Int32, so the 4-lane splat produces the correct result for 8-lane and
16-lane splats too. Either an all-zeroes vector or an all-ones vector.
- Rename LSimdBinaryBitwiseX4 to LSimdBinaryBitwise and use it for all types.
- Add pmullw to the assembler for 16x8 multiplies.
Don't implement 8x16 multiplies just yet. There are no SSE instructions for
that operation, so they need to be synthesied from 16x8 multiplies and shuffles.
