#if 0 // // FX Version: fx_4_0 // Child effect (requires effect pool): false // // 2 local buffer(s) // cbuffer cb0 { float4 QuadDesc; // Offset: 0, size: 16 float4 TexCoords; // Offset: 16, size: 16 } cbuffer cb1 { float4 BlurOffsetsH[3]; // Offset: 0, size: 48 float4 BlurOffsetsV[3]; // Offset: 48, size: 48 float4 BlurWeights[3]; // Offset: 96, size: 48 float4 ShadowColor; // Offset: 144, size: 16 } // // 6 local object(s) // Texture2D tex; SamplerState sSampler { Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */); Texture = tex; AddressU = uint(CLAMP /* 3 */); AddressV = uint(CLAMP /* 3 */); }; SamplerState sShadowSampler { Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */); Texture = tex; AddressU = uint(BORDER /* 4 */); AddressV = uint(BORDER /* 4 */); BorderColor = float4(0, 0, 0, 0); }; RasterizerState TextureRast { ScissorEnable = bool(FALSE /* 0 */); CullMode = uint(NONE /* 1 */); }; BlendState ShadowBlendH { BlendEnable[0] = bool(FALSE /* 0 */); RenderTargetWriteMask[0] = byte(0x0f); }; BlendState ShadowBlendV { BlendEnable[0] = bool(TRUE /* 1 */); SrcBlend[0] = uint(ONE /* 2 */); DestBlend[0] = uint(INV_SRC_ALPHA /* 6 */); BlendOp[0] = uint(ADD /* 1 */); SrcBlendAlpha[0] = uint(ONE /* 2 */); DestBlendAlpha[0] = uint(INV_SRC_ALPHA /* 6 */); BlendOpAlpha[0] = uint(ADD /* 1 */); RenderTargetWriteMask[0] = byte(0x0f); }; // // 2 technique(s) // technique10 SampleTexture { pass P0 { RasterizerState = TextureRast; VertexShader = asm { // // Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111 // // // Buffer Definitions: // // cbuffer cb0 // { // // float4 QuadDesc; // Offset: 0 Size: 16 // float4 TexCoords; // Offset: 16 Size: 16 // // } // // // Resource Bindings: // // Name Type Format Dim Slot Elements // ------------------------------ ---------- ------- ----------- ---- -------- // cb0 cbuffer NA NA 0 1 // // // // Input signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // POSITION 0 xyz 0 NONE float xy // // // Output signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Position 0 xyzw 0 POS float xyzw // TEXCOORD 0 xy 1 NONE float xy // // // Constant buffer to DX9 shader constant mappings: // // Target Reg Buffer Start Reg # of Regs Data Conversion // ---------- ------- --------- --------- ---------------------- // c1 cb0 0 2 ( FLT, FLT, FLT, FLT) // // // Runtime generated constant mappings: // // Target Reg Constant Description // ---------- -------------------------------------------------- // c0 Vertex Shader position offset // // // Level9 shader bytecode: // vs_2_x def c3, 0, 1, 0, 0 dcl_texcoord v0 mad oT0.xy, v0, c2.zwzw, c2 mad r0.xy, v0, c1.zwzw, c1 add oPos.xy, r0, c0 mov oPos.zw, c3.xyxy // approximately 4 instruction slots used vs_4_0 dcl_constantbuffer cb0[2], immediateIndexed dcl_input v0.xy dcl_output_siv o0.xyzw, position dcl_output o1.xy mad o0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx mov o0.zw, l(0,0,0,1.000000) mad o1.xy, v0.xyxx, cb0[1].zwzz, cb0[1].xyxx ret // Approximately 4 instruction slots used }; GeometryShader = NULL; PixelShader = asm { // // Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111 // // // Resource Bindings: // // Name Type Format Dim Slot Elements // ------------------------------ ---------- ------- ----------- ---- -------- // sSampler sampler NA NA 0 1 // tex texture float4 2d 0 1 // // // // Input signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Position 0 xyzw 0 POS float // TEXCOORD 0 xy 1 NONE float xy // // // Output signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Target 0 xyzw 0 TARGET float xyzw // // // Sampler/Resource to DX9 shader sampler mappings: // // Target Sampler Source Sampler Source Resource // -------------- --------------- ---------------- // s0 s0 t0 // // // Level9 shader bytecode: // ps_2_x dcl t0.xy dcl_2d s0 texld r0, t0, s0 mov oC0, r0 // approximately 2 instruction slots used (1 texture, 1 arithmetic) ps_4_0 dcl_sampler s0, mode_default dcl_resource_texture2d (float,float,float,float) t0 dcl_input_ps linear v1.xy dcl_output o0.xyzw sample o0.xyzw, v1.xyxx, t0.xyzw, s0 ret // Approximately 2 instruction slots used }; } } technique10 SampleTextureWithShadow { pass P0 { RasterizerState = TextureRast; AB_BlendFactor = float4(1, 1, 1, 1); AB_SampleMask = uint(0xffffffff); BlendState = ShadowBlendH; VertexShader = asm { // // Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111 // // // Buffer Definitions: // // cbuffer cb0 // { // // float4 QuadDesc; // Offset: 0 Size: 16 // float4 TexCoords; // Offset: 16 Size: 16 // // } // // // Resource Bindings: // // Name Type Format Dim Slot Elements // ------------------------------ ---------- ------- ----------- ---- -------- // cb0 cbuffer NA NA 0 1 // // // // Input signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // POSITION 0 xyz 0 NONE float xy // // // Output signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Position 0 xyzw 0 POS float xyzw // TEXCOORD 0 xy 1 NONE float xy // // // Constant buffer to DX9 shader constant mappings: // // Target Reg Buffer Start Reg # of Regs Data Conversion // ---------- ------- --------- --------- ---------------------- // c1 cb0 0 2 ( FLT, FLT, FLT, FLT) // // // Runtime generated constant mappings: // // Target Reg Constant Description // ---------- -------------------------------------------------- // c0 Vertex Shader position offset // // // Level9 shader bytecode: // vs_2_x def c3, 0, 1, 0, 0 dcl_texcoord v0 mad oT0.xy, v0, c2.zwzw, c2 mad r0.xy, v0, c1.zwzw, c1 add oPos.xy, r0, c0 mov oPos.zw, c3.xyxy // approximately 4 instruction slots used vs_4_0 dcl_constantbuffer cb0[2], immediateIndexed dcl_input v0.xy dcl_output_siv o0.xyzw, position dcl_output o1.xy mad o0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx mov o0.zw, l(0,0,0,1.000000) mad o1.xy, v0.xyxx, cb0[1].zwzz, cb0[1].xyxx ret // Approximately 4 instruction slots used }; GeometryShader = NULL; PixelShader = asm { // // Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111 // // // Buffer Definitions: // // cbuffer cb1 // { // // float4 BlurOffsetsH[3]; // Offset: 0 Size: 48 // float4 BlurOffsetsV[3]; // Offset: 48 Size: 48 [unused] // float4 BlurWeights[3]; // Offset: 96 Size: 48 // float4 ShadowColor; // Offset: 144 Size: 16 // // } // // // Resource Bindings: // // Name Type Format Dim Slot Elements // ------------------------------ ---------- ------- ----------- ---- -------- // sShadowSampler sampler NA NA 0 1 // tex texture float4 2d 0 1 // cb1 cbuffer NA NA 0 1 // // // // Input signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Position 0 xyzw 0 POS float // TEXCOORD 0 xy 1 NONE float xy // // // Output signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Target 0 xyzw 0 TARGET float xyzw // // // Constant buffer to DX9 shader constant mappings: // // Target Reg Buffer Start Reg # of Regs Data Conversion // ---------- ------- --------- --------- ---------------------- // c0 cb0 0 3 ( FLT, FLT, FLT, FLT) // c3 cb0 6 4 ( FLT, FLT, FLT, FLT) // // // Sampler/Resource to DX9 shader sampler mappings: // // Target Sampler Source Sampler Source Resource // -------------- --------------- ---------------- // s0 s0 t0 // // // Level9 shader bytecode: // ps_2_x dcl t0.xy dcl_2d s0 add r0.x, t0.x, c0.y mov r0.y, t0.y add r1.x, t0.x, c0.x mov r1.y, t0.y texld r0, r0, s0 texld r1, r1, s0 mul r0.x, r0.w, c3.y mad r0.x, c3.x, r1.w, r0.x add r1.x, t0.x, c0.z mov r1.y, t0.y add r2.x, t0.x, c0.w mov r2.y, t0.y texld r1, r1, s0 texld r2, r2, s0 mad r0.x, c3.z, r1.w, r0.x mad r0.x, c3.w, r2.w, r0.x add r1.x, t0.x, c1.x mov r1.y, t0.y add r2.x, t0.x, c1.y mov r2.y, t0.y texld r1, r1, s0 texld r2, r2, s0 mad r0.x, c4.x, r1.w, r0.x mad r0.x, c4.y, r2.w, r0.x add r1.x, t0.x, c1.z mov r1.y, t0.y add r2.x, t0.x, c1.w mov r2.y, t0.y texld r1, r1, s0 texld r2, r2, s0 mad r0.x, c4.z, r1.w, r0.x mad r0.x, c4.w, r2.w, r0.x add r1.x, t0.x, c2.x mov r1.y, t0.y texld r1, r1, s0 mad r0.x, c5.x, r1.w, r0.x mul r0, r0.x, c6 mov oC0, r0 // approximately 38 instruction slots used (9 texture, 29 arithmetic) ps_4_0 dcl_constantbuffer cb0[10], immediateIndexed dcl_sampler s0, mode_default dcl_resource_texture2d (float,float,float,float) t0 dcl_input_ps linear v1.xy dcl_output o0.xyzw dcl_temps 4 add r0.xyzw, v1.xxxx, cb0[0].zxwy mov r1.xz, r0.yywy mov r1.yw, v1.yyyy sample r2.xyzw, r1.zwzz, t0.xyzw, s0 sample r1.xyzw, r1.xyxx, t0.xyzw, s0 mul r1.x, r2.w, cb0[6].y mad r1.x, cb0[6].x, r1.w, r1.x mov r0.yw, v1.yyyy sample r2.xyzw, r0.xyxx, t0.xyzw, s0 sample r0.xyzw, r0.zwzz, t0.xyzw, s0 mad r0.x, cb0[6].z, r2.w, r1.x mad r0.x, cb0[6].w, r0.w, r0.x add r1.xyzw, v1.xxxx, cb0[1].zxwy mov r2.xz, r1.yywy mov r2.yw, v1.yyyy sample r3.xyzw, r2.xyxx, t0.xyzw, s0 sample r2.xyzw, r2.zwzz, t0.xyzw, s0 mad r0.x, cb0[7].x, r3.w, r0.x mad r0.x, cb0[7].y, r2.w, r0.x mov r1.yw, v1.yyyy sample r2.xyzw, r1.xyxx, t0.xyzw, s0 sample r1.xyzw, r1.zwzz, t0.xyzw, s0 mad r0.x, cb0[7].z, r2.w, r0.x mad r0.x, cb0[7].w, r1.w, r0.x add r1.x, v1.x, cb0[2].x mov r1.y, v1.y sample r1.xyzw, r1.xyxx, t0.xyzw, s0 mad r0.x, cb0[8].x, r1.w, r0.x mul o0.xyzw, r0.xxxx, cb0[9].xyzw ret // Approximately 30 instruction slots used }; } pass P1 { RasterizerState = TextureRast; AB_BlendFactor = float4(1, 1, 1, 1); AB_SampleMask = uint(0xffffffff); BlendState = ShadowBlendV; VertexShader = asm { // // Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111 // // // Buffer Definitions: // // cbuffer cb0 // { // // float4 QuadDesc; // Offset: 0 Size: 16 // float4 TexCoords; // Offset: 16 Size: 16 // // } // // // Resource Bindings: // // Name Type Format Dim Slot Elements // ------------------------------ ---------- ------- ----------- ---- -------- // cb0 cbuffer NA NA 0 1 // // // // Input signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // POSITION 0 xyz 0 NONE float xy // // // Output signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Position 0 xyzw 0 POS float xyzw // TEXCOORD 0 xy 1 NONE float xy // // // Constant buffer to DX9 shader constant mappings: // // Target Reg Buffer Start Reg # of Regs Data Conversion // ---------- ------- --------- --------- ---------------------- // c1 cb0 0 2 ( FLT, FLT, FLT, FLT) // // // Runtime generated constant mappings: // // Target Reg Constant Description // ---------- -------------------------------------------------- // c0 Vertex Shader position offset // // // Level9 shader bytecode: // vs_2_x def c3, 0, 1, 0, 0 dcl_texcoord v0 mad oT0.xy, v0, c2.zwzw, c2 mad r0.xy, v0, c1.zwzw, c1 add oPos.xy, r0, c0 mov oPos.zw, c3.xyxy // approximately 4 instruction slots used vs_4_0 dcl_constantbuffer cb0[2], immediateIndexed dcl_input v0.xy dcl_output_siv o0.xyzw, position dcl_output o1.xy mad o0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx mov o0.zw, l(0,0,0,1.000000) mad o1.xy, v0.xyxx, cb0[1].zwzz, cb0[1].xyxx ret // Approximately 4 instruction slots used }; GeometryShader = NULL; PixelShader = asm { // // Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111 // // // Buffer Definitions: // // cbuffer cb1 // { // // float4 BlurOffsetsH[3]; // Offset: 0 Size: 48 [unused] // float4 BlurOffsetsV[3]; // Offset: 48 Size: 48 // float4 BlurWeights[3]; // Offset: 96 Size: 48 // float4 ShadowColor; // Offset: 144 Size: 16 [unused] // // } // // // Resource Bindings: // // Name Type Format Dim Slot Elements // ------------------------------ ---------- ------- ----------- ---- -------- // sShadowSampler sampler NA NA 0 1 // tex texture float4 2d 0 1 // cb1 cbuffer NA NA 0 1 // // // // Input signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Position 0 xyzw 0 POS float // TEXCOORD 0 xy 1 NONE float xy // // // Output signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------ ------ // SV_Target 0 xyzw 0 TARGET float xyzw // // // Constant buffer to DX9 shader constant mappings: // // Target Reg Buffer Start Reg # of Regs Data Conversion // ---------- ------- --------- --------- ---------------------- // c0 cb0 3 6 ( FLT, FLT, FLT, FLT) // // // Sampler/Resource to DX9 shader sampler mappings: // // Target Sampler Source Sampler Source Resource // -------------- --------------- ---------------- // s0 s0 t0 // // // Level9 shader bytecode: // ps_2_x dcl t0.xy dcl_2d s0 add r0.y, t0.y, c0.y mov r0.x, t0.x add r1.y, t0.y, c0.x mov r1.x, t0.x texld r0, r0, s0 texld r1, r1, s0 mul r0, r0, c3.y mad r0, c3.x, r1, r0 add r1.y, t0.y, c0.z mov r1.x, t0.x add r2.y, t0.y, c0.w mov r2.x, t0.x texld r1, r1, s0 texld r2, r2, s0 mad r0, c3.z, r1, r0 mad r0, c3.w, r2, r0 add r1.y, t0.y, c1.x mov r1.x, t0.x add r2.y, t0.y, c1.y mov r2.x, t0.x texld r1, r1, s0 texld r2, r2, s0 mad r0, c4.x, r1, r0 mad r0, c4.y, r2, r0 add r1.y, t0.y, c1.z mov r1.x, t0.x add r2.y, t0.y, c1.w mov r2.x, t0.x texld r1, r1, s0 texld r2, r2, s0 mad r0, c4.z, r1, r0 mad r0, c4.w, r2, r0 add r1.y, t0.y, c2.x mov r1.x, t0.x texld r1, r1, s0 mad r0, c5.x, r1, r0 mov oC0, r0 // approximately 37 instruction slots used (9 texture, 28 arithmetic) ps_4_0 dcl_constantbuffer cb0[9], immediateIndexed dcl_sampler s0, mode_default dcl_resource_texture2d (float,float,float,float) t0 dcl_input_ps linear v1.xy dcl_output o0.xyzw dcl_temps 4 mov r0.xz, v1.xxxx add r1.xyzw, v1.yyyy, cb0[3].xzyw mov r0.yw, r1.xxxz sample r2.xyzw, r0.zwzz, t0.xyzw, s0 sample r0.xyzw, r0.xyxx, t0.xyzw, s0 mul r2.xyzw, r2.xyzw, cb0[6].yyyy mad r0.xyzw, cb0[6].xxxx, r0.xyzw, r2.xyzw mov r1.xz, v1.xxxx sample r2.xyzw, r1.xyxx, t0.xyzw, s0 sample r1.xyzw, r1.zwzz, t0.xyzw, s0 mad r0.xyzw, cb0[6].zzzz, r2.xyzw, r0.xyzw mad r0.xyzw, cb0[6].wwww, r1.xyzw, r0.xyzw mov r1.xz, v1.xxxx add r2.xyzw, v1.yyyy, cb0[4].xzyw mov r1.yw, r2.xxxz sample r3.xyzw, r1.xyxx, t0.xyzw, s0 sample r1.xyzw, r1.zwzz, t0.xyzw, s0 mad r0.xyzw, cb0[7].xxxx, r3.xyzw, r0.xyzw mad r0.xyzw, cb0[7].yyyy, r1.xyzw, r0.xyzw mov r2.xz, v1.xxxx sample r1.xyzw, r2.xyxx, t0.xyzw, s0 sample r2.xyzw, r2.zwzz, t0.xyzw, s0 mad r0.xyzw, cb0[7].zzzz, r1.xyzw, r0.xyzw mad r0.xyzw, cb0[7].wwww, r2.xyzw, r0.xyzw add r1.y, v1.y, cb0[5].x mov r1.x, v1.x sample r1.xyzw, r1.xyxx, t0.xyzw, s0 mad o0.xyzw, cb0[8].xxxx, r1.xyzw, r0.xyzw ret // Approximately 29 instruction slots used }; } } #endif const BYTE d2deffect[] = { 68, 88, 66, 67, 245, 80, 253, 174, 31, 0, 29, 195, 254, 34, 10, 37, 101, 204, 99, 74, 1, 0, 0, 0, 216, 40, 0, 0, 1, 0, 0, 0, 36, 0, 0, 0, 70, 88, 49, 48, 172, 40, 0, 0, 1, 16, 255, 254, 2, 0, 0, 0, 6, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 80, 36, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 99, 98, 48, 0, 102, 108, 111, 97, 116, 52, 0, 8, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 16, 0, 0, 0, 16, 0, 0, 0, 10, 33, 0, 0, 81, 117, 97, 100, 68, 101, 115, 99, 0, 84, 101, 120, 67, 111, 111, 114, 100, 115, 0, 99, 98, 49, 0, 8, 0, 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 48, 0, 0, 0, 16, 0, 0, 0, 48, 0, 0, 0, 10, 33, 0, 0, 66, 108, 117, 114, 79, 102, 102, 115, 101, 116, 115, 72, 0, 66, 108, 117, 114, 79, 102, 102, 115, 101, 116, 115, 86, 0, 66, 108, 117, 114, 87, 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