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8a0a0f7524
MOZ_RUNINIT => initialized at runtime MOZ_CONSTINIT => initialized at compile time MOZ_GLOBINIT => initialized either at runtime or compile time, depending on template parameter, macro parameter etc This annotation is only understood by our clang-tidy plugin. It has no effect on regular compilation. Differential Revision: https://phabricator.services.mozilla.com/D223341
262 lines
7.4 KiB
C++
262 lines
7.4 KiB
C++
/* vim: set shiftwidth=4 tabstop=8 autoindent cindent expandtab: */
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/* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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/* compile-time and runtime tests for whether to use SSE instructions */
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#include "SSE.h"
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#include "mozilla/Attributes.h"
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#ifdef HAVE_CPUID_H
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// cpuid.h is available on gcc 4.3 and higher on i386 and x86_64
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# include <cpuid.h>
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#elif defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_AMD64))
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// MSVC 2005 or newer on x86-32 or x86-64
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# include <intrin.h>
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#endif
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namespace {
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// SSE.h has parallel #ifs which declare MOZILLA_SSE_HAVE_CPUID_DETECTION.
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// We can't declare these functions in the header file, however, because
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// <intrin.h> conflicts with <windows.h> on MSVC 2005, and some files want to
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// include both SSE.h and <windows.h>.
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#ifdef HAVE_CPUID_H
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enum CPUIDRegister { eax = 0, ebx = 1, ecx = 2, edx = 3 };
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static bool has_cpuid_bits(unsigned int level, CPUIDRegister reg,
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unsigned int bits) {
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unsigned int regs[4];
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unsigned int eax, ebx, ecx, edx;
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unsigned max = __get_cpuid_max(level & 0x80000000u, nullptr);
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if (level > max) return false;
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__cpuid_count(level, 0, eax, ebx, ecx, edx);
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regs[0] = eax;
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regs[1] = ebx;
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regs[2] = ecx;
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regs[3] = edx;
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return (regs[reg] & bits) == bits;
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}
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static bool has_cpuid_bits_ex(unsigned int level, CPUIDRegister reg,
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unsigned int bits) {
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unsigned int regs[4];
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unsigned int eax, ebx, ecx, edx;
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unsigned max = __get_cpuid_max(level & 0x80000000u, nullptr);
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if (level > max) return false;
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__cpuid_count(level, 1, eax, ebx, ecx, edx);
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regs[0] = eax;
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regs[1] = ebx;
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regs[2] = ecx;
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regs[3] = edx;
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return (regs[reg] & bits) == bits;
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}
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#elif defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_AMD64))
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enum CPUIDRegister { eax = 0, ebx = 1, ecx = 2, edx = 3 };
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static bool has_cpuid_bits(unsigned int level, CPUIDRegister reg,
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unsigned int bits) {
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// Check that the level in question is supported.
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int regs[4];
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__cpuid_ex(regs, level & 0x80000000u, 1);
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if (unsigned(regs[0]) < level) return false;
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// "The __cpuid intrinsic clears the ECX register before calling the cpuid
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// instruction."
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__cpuid_ex(regs, level, 1);
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return (unsigned(regs[reg]) & bits) == bits;
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}
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#elif (defined(__GNUC__) || defined(__SUNPRO_CC)) && \
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(defined(__i386) || defined(__x86_64__))
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enum CPUIDRegister { eax = 0, ebx = 1, ecx = 2, edx = 3 };
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# ifdef __i386
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static void moz_cpuid(int CPUInfo[4], int InfoType) {
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asm("xchg %esi, %ebx\n"
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"xor %ecx, %ecx\n" // ecx is the sub-leaf (we only ever need 0)
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"cpuid\n"
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"movl %eax, (%edi)\n"
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"movl %ebx, 4(%edi)\n"
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"movl %ecx, 8(%edi)\n"
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"movl %edx, 12(%edi)\n"
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"xchg %esi, %ebx\n"
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:
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: "a"(InfoType), // %eax
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"D"(CPUInfo) // %edi
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: "%ecx", "%edx", "%esi");
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}
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static void moz_cpuid_ex(int CPUInfo[4], int InfoType) {
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asm("xchg %esi, %ebx\n"
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"movl 1, %ecx\n"
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"cpuid\n"
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"movl %eax, (%edi)\n"
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"movl %ebx, 4(%edi)\n"
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"movl %ecx, 8(%edi)\n"
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"movl %edx, 12(%edi)\n"
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"xchg %esi, %ebx\n"
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:
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: "a"(InfoType), // %eax
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"D"(CPUInfo) // %edi
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: "%ecx", "%edx", "%esi");
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}
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# else
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static void moz_cpuid(int CPUInfo[4], int InfoType) {
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asm("xchg %rsi, %rbx\n"
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"xor %ecx, %ecx\n" // ecx is the sub-leaf (we only ever need 0)
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"cpuid\n"
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"movl %eax, (%rdi)\n"
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"movl %ebx, 4(%rdi)\n"
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"movl %ecx, 8(%rdi)\n"
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"movl %edx, 12(%rdi)\n"
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"xchg %rsi, %rbx\n"
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:
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: "a"(InfoType), // %eax
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"D"(CPUInfo) // %rdi
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: "%ecx", "%edx", "%rsi");
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}
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static void moz_cpuid_ex(int CPUInfo[4], int InfoType) {
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asm("xchg %rsi, %rbx\n"
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"movl 1, %ecx\n"
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"cpuid\n"
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"movl %eax, (%rdi)\n"
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"movl %ebx, 4(%rdi)\n"
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"movl %ecx, 8(%rdi)\n"
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"movl %edx, 12(%rdi)\n"
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"xchg %rsi, %rbx\n"
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:
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: "a"(InfoType), // %eax
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"D"(CPUInfo) // %rdi
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: "%ecx", "%edx", "%rsi");
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}
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# endif
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static bool has_cpuid_bits(unsigned int level, CPUIDRegister reg,
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unsigned int bits) {
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// Check that the level in question is supported.
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volatile int regs[4];
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moz_cpuid((int*)regs, level & 0x80000000u);
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if (unsigned(regs[0]) < level) return false;
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moz_cpuid((int*)regs, level);
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return (unsigned(regs[reg]) & bits) == bits;
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}
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static bool has_cpuid_bits_ex(unsigned int level, CPUIDRegister reg,
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unsigned int bits) {
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// Check that the level in question is supported.
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volatile int regs[4];
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moz_cpuid_ex((int*)regs, level & 0x80000000u);
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if (unsigned(regs[0]) < level) return false;
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moz_cpuid_ex((int*)regs, level);
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return (unsigned(regs[reg]) & bits) == bits;
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}
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#endif // end CPUID declarations
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} // namespace
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namespace mozilla {
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namespace sse_private {
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#if defined(MOZILLA_SSE_HAVE_CPUID_DETECTION)
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# if !defined(MOZILLA_PRESUME_MMX)
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MOZ_RUNINIT bool mmx_enabled = has_cpuid_bits(1u, edx, (1u << 23));
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# endif
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# if !defined(MOZILLA_PRESUME_SSE)
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MOZ_RUNINIT bool sse_enabled = has_cpuid_bits(1u, edx, (1u << 25));
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# endif
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# if !defined(MOZILLA_PRESUME_SSE2)
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MOZ_RUNINIT bool sse2_enabled = has_cpuid_bits(1u, edx, (1u << 26));
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# endif
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# if !defined(MOZILLA_PRESUME_SSE3)
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MOZ_RUNINIT bool sse3_enabled = has_cpuid_bits(1u, ecx, (1u << 0));
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# endif
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# if !defined(MOZILLA_PRESUME_SSSE3)
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MOZ_RUNINIT bool ssse3_enabled = has_cpuid_bits(1u, ecx, (1u << 9));
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# endif
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# if !defined(MOZILLA_PRESUME_SSE4A)
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MOZ_RUNINIT bool sse4a_enabled = has_cpuid_bits(0x80000001u, ecx, (1u << 6));
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# endif
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# if !defined(MOZILLA_PRESUME_SSE4_1)
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MOZ_RUNINIT bool sse4_1_enabled = has_cpuid_bits(1u, ecx, (1u << 19));
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# endif
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# if !defined(MOZILLA_PRESUME_SSE4_2)
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MOZ_RUNINIT bool sse4_2_enabled = has_cpuid_bits(1u, ecx, (1u << 20));
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# endif
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# if !defined(MOZILLA_PRESUME_FMA3)
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MOZ_RUNINIT bool fma3_enabled = has_cpuid_bits(1u, ecx, (1u << 12));
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# endif
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# if !defined(MOZILLA_PRESUME_AVX) || !defined(MOZILLA_PRESUME_AVX2)
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static bool has_avx() {
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# if defined(MOZILLA_PRESUME_AVX)
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return true;
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# else
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const unsigned AVX = 1u << 28;
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const unsigned OSXSAVE = 1u << 27;
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const unsigned XSAVE = 1u << 26;
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const unsigned XMM_STATE = 1u << 1;
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const unsigned YMM_STATE = 1u << 2;
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const unsigned AVX_STATE = XMM_STATE | YMM_STATE;
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return has_cpuid_bits(1u, ecx, AVX | OSXSAVE | XSAVE) &&
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// ensure the OS supports XSAVE of YMM registers
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(xgetbv(0) & AVX_STATE) == AVX_STATE;
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# endif // MOZILLA_PRESUME_AVX
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}
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# endif // !MOZILLA_PRESUME_AVX || !MOZILLA_PRESUME_AVX2
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# if !defined(MOZILLA_PRESUME_AVX)
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MOZ_RUNINIT bool avx_enabled = has_avx();
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# endif
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# if !defined(MOZILLA_PRESUME_AVX2)
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MOZ_RUNINIT bool avx2_enabled = has_avx() && has_cpuid_bits(7u, ebx, (1u << 5));
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# endif
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# if !defined(MOZILLA_PRESUME_AVXVNNI)
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MOZ_RUNINIT bool avxvnni_enabled = has_cpuid_bits_ex(7u, eax, (1u << 4));
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# endif
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# if !defined(MOZILLA_PRESUME_AES)
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MOZ_RUNINIT bool aes_enabled = has_cpuid_bits(1u, ecx, (1u << 25));
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# endif
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MOZ_RUNINIT bool has_constant_tsc = has_cpuid_bits(0x80000007u, edx, (1u << 8));
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#endif
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} // namespace sse_private
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#ifdef HAVE_CPUID_H
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uint64_t xgetbv(uint32_t xcr) {
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uint32_t eax, edx;
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__asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
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return (uint64_t)(edx) << 32 | eax;
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}
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#endif
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} // namespace mozilla
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