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307e5968d6
Results of running ./update.py --ndk ~/android/android-ndk-r9
--commit c731d6a4f19eea861ceb2ff31399420b2452eb74
71 lines
3.4 KiB
Perl
71 lines
3.4 KiB
Perl
#!/usr/bin/env perl
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##
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## Copyright (c) 2013 The WebM project authors. All Rights Reserved.
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##
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## Use of this source code is governed by a BSD-style license
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## that can be found in the LICENSE file in the root of the source
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## tree. An additional intellectual property rights grant can be found
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## in the file PATENTS. All contributing project authors may
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## be found in the AUTHORS file in the root of the source tree.
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##
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package thumb;
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sub FixThumbInstructions($$)
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{
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my $short_branches = $_[1];
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my $branch_shift_offset = $short_branches ? 1 : 0;
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# Write additions with shifts, such as "add r10, r11, lsl #8",
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# in three operand form, "add r10, r10, r11, lsl #8".
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s/(add\s+)(r\d+),\s*(r\d+),\s*(lsl #\d+)/$1$2, $2, $3, $4/g;
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# Convert additions with a non-constant shift into a sequence
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# with left shift, addition and a right shift (to restore the
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# register to the original value). Currently the right shift
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# isn't necessary in the code base since the values in these
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# registers aren't used, but doing the shift for consistency.
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# This converts instructions such as "add r12, r12, r5, lsl r4"
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# into the sequence "lsl r5, r4", "add r12, r12, r5", "lsr r5, r4".
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s/^(\s*)(add)(\s+)(r\d+),\s*(r\d+),\s*(r\d+),\s*lsl (r\d+)/$1lsl$3$6, $7\n$1$2$3$4, $5, $6\n$1lsr$3$6, $7/g;
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# Convert loads with right shifts in the indexing into a
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# sequence of an add, load and sub. This converts
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# "ldrb r4, [r9, lr, asr #1]" into "add r9, r9, lr, asr #1",
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# "ldrb r9, [r9]", "sub r9, r9, lr, asr #1".
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s/^(\s*)(ldrb)(\s+)(r\d+),\s*\[(\w+),\s*(\w+),\s*(asr #\d+)\]/$1add $3$5, $5, $6, $7\n$1$2$3$4, [$5]\n$1sub $3$5, $5, $6, $7/g;
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# Convert register indexing with writeback into a separate add
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# instruction. This converts "ldrb r12, [r1, r2]!" into
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# "ldrb r12, [r1, r2]", "add r1, r1, r2".
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s/^(\s*)(ldrb)(\s+)(r\d+),\s*\[(\w+),\s*(\w+)\]!/$1$2$3$4, [$5, $6]\n$1add $3$5, $6/g;
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# Convert negative register indexing into separate sub/add instructions.
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# This converts "ldrne r4, [src, -pstep, lsl #1]" into
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# "subne src, src, pstep, lsl #1", "ldrne r4, [src]",
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# "addne src, src, pstep, lsl #1". In a couple of cases where
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# this is used, it's used for two subsequent load instructions,
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# where a hand-written version of it could merge two subsequent
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# add and sub instructions.
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s/^(\s*)((ldr|str|pld)(ne)?)(\s+)(r\d+,\s*)?\[(\w+), -([^\]]+)\]/$1sub$4$5$7, $7, $8\n$1$2$5$6\[$7\]\n$1add$4$5$7, $7, $8/g;
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# Convert register post indexing to a separate add instruction.
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# This converts "ldrneb r9, [r0], r2" into "ldrneb r9, [r0]",
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# "addne r0, r0, r2".
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s/^(\s*)((ldr|str)(ne)?[bhd]?)(\s+)(\w+),(\s*\w+,)?\s*\[(\w+)\],\s*(\w+)/$1$2$5$6,$7 [$8]\n$1add$4$5$8, $8, $9/g;
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# Convert a conditional addition to the pc register into a series of
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# instructions. This converts "addlt pc, pc, r3, lsl #2" into
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# "itttt lt", "movlt.n r12, pc", "addlt.w r12, #12",
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# "addlt.w r12, r12, r3, lsl #2", "movlt.n pc, r12".
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# This assumes that r12 is free at this point.
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s/^(\s*)addlt(\s+)pc,\s*pc,\s*(\w+),\s*lsl\s*#(\d+)/$1itttt$2lt\n$1movlt.n$2r12, pc\n$1addlt.w$2r12, #12\n$1addlt.w$2r12, r12, $3, lsl #($4-$branch_shift_offset)\n$1movlt.n$2pc, r12/g;
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# Convert "mov pc, lr" into "bx lr", since the former only works
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# for switching from arm to thumb (and only in armv7), but not
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# from thumb to arm.
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s/mov(\s*)pc\s*,\s*lr/bx$1lr/g;
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}
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1;
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