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100 lines
3.2 KiB
C++
100 lines
3.2 KiB
C++
/* -*- Mode: C++; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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*
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* The contents of this file are subject to the Netscape Public
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* License Version 1.1 (the "License"); you may not use this file
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* except in compliance with the License. You may obtain a copy of
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* the License at http://www.mozilla.org/NPL/
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*
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* Software distributed under the License is distributed on an "AS
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* IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
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* implied. See the License for the specific language governing
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* rights and limitations under the License.
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*
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* The Original Code is mozilla.org code.
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*
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* The Initial Developer of the Original Code is Netscape
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* Communications Corporation. Portions created by Netscape are
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* Copyright (C) 1998 Netscape Communications Corporation. All
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* Rights Reserved.
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*
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* Contributor(s):
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*/
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#ifndef _REGISTER_ALLOCATOR_H_
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#define _REGISTER_ALLOCATOR_H_
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#include "RegisterAssigner.h"
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#include "Coloring.h"
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#include "FastBitMatrix.h"
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#include "Spilling.h"
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#include "LogModule.h"
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class ControlGraph;
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class InstructionEmitter;
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class VirtualRegisterManager;
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class FastBitMatrix;
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class Pool;
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extern void printGraph(Uint32 nNodes, ControlNode** dfsList);
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/*
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*--------------------------RegisterAllocator.h----------------------------
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*
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* class RegisterAllocator --
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*
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*-----------------------------------------------------------------------
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*/
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class RegisterAllocator
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{
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private:
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Pool& regAllocPool; // Register Allocation Pool.
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/*
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* ControlGraph data.
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*/
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ControlNode** dfsList; // List of the nodes in Depth First Search order.
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ControlNode** lndList; // List of the nodes in Loop Nesting Depth order.
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PRUint32 nNodes; // Number of nodes in this graph.
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VirtualRegisterManager& vRegManager; // Virtual Register Manager for this graph.
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MdEmitter& instructionEmitter; // Instruction emitter for this platform.
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Coloring registerAssigner; // Register assigner (right now only graph coloring is supported)
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Spilling spilling; // Register spilling
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FastBitMatrix interferenceMatrix; // Register interference matrix.
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/*
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* Register Allocation core private methods.
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*/
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void checkRegisterClassConflicts();
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void checkPhiNodesAnnotation();
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void buildInterferenceGraph();
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bool canCoalesceRegisters(VirtualRegister& inVR, VirtualRegister& outVR, PRUint32& from, PRUint32& to);
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void coalesceRegisters(PRUint32 from, PRUint32 to);
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void coalesce();
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void calculateSpillCosts();
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void spillPhiNodes();
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bool removePhiNodes();
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void updateLocalVariableTable();
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#ifdef DEBUG_LOG
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void printRegisterDebug(LogModuleObject &f, bool verbose = false);
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#endif
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public:
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/*
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* Constructor.
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*/
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RegisterAllocator(Pool& pool, ControlNode** dfs, ControlNode **lnd, PRUint32 n, VirtualRegisterManager& vrMan, MdEmitter& emitter) :
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regAllocPool(pool), dfsList(dfs), lndList(lnd), nNodes(n), vRegManager(vrMan), instructionEmitter(emitter),
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registerAssigner(pool, vRegManager), spilling(vrMan, emitter), interferenceMatrix(pool) {}
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/*
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* Public call for register allocation.
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*/
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void allocateRegisters();
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};
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#endif /* _REGISTER_ALLOCATOR_H_ */
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