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GT-3466 Fixed export of local variables as constants

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ghidorahrex 2020-02-07 12:07:26 -05:00
parent eb59366386
commit 02319781b6
4 changed files with 10 additions and 10 deletions
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4
Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
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@ -1837,8 +1837,8 @@ is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1
# C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 KEEPWITH
# sf == 0 && sz = 00 CRC32CB variant
crcpoly: "" is b_12=0 { local tmp = 0x04C11DB7:4; export *[const]:4 tmp; }
crcpoly: "c" is b_12=1 { local tmp = 0x1EDC6F41:4; export *[const]:4 tmp; }
crcpoly: "" is b_12=0 {export *[const]:4 0x04C11DB7:4; }
crcpoly: "c" is b_12=1 { export *[const]:4 0x1EDC6F41:4; }
# C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 MATCH x1ac04000/mask=x7fe0f000
# C6.2.60 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-613 line 35898 MATCH x1ac05000/mask=x7fe0f000

8
Ghidra/Processors/MIPS/data/languages/mips16.sinc
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@ -137,11 +137,11 @@ EXT_IS0: val is m16_i_imm [ val = m16_i_imm << 0; ] { export *[const]:2 val
EXT_IS1: val is m16_i_imm [ val = m16_i_imm << 1; ] { export *[const]:2 val; }
EXT_RI: val is ext_value_1511 & ext_value_1005 & m16_ri_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_ri_imm; ] { export *[const]:2 val; }
EXT_RRIA: val is ext_is_ext=1 & ext_value_1411s & ext_value_1004 & m16_rria_imm [ val=(ext_value_1411s << 11) | (ext_value_1004 << 4) | m16_rria_imm; ] { export *[const]:2 val; }
EXT_RRIA: m16_rria_simm is ext_is_ext=0 & m16_rria_simm { tmp:1 = m16_rria_simm; tmpa:2 = sext(tmp); export *[const]:2 tmpa; }
EXT_RRIA: m16_rria_simm is ext_is_ext=0 & m16_rria_simm { export *[const]:2 m16_rria_simm; }
EXT_IS8: val is ext_is_ext=1 & ext_value_1511s & ext_value_1005 & m16_i8_imm [val=(ext_value_1511s << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; }
EXT_IS8: m16_is8_imm is ext_is_ext=0 & m16_is8_imm { tmp:1 = m16_is8_imm; tmpa:2 = sext(tmp); export *[const]:2 tmpa; }
EXT_IS8L3: val is ext_is_ext=0 & ext_value_1511 & ext_value_1005 & m16_is8_imm [val = m16_is8_imm << 3; ] { tmp:2 = val; export *[const]:2 tmp; }
EXT_IS8: m16_is8_imm is ext_is_ext=0 & m16_is8_imm { export *[const]:2 m16_is8_imm; }
EXT_IS8L3: val is ext_is_ext=0 & ext_value_1511 & ext_value_1005 & m16_is8_imm [val = m16_is8_imm << 3; ] { export *[const]:2 val; }
EXT_IU8: val is ext_is_ext=1 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; }
EXT_IU8: val is ext_is_ext=0 & m16_iu8_imm [val = m16_iu8_imm << 2; ] { export *[const]:2 val; }
@ -153,7 +153,7 @@ EXT_SHIFT: ext_value_sa40 is ext_is_ext=1 & ext_value_saz=0 & m16_shft_sa=0 &
EXT_SHIFT: val is ext_is_ext=0 & m16_shft_sa=0 [val = 8; ] { export *[const]:1 val;}
EXT_SHIFT: m16_shft_sa is ext_is_ext=0 & m16_shft_sa { export *[const]:1 m16_shft_sa;}
EXT_SET: val is ext_is_ext=1 & m16_ri_z=0 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { tmp:2 = val; tmpb:4 = sext(tmp); export *[const]:4 tmpb; }
EXT_SET: val is ext_is_ext=1 & m16_ri_z=0 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:4 val; }
EXT_SET: m16_iu8_imm is ext_is_ext=0 & m16_iu8_imm { export *[const]:4 m16_iu8_imm; }
OFF_M16: EXT_IS8(m16_rx) is ext_is_ext=1 & EXT_IS8 & m16_rx { tmp:$(REGSIZE) = m16_rx + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }

4
Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc
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@ -284,7 +284,7 @@ REG_B_AS: indexExtWord16_0_16s^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 &
REG_B_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):
REG_B_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):
REG_B_AS: labelCalc is reg16_0_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic
REG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {tmp:1 = indexExtWord16_0_16[0,8]; export *[const]:1 tmp; } # Immediate
REG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 { export *[const]:1 indexExtWord16_0_16; } # Immediate
REG_B_AS: "&"^indexExtWord16_0_16 is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute
REG_B_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;} # Constant
REG_B_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;} # Constant
@ -324,7 +324,7 @@ SRC_B_AS: indexExtWord16_0_16s^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 &
SRC_B_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):
SRC_B_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):
SRC_B_AS: labelCalc is src16_8_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic
SRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {tmp:1 = indexExtWord16_0_16[0,8]; export *[const]:1 tmp;} # Immediate
SRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16;} # Immediate
SRC_B_AS: "&"^indexExtWord16_0_16 is src16_8_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute
SRC_B_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; } # Constant
SRC_B_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; } # Constant

4
Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc
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@ -46,7 +46,7 @@ XREG_B_AS: indexExtWord16_0_16s^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 &
XREG_B_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):
XREG_B_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):
XREG_B_AS: labelCalc is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:1 labelCalc; } # Symbolic
XREG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {tmp:1 = indexExtWord16_0_16[0,8]; export *[const]:1 tmp; } # Immediate
XREG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16; } # Immediate
XREG_B_AS: "&"^indexExtWord16_0_16 is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute
XREG_B_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;} # Constant
XREG_B_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;} # Constant
@ -159,7 +159,7 @@ XSRC_B_AS: indexExtWord16_0_16s^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 &
XSRC_B_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):
XSRC_B_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):
XSRC_B_AS: labelCalc is src16_8_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:1 labelCalc; } # Symbolic
XSRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {tmp:1 = indexExtWord16_0_16[0,8]; export *[const]:1 tmp;} # Immediate
XSRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16;} # Immediate
XSRC_B_AS: "&"^indexExtWord16_0_16 is src16_8_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute
XSRC_B_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; } # Constant
XSRC_B_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; } # Constant