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Merge remote-tracking branch 'origin/patch'

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This commit is contained in:
Ryan Kurtz 2023-02-08 06:10:33 -05:00
commit 1de4b32e51
23 changed files with 209 additions and 183 deletions
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4
Ghidra/Features/Decompiler/src/decompile/cpp/type.cc
View File

@ -820,7 +820,7 @@ void TypePointer::encode(Encoder &encoder) const
encoder.openElement(ELEM_TYPE);
encodeBasic(metatype,encoder);
if (wordsize != 1)
encoder.writeSignedInteger(ATTRIB_WORDSIZE, wordsize);
encoder.writeUnsignedInteger(ATTRIB_WORDSIZE, wordsize);
if (spaceid != (AddrSpace *)0)
encoder.writeSpace(ATTRIB_SPACE, spaceid);
ptrto->encodeRef(encoder);
@ -2129,7 +2129,7 @@ void TypePointerRel::encode(Encoder &encoder) const
encoder.openElement(ELEM_TYPE);
encodeBasic(TYPE_PTRREL,encoder); // Override the metatype for XML
if (wordsize != 1)
encoder.writeSignedInteger(ATTRIB_WORDSIZE, wordsize);
encoder.writeUnsignedInteger(ATTRIB_WORDSIZE, wordsize);
ptrto->encode(encoder);
parent->encodeRef(encoder);
encoder.openElement(ELEM_OFF);

22
Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/sleigh/SleighLanguage.java
View File

@ -809,8 +809,8 @@ public class SleighLanguage implements Language {
boolean isEntry = SpecXmlUtils.decodeBoolean(symbol.getAttribute("entry"));
Address startAddress = addressFactory.getAddress(addressString);
int rangeSize = SpecXmlUtils.decodeInt(symbol.getAttribute("size"));
Boolean isVolatile = SpecXmlUtils.decodeNullableBoolean(
symbol.getAttribute("volatile"));
Boolean isVolatile =
SpecXmlUtils.decodeNullableBoolean(symbol.getAttribute("volatile"));
if (startAddress == null) {
Msg.error(this, "invalid symbol address \"" + addressString + "\": " +
description.getSpecFile());
@ -820,8 +820,10 @@ public class SleighLanguage implements Language {
try {
info = new AddressLabelInfo(startAddress, rangeSize, labelName, false,
isEntry, type, isVolatile);
} catch (AddressOverflowException e) {
throw new XmlParseException("invalid symbol definition: " + labelName, e);
}
catch (AddressOverflowException e) {
throw new XmlParseException("invalid symbol definition: " + labelName,
e);
}
defaultSymbols.add(info);
if (isVolatile != null) {
@ -831,7 +833,8 @@ public class SleighLanguage implements Language {
volatileSymbolAddresses = new AddressSet();
}
volatileSymbolAddresses.addRange(startAddress, endAddress);
} else {
}
else {
if (nonVolatileSymbolAddresses == null) {
nonVolatileSymbolAddresses = new AddressSet();
}
@ -896,7 +899,8 @@ public class SleighLanguage implements Language {
read(parser);
}
catch (XmlParseException e) {
Msg.error(this, "Failed to parse Sleigh Specification ("+ specFile.getName() + "): " + e.getMessage());
Msg.error(this, "Failed to parse Sleigh Specification (" + specFile.getName() + "): " +
e.getMessage());
}
finally {
parser.dispose();
@ -1454,8 +1458,7 @@ public class SleighLanguage implements Language {
encoder.writeBool(ATTRIB_BIGENDIAN, isBigEndian());
encoder.writeUnsignedInteger(ATTRIB_UNIQBASE, uniqueOffset);
encoder.openElement(ELEM_SPACES);
encoder.writeString(ATTRIB_DEFAULTSPACE,
factory.getDefaultAddressSpace().getName());
encoder.writeString(ATTRIB_DEFAULTSPACE, factory.getDefaultAddressSpace().getName());
ElementId tag;
int delay;
@ -1511,8 +1514,7 @@ public class SleighLanguage implements Language {
encoder.writeSignedInteger(ATTRIB_SIZE, bytesize);
if (element.getAddressableUnitSize() > 1) {
encoder.writeSignedInteger(ATTRIB_WORDSIZE,
element.getAddressableUnitSize());
encoder.writeUnsignedInteger(ATTRIB_WORDSIZE, element.getAddressableUnitSize());
}
encoder.writeBool(ATTRIB_BIGENDIAN, isBigEndian());

20
Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/pcode/LocalSymbolMap.java
View File

@ -26,6 +26,7 @@ import ghidra.program.model.data.DataType;
import ghidra.program.model.data.Undefined;
import ghidra.program.model.listing.*;
import ghidra.program.model.symbol.*;
import ghidra.util.Msg;
import ghidra.util.SystemUtilities;
/**
@ -576,12 +577,23 @@ public class LocalSymbolMap {
}
public MappedVarKey(VariableStorage store, Address pcad) {
addr = store.getFirstVarnode().getAddress();
Varnode first = store.getFirstVarnode();
if (first != null) {
addr = first.getAddress();
if (!addr.isStackAddress()) {
// first use not supported for stack
pcaddr = pcad;
}
}
else {
// Hack: first can come back as null if something has gone wrong, such as a
// spacebase without a range.
Msg.warn(this, "First use is null, possible spacebase/global range issue." +
"There will be variable rename issues");
pcaddr = pcad;
}
}
@Override
public boolean equals(Object op2) {
@ -589,12 +601,14 @@ public class LocalSymbolMap {
if (!SystemUtilities.isEqual(pcaddr, op.pcaddr)) {
return false;
}
return addr.equals(op.addr);
return SystemUtilities.isEqual(addr, op.addr);
}
@Override
public int hashCode() {
int hash1 = addr.hashCode();
// Hack: addr should not be null, but can be if something in decompiler went wrong
// most likely a spacebase without a corresponding global register range entry
int hash1 = addr != null ? addr.hashCode() : 0;
int hash2 = pcaddr != null ? pcaddr.hashCode() : 0;
return (hash1 << 4) ^ hash2;
}

4
Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/pcode/PcodeDataTypeManager.java
View File

@ -333,7 +333,7 @@ public class PcodeDataTypeManager {
}
encoder.writeSignedInteger(ATTRIB_SIZE, ptrLen);
if (pointerWordSize != 1) {
encoder.writeSignedInteger(ATTRIB_WORDSIZE, pointerWordSize);
encoder.writeUnsignedInteger(ATTRIB_WORDSIZE, pointerWordSize);
}
if (spc != null) {
encoder.writeSpace(ATTRIB_SPACE, spc);
@ -398,7 +398,7 @@ public class PcodeDataTypeManager {
encodeNameIdAttributes(encoder, type);
encoder.writeSignedInteger(ATTRIB_SIZE, pointer.getLength());
if (pointerWordSize != 1) {
encoder.writeSignedInteger(ATTRIB_WORDSIZE, pointerWordSize);
encoder.writeUnsignedInteger(ATTRIB_WORDSIZE, pointerWordSize);
}
if (space != null) {
encoder.writeSpace(ATTRIB_SPACE, space);

38
Ghidra/Processors/ARM/data/languages/ARM.ldefs
View File

@ -5,7 +5,7 @@
endian="little"
size="32"
variant="v8"
version="1.106"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@ -29,7 +29,7 @@
endian="little"
size="32"
variant="v8T"
version="1.106"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
@ -49,7 +49,7 @@
instructionEndian="little"
size="32"
variant="v8LEInstruction"
version="1.106"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@ -64,7 +64,7 @@
endian="big"
size="32"
variant="v8"
version="1.106"
version="1.107"
slafile="ARM8_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@ -87,7 +87,7 @@
endian="big"
size="32"
variant="v8T"
version="1.106"
version="1.107"
slafile="ARM8_be.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
@ -104,7 +104,7 @@
endian="little"
size="32"
variant="v7"
version="1.106"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@ -124,7 +124,7 @@
instructionEndian="little"
size="32"
variant="v7LEInstruction"
version="1.106"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@ -139,7 +139,7 @@
endian="big"
size="32"
variant="v7"
version="1.106"
version="1.107"
slafile="ARM7_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@ -157,7 +157,7 @@
endian="little"
size="32"
variant="Cortex"
version="1.106"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
@ -177,7 +177,7 @@
endian="big"
size="32"
variant="Cortex"
version="1.106"
version="1.107"
slafile="ARM7_be.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
@ -196,7 +196,7 @@
endian="little"
size="32"
variant="v6"
version="1.106"
version="1.107"
slafile="ARM6_le.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
@ -216,7 +216,7 @@
endian="big"
size="32"
variant="v6"
version="1.106"
version="1.107"
slafile="ARM6_be.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
@ -236,7 +236,7 @@
endian="little"
size="32"
variant="v5t"
version="1.106"
version="1.107"
slafile="ARM5t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@ -254,7 +254,7 @@
endian="big"
size="32"
variant="v5t"
version="1.106"
version="1.107"
slafile="ARM5t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@ -272,7 +272,7 @@
endian="little"
size="32"
variant="v5"
version="1.106"
version="1.107"
slafile="ARM5_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@ -304,7 +304,7 @@
endian="little"
size="32"
variant="v4t"
version="1.106"
version="1.107"
slafile="ARM4t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@ -321,7 +321,7 @@
endian="big"
size="32"
variant="v4t"
version="1.106"
version="1.107"
slafile="ARM4t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@ -338,7 +338,7 @@
endian="little"
size="32"
variant="v4"
version="1.106"
version="1.107"
slafile="ARM4_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@ -358,7 +358,7 @@
endian="big"
size="32"
variant="v4"
version="1.106"
version="1.107"
slafile="ARM4_be.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"

240
Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
View File

@ -2114,6 +2114,22 @@ define pcodeop ExclusiveAccess;
Rt1215 = *tmp;
}
# overlaps patterns with the other ldr intructions when Rn==1111, therefore it must occur first
:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf85 & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
Rt1215 = PcrelOffset12:4;
build RtGotoCheck;
}
:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8d & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
Rt1215 = PcrelOffset12:4;
build RtGotoCheck;
}
:ldr^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8d; Rt1215 & RtGotoCheck) & RnIndirect12
{
@ -2131,23 +2147,6 @@ define pcodeop ExclusiveAccess;
build RtGotoCheck;
}
:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8d & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
Rt1215 = PcrelOffset12:4;
build RtGotoCheck;
}
# overlaps pattern with next ldr intruction, must occur first
:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf85 & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
Rt1215 = PcrelOffset12:4;
build RtGotoCheck;
}
:ldr^ItCond^".w" Rt1215,[Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & RtGotoCheck & thc1111=0 & sop0610=0 & thc0405=0 & Rm0003
{
build ItCond;
@ -2164,6 +2163,23 @@ define pcodeop ExclusiveAccess;
build RtGotoCheck;
}
:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf81 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = zext(tmp);
}
# overlaps patterns with the other ldrb intructions when Rn==1111, therefore it must occur first
:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf89 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = zext(tmp);
}
:ldrb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf89; Rt1215) & RnIndirect12
{
build ItCond;
@ -2180,21 +2196,6 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(tmp);
}
:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf89 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = zext(tmp);
}
:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf81 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = zext(tmp);
}
:ldrb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003
{
build ItCond;
@ -2203,6 +2204,7 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(val);
}
:ldrbt^ItCond^".w" Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc0811=14 & Immed8
{
build ItCond;
@ -2211,6 +2213,17 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(val);
}
# overlaps patterns with the other ldrd intructions when Rn==1111, therefore it must occur first
:ldrd^ItCond Rt1215,Rt0811,Pcrel8_s8 is TMode=1 & ItCond & op9=0x74 & thc0606=1 & thc0404=1 & sop0003=15; Rt1215 & Rt0811 & Pcrel8_s8
{
build ItCond;
build Pcrel8_s8;
local val = Pcrel8_s8;
Rt1215 = val(4);
Rt0811 = val(0);
}
:ldrd^ItCond Rt1215,Rt0811,RnIndirectPUW1 is TMode=1 & ItCond & (op9=0x74 & thc0606=1 & thc0404=1 & Rn0003; Rt1215 & Rt0811) & $(RN_INDIRECT_PUW1)
{
build ItCond;
@ -2219,13 +2232,42 @@ define pcodeop ExclusiveAccess;
Rt0811 = *(RnIndirectPUW1+4);
}
:ldrd^ItCond Rt1215,Rt0811,Pcrel8_s8 is TMode=1 & ItCond & op9=0x74 & thc0606=1 & thc0404=1 & sop0003=15; Rt1215 & Rt0811 & Pcrel8_s8
# pldw must come before ldrh.w because of overlap of Rt != 1111 in ldrh.w
:pldw^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op6=0x3e2 & thwbit=1 & thc0404=1 & Rn0003; op12=0xf & offset12
{
build ItCond;
build Pcrel8_s8;
local val = Pcrel8_s8;
Rt1215 = val(4);
Rt0811 = val(0);
addr:4 = Rn0003 + offset12;
HintPreloadDataForWrite(addr);
}
:pldw^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xfc & immed8
{
build ItCond;
addr:4 = Rn0003 - immed8;
HintPreloadDataForWrite(addr);
}
:pldw^ItCond Rn0003,Rm0003,"lsl #"^thc0405 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003
{
build ItCond;
addr:4 = Rn0003 + (Rm0003 << thc0405);
HintPreloadDataForWrite(addr);
}
# overlaps patterns with the other ldrh intructions when Rn==1111, therefore it must occur first
:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf83 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
local tmp = PcrelOffset12:2;
Rt1215 = zext(tmp);
}
:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8b & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:2 = PcrelOffset12:2;
Rt1215 = zext(tmp);
}
:ldrh.w^ItCond Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8B; Rt1215) & RnIndirect12
@ -2244,19 +2286,6 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(tmp);
}
:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf83 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
local tmp = PcrelOffset12:2;
Rt1215 = zext(tmp);
}
:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8b & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:2 = PcrelOffset12:2;
Rt1215 = zext(tmp);
}
:ldrh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf83 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003
{
build ItCond;
@ -2273,6 +2302,44 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(val);
}
# pli moevd above ldrsb to avoid conflict for ldrsb when Rt == 1111
:pli^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op4=0xf99 & Rn0003; op12=0xf & offset12
{
build ItCond;
addr:4 = Rn0003 + offset12;
HintPreloadInstruction(addr);
}
:pli^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op8=0xfc & immed8
{
build ItCond;
addr:4 = Rn0003 - immed8;
HintPreloadInstruction(addr);
}
:pli^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12
{
build ItCond;
HintPreloadInstruction(PcrelOffset12);
}
:pli^ItCond Rn0003,Rm0003"lsl #"^thc0405 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op6=0x3c0 & thc0405 & Rm0003
{
build ItCond;
addr:4 = Rn0003 + (Rm0003 << thc0405);
HintPreloadInstruction(addr);
}
# overlaps patterns with the other ldrsb intructions when Rn==1111, therefore it must occur first
:ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:1 = *PcrelOffset12;
Rt1215 = sext(tmp);
}
:ldrsb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12
{
build ItCond;
@ -2288,13 +2355,6 @@ define pcodeop ExclusiveAccess;
Rt1215 = sext(tmp);
}
:ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:1 = *PcrelOffset12;
Rt1215 = sext(tmp);
}
:ldrsb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf91 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003
{
build ItCond;
@ -2311,6 +2371,16 @@ define pcodeop ExclusiveAccess;
Rt1215 = sext(val);
}
# overlaps patterns with the other ldr intructions when Rn==1111, therefore it must occur first
:ldrsh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=1 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:2 = *PcrelOffset12;
Rt1215 = sext(tmp);
}
:ldrsh^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf9B; Rt1215) & RnIndirect12
{
build ItCond;
@ -2326,14 +2396,6 @@ define pcodeop ExclusiveAccess;
Rt1215 = sext(tmp);
}
:ldrsh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=1 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:2 = *PcrelOffset12;
Rt1215 = sext(tmp);
}
:ldrsh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf93 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003
{
build ItCond;
@ -3023,12 +3085,6 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; }
HintPreloadData(addr);
}
:pldw^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op6=0x3e2 & thwbit=1 & thc0404=1 & Rn0003; op12=0xf & offset12
{
build ItCond;
addr:4 = Rn0003 + offset12;
HintPreloadDataForWrite(addr);
}
:pld^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op6=0x3e0 & thwbit=0 & thc0404=1 & Rn0003; op8=0xfc & immed8
{
@ -3037,13 +3093,6 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; }
HintPreloadData(addr);
}
:pldw^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xfc & immed8
{
build ItCond;
addr:4 = Rn0003 - immed8;
HintPreloadDataForWrite(addr);
}
:pld^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf8 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12
{
build ItCond;
@ -3057,40 +3106,9 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; }
HintPreloadData(addr);
}
:pldw^ItCond Rn0003,Rm0003,"lsl #"^thc0405 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003
{
build ItCond;
addr:4 = Rn0003 + (Rm0003 << thc0405);
HintPreloadDataForWrite(addr);
}
# pld.w moved above ldrh to avoid conflicts
:pli^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op4=0xf99 & Rn0003; op12=0xf & offset12
{
build ItCond;
addr:4 = Rn0003 + offset12;
HintPreloadInstruction(addr);
}
:pli^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op8=0xfc & immed8
{
build ItCond;
addr:4 = Rn0003 - immed8;
HintPreloadInstruction(addr);
}
:pli^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12
{
build ItCond;
HintPreloadInstruction(PcrelOffset12);
}
:pli^ItCond Rn0003,Rm0003"lsl #"^thc0405 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op6=0x3c0 & thc0405 & Rm0003
{
build ItCond;
addr:4 = Rn0003 + (Rm0003 << thc0405);
HintPreloadInstruction(addr);
}
#pli moved above ldrsb
@endif # VERSION_6T2 || VERSION_7

2
Ghidra/Processors/MIPS/data/languages/mips32_fp64.cspec
View File

@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips32be.cspec
View File

@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips32be_eabi.cspec
View File

@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips32le.cspec
View File

@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips32le_eabi.cspec
View File

@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips64.cspec
View File

@ -14,9 +14,7 @@
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips64_32_n32.cspec
View File

@ -35,9 +35,7 @@
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips64_32_o32.cspec
View File

@ -40,9 +40,7 @@
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips64_32_o64.cspec
View File

@ -25,9 +25,7 @@
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

6
Ghidra/Processors/MIPS/src/main/java/ghidra/app/plugin/core/analysis/MipsAddressAnalyzer.java
View File

@ -477,6 +477,12 @@ public class MipsAddressAnalyzer extends ConstantPropagationAnalyzer {
coveredSet.add(func.getBody());
amgr.codeDefined(coveredSet);
}
else {
// else T9 was set at the beginning of the function
// something within the function must have set it to
// an unknown value, so can continue
return null;
}
}
catch (ContextChangeException e) {
throw new AssertException("Unexpected Exception", e);

1
Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec
View File

@ -20,7 +20,6 @@
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>

1
Ghidra/Processors/RISCV/data/languages/riscv32.cspec
View File

@ -18,7 +18,6 @@
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>

1
Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec
View File

@ -20,7 +20,6 @@
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>

1
Ghidra/Processors/RISCV/data/languages/riscv64.cspec
View File

@ -18,7 +18,6 @@
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>

8
Ghidra/Processors/tricore/data/languages/tricore.cspec
View File

@ -20,12 +20,12 @@
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="a0_" register="a0" space="ram"/>
<spacebase name="a1_" register="a1" space="ram"/>
<spacebase name="a8_" register="a8" space="ram"/>
<spacebase name="a9_" register="a9" space="ram"/>
<global>
<range space="ram"/>
<register name="a0"/>
<register name="a1"/>
<register name="a8"/>
<register name="a9"/>
</global>
<returnaddress>

8
Ghidra/Processors/tricore/data/languages/tricore.ldefs
View File

@ -6,7 +6,7 @@
endian="little"
size="32"
variant="default"
version="1.6"
version="1.7"
slafile="tricore.sla"
processorspec="tricore.pspec"
manualindexfile="../manuals/tricore2.idx"
@ -19,7 +19,7 @@
endian="little"
size="32"
variant="TC29x"
version="1.6"
version="1.7"
slafile="tricore.sla"
processorspec="tc29x.pspec"
manualindexfile="../manuals/tricore2.idx"
@ -32,7 +32,7 @@
endian="little"
size="32"
variant="TC172x"
version="1.3"
version="1.7"
slafile="tricore.sla"
processorspec="tc172x.pspec"
manualindexfile="../manuals/tricore.idx"
@ -45,7 +45,7 @@
endian="little"
size="32"
variant="TC176x"
version="1.3"
version="1.7"
slafile="tricore.sla"
processorspec="tc176x.pspec"
manualindexfile="../manuals/tricore.idx"

12
Ghidra/Processors/tricore/data/languages/tricore.sinc
View File

@ -2893,6 +2893,10 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
tmp[0,1] = 0;
goto [tmp];
}
:ji a11 is PCPMode=0 & op0811=11 & op0007=0xdc & op1215=0x0 & a11
{
return [a11];
}
@endif
@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
@ -2903,13 +2907,17 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
tmp[0,1] = 0;
goto [tmp];
}
:ji a11 is PCPMode=0 & op0811=11 & op0007=0x2d & op1215=0x0 & a11; op1631=0x30
{
return [a11];
}
@endif
# JL disp24 (B)
:jl off24pc is PCPMode=0 & ( op0007=0x5d ) ... & off24pc
{
#TODO is this just a call w/o context switching?
a11 = inst_start + 4;
a11 = inst_next;
call off24pc;
}
@ -2917,7 +2925,7 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
:jla off24abs is PCPMode=0 & ( op0007=0xdd ) ... & off24abs
{
#TODO is this just a call w/o context switching?
a11 = inst_start + 4;
a11 = inst_next;
call off24abs;
}