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GT-2880 More changes to ARM processor files
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ghizard
parent
6628bd3069
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651971c493
@ -9,6 +9,7 @@ data/languages/AARCH64.opinion||GHIDRA||||END|
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data/languages/AARCH64.pspec||GHIDRA||||END|
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data/languages/AARCH64.slaspec||GHIDRA||||END|
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data/languages/AARCH64BE.slaspec||GHIDRA||||END|
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data/languages/AARCH64_win.cspec||GHIDRA||||END|
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data/languages/AARCH64base.sinc||GHIDRA||||END|
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data/languages/AARCH64instructions.sinc||GHIDRA||||END|
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data/languages/AARCH64ldst.sinc||GHIDRA||||END|
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171
Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec
Normal file
171
Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec
Normal file
@ -0,0 +1,171 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<compiler_spec>
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<!-- Copied from AARCH.cspec and modified... See: https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019 -->
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<data_organization>
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<absolute_max_alignment value="0" />
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<machine_alignment value="4" />
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<default_alignment value="1" />
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<default_pointer_alignment value="4" />
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<pointer_size value="8" />
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<wchar_size value="2" />
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<short_size value="2" />
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<integer_size value="4" />
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<long_size value="4" />
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<long_long_size value="8" />
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<float_size value="4" />
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<double_size value="8" />
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<long_double_size value="8" />
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<size_alignment_map>
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<entry size="1" alignment="1" />
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<entry size="2" alignment="2" />
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<entry size="4" alignment="4" />
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<entry size="8" alignment="8" />
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</size_alignment_map>
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</data_organization>
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<global>
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<range space="ram"/>
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<range space="register" first="0x3000" last="0x3fff"/>
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</global>
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<stackpointer register="sp" space="ram"/>
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<funcptr align="4"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
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<prefersplit style="inhalf">
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<register name="q0"/>
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<register name="q1"/>
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<register name="q2"/>
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<register name="q3"/>
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<register name="q4"/>
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<register name="q5"/>
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<register name="q6"/>
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<register name="q7"/>
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<register name="q8"/>
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<register name="q9"/>
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<register name="q10"/>
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<register name="q11"/>
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<register name="q12"/>
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<register name="q13"/>
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<register name="q14"/>
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<register name="q15"/>
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<register name="q16"/>
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<register name="q17"/>
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<register name="q18"/>
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<register name="q19"/>
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<register name="q20"/>
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<register name="q21"/>
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<register name="q22"/>
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<register name="q23"/>
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<register name="q24"/>
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<register name="q25"/>
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<register name="q26"/>
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<register name="q27"/>
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<register name="q28"/>
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<register name="q29"/>
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<register name="q30"/>
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</prefersplit>
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<default_proto>
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<prototype name="__cdecl" extrapop="0" stackshift="0">
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<input>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="d0"/>
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</pentry>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="d1"/>
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</pentry>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="d2"/>
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</pentry>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="d3"/>
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</pentry>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="d4"/>
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</pentry>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="d5"/>
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</pentry>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="d6"/>
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</pentry>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="d7"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x0"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x1"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x2"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x3"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x4"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x5"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x6"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x7"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="4">
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<addr offset="0" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="8" metatype="float">
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<register name="q0"/>
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</pentry>
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<pentry minsize="1" maxsize="8" extension="zero">
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<register name="x0"/>
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</pentry>
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</output>
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<unaffected>
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<register name="x18"/>
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<register name="x19"/>
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<register name="x20"/>
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<register name="x21"/>
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<register name="x22"/>
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<register name="x23"/>
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<register name="x24"/>
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<register name="x25"/>
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<register name="x26"/>
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<register name="x27"/>
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<register name="x28"/>
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<register name="x29"/>
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<register name="x30"/>
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<register name="sp"/>
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</unaffected>
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<killedbycall>
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<register name="x1"/>
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<register name="x9"/>
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<register name="x10"/>
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<register name="x11"/>
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<register name="x12"/>
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<register name="x13"/>
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<register name="x14"/>
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<register name="x15"/>
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</killedbycall>
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</prototype>
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</default_proto>
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<callfixup name="PlaceHolderCallFixup"> <!-- This is here just to force call fixup and NoReturn fixup. Will be fixed in Ghidra V6.0 -->
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<target name="___NotARealFunctionName___"/>
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<pcode>
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<body><![CDATA[
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tmpptr:4 = 0;
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]]></body>
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</pcode>
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</callfixup>
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</compiler_spec>
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@ -17,20 +17,21 @@
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<external_name tool="IDA-PRO" name="arm"/>
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<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
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</language>
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<language processor="ARM"
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endian="big"
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instructionEndian="little"
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endian="little"
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size="32"
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variant="v8LEInstruction"
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variant="v8"
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version="1.102"
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slafile="ARM8_le.sla"
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processorspec="ARMt.pspec"
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manualindexfile="../manuals/ARM.idx"
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id="ARM:LEBE:32:v8LEInstruction">
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<description>Generic ARM/Thumb v8 little endian instructions and big endian data</description>
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id="ARM:LE:32:v8">
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<description>Generic ARM/Thumb v8 little endian</description>
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<compiler name="default" spec="ARM.cspec" id="default"/>
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<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
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<external_name tool="gnu" name="iwmmxt"/>
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<external_name tool="IDA-PRO" name="arm"/>
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<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
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</language>
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@ -67,22 +68,6 @@
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<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
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</language>
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<language processor="ARM"
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endian="big"
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instructionEndian="little"
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size="32"
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variant="v7LEInstruction"
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version="1.102"
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slafile="ARM7_le.sla"
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processorspec="ARMt.pspec"
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manualindexfile="../manuals/ARM.idx"
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id="ARM:LEBE:32:v7LEInstruction">
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<description>Generic ARM/Thumb v7 little endian instructions and big endian data</description>
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<compiler name="default" spec="ARM.cspec" id="default"/>
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<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
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<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
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</language>
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<language processor="ARM"
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endian="big"
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size="32"
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@ -1,18 +1,18 @@
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<opinions>
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<constraint loader="Portable Executable (PE)">
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<constraint compilerSpecID="windows">
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<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
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<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <!-- THUMB -->
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<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" /> <!-- THUMB -->
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<constraint primary="448" processor="ARM" endian="little" size="32" variant="v7" />
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<constraint primary="450" processor="ARM" endian="little" size="32" variant="v7" /> <!-- THUMB -->
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<constraint primary="452" processor="ARM" endian="little" size="32" variant="v7" /> <!-- THUMB -->
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</constraint>
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<constraint compilerSpecID="default">
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<constraint primary="2560" processor="ARM" endian="big" size="32" variant="v8" />
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</constraint>
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</constraint>
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<constraint loader="Debug Symbols (DBG)" compilerSpecID="windows">
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<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
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<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <!-- THUMB -->
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<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" /> <!-- THUMB -->
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<constraint primary="448" processor="ARM" endian="little" size="32" variant="v7" />
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<constraint primary="450" processor="ARM" endian="little" size="32" variant="v7" /> <!-- THUMB -->
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<constraint primary="452" processor="ARM" endian="little" size="32" variant="v7" /> <!-- THUMB -->
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</constraint>
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<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
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<constraint primary="40" processor="ARM" size="32" variant="v8" />
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@ -31,8 +31,8 @@
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<constraint primary="arm7" processor="ARM" endian="little" size="32" variant="v7" />
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</constraint>
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<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="windows">
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<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
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<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" />
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<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" />
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<constraint primary="448" processor="ARM" endian="little" size="32" variant="v7" />
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<constraint primary="450" processor="ARM" endian="little" size="32" variant="v7" />
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<constraint primary="452" processor="ARM" endian="little" size="32" variant="v7" />
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</constraint>
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</opinions>
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@ -23,9 +23,11 @@
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<entry size="8" alignment="8" />
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</size_alignment_map>
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</data_organization>
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<global>
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<range space="ram"/>
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</global>
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<stackpointer register="sp" space="ram"/>
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<funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
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@ -100,10 +102,16 @@
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<register name="d13"/>
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<register name="d14"/>
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<register name="d15"/>
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<!-- Do we need to say something about q0-q15 instead of d?... -->
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<register name="sp"/>
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</unaffected>
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<killedbycall>
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<!-- Maybe r0, r1, r2, r3, r12... was only r1 -->
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<register name="r0"/>
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<register name="r1"/>
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<register name="r2"/>
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<register name="r3"/>
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<register name="r12"/>
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<register name="d0"/>
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<register name="d1"/>
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<register name="d2"/>
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@ -112,6 +120,23 @@
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<register name="d5"/>
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<register name="d6"/>
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<register name="d7"/>
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<!-- Maybe d16-d31 -->
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<register name="d16"/>
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<register name="d17"/>
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<register name="d18"/>
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<register name="d19"/>
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<register name="d20"/>
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<register name="d21"/>
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<register name="d22"/>
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<register name="d23"/>
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<register name="d24"/>
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<register name="d25"/>
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<register name="d26"/>
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<register name="d27"/>
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<register name="d28"/>
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<register name="d29"/>
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<register name="d30"/>
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<register name="d31"/>
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</killedbycall>
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</prototype>
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</default_proto>
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