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GT-2880 More changes to ARM processor files

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This commit is contained in:
ghizard 2019-06-05 08:37:31 -04:00
parent 6628bd3069
commit 651971c493
5 changed files with 213 additions and 31 deletions
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1
Ghidra/Processors/AARCH64/certification.manifest
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@ -9,6 +9,7 @@ data/languages/AARCH64.opinion||GHIDRA||||END|
data/languages/AARCH64.pspec||GHIDRA||||END| data/languages/AARCH64.pspec||GHIDRA||||END|
data/languages/AARCH64.slaspec||GHIDRA||||END| data/languages/AARCH64.slaspec||GHIDRA||||END|
data/languages/AARCH64BE.slaspec||GHIDRA||||END| data/languages/AARCH64BE.slaspec||GHIDRA||||END|
data/languages/AARCH64_win.cspec||GHIDRA||||END|
data/languages/AARCH64base.sinc||GHIDRA||||END| data/languages/AARCH64base.sinc||GHIDRA||||END|
data/languages/AARCH64instructions.sinc||GHIDRA||||END| data/languages/AARCH64instructions.sinc||GHIDRA||||END|
data/languages/AARCH64ldst.sinc||GHIDRA||||END| data/languages/AARCH64ldst.sinc||GHIDRA||||END|

171
Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec Normal file
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@ -0,0 +1,171 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<!-- Copied from AARCH.cspec and modified... See: https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019 -->
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="8" />
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
<range space="register" first="0x3000" last="0x3fff"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="4"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<prefersplit style="inhalf">
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
<register name="q16"/>
<register name="q17"/>
<register name="q18"/>
<register name="q19"/>
<register name="q20"/>
<register name="q21"/>
<register name="q22"/>
<register name="q23"/>
<register name="q24"/>
<register name="q25"/>
<register name="q26"/>
<register name="q27"/>
<register name="q28"/>
<register name="q29"/>
<register name="q30"/>
</prefersplit>
<default_proto>
<prototype name="__cdecl" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d1"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d2"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d3"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d4"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d5"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d6"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d7"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x1"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x2"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x3"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x4"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x5"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x6"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="q0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
</output>
<unaffected>
<register name="x18"/>
<register name="x19"/>
<register name="x20"/>
<register name="x21"/>
<register name="x22"/>
<register name="x23"/>
<register name="x24"/>
<register name="x25"/>
<register name="x26"/>
<register name="x27"/>
<register name="x28"/>
<register name="x29"/>
<register name="x30"/>
<register name="sp"/>
</unaffected>
<killedbycall>
<register name="x1"/>
<register name="x9"/>
<register name="x10"/>
<register name="x11"/>
<register name="x12"/>
<register name="x13"/>
<register name="x14"/>
<register name="x15"/>
</killedbycall>
</prototype>
</default_proto>
<callfixup name="PlaceHolderCallFixup"> <!-- This is here just to force call fixup and NoReturn fixup. Will be fixed in Ghidra V6.0 -->
<target name="___NotARealFunctionName___"/>
<pcode>
<body><![CDATA[
tmpptr:4 = 0;
]]></body>
</pcode>
</callfixup>
</compiler_spec>

29
Ghidra/Processors/ARM/data/languages/ARM.ldefs
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@ -17,20 +17,21 @@
<external_name tool="IDA-PRO" name="arm"/> <external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/> <external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language> </language>
<language processor="ARM" <language processor="ARM"
endian="big" endian="little"
instructionEndian="little"
size="32" size="32"
variant="v8LEInstruction" variant="v8"
version="1.102" version="1.102"
slafile="ARM8_le.sla" slafile="ARM8_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
id="ARM:LEBE:32:v8LEInstruction"> id="ARM:LE:32:v8">
<description>Generic ARM/Thumb v8 little endian instructions and big endian data</description> <description>Generic ARM/Thumb v8 little endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/> <compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/> <compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/> <external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language> </language>
@ -67,22 +68,6 @@
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/> <external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language> </language>
<language processor="ARM"
endian="big"
instructionEndian="little"
size="32"
variant="v7LEInstruction"
version="1.102"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LEBE:32:v7LEInstruction">
<description>Generic ARM/Thumb v7 little endian instructions and big endian data</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM" <language processor="ARM"
endian="big" endian="big"
size="32" size="32"

18
Ghidra/Processors/ARM/data/languages/ARM.opinion
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@ -1,18 +1,18 @@
<opinions> <opinions>
<constraint loader="Portable Executable (PE)"> <constraint loader="Portable Executable (PE)">
<constraint compilerSpecID="windows"> <constraint compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" /> <constraint primary="448" processor="ARM" endian="little" size="32" variant="v7" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <!-- THUMB --> <constraint primary="450" processor="ARM" endian="little" size="32" variant="v7" /> <!-- THUMB -->
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" /> <!-- THUMB --> <constraint primary="452" processor="ARM" endian="little" size="32" variant="v7" /> <!-- THUMB -->
</constraint> </constraint>
<constraint compilerSpecID="default"> <constraint compilerSpecID="default">
<constraint primary="2560" processor="ARM" endian="big" size="32" variant="v8" /> <constraint primary="2560" processor="ARM" endian="big" size="32" variant="v8" />
</constraint> </constraint>
</constraint> </constraint>
<constraint loader="Debug Symbols (DBG)" compilerSpecID="windows"> <constraint loader="Debug Symbols (DBG)" compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" /> <constraint primary="448" processor="ARM" endian="little" size="32" variant="v7" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <!-- THUMB --> <constraint primary="450" processor="ARM" endian="little" size="32" variant="v7" /> <!-- THUMB -->
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" /> <!-- THUMB --> <constraint primary="452" processor="ARM" endian="little" size="32" variant="v7" /> <!-- THUMB -->
</constraint> </constraint>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default"> <constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="40" processor="ARM" size="32" variant="v8" /> <constraint primary="40" processor="ARM" size="32" variant="v8" />
@ -31,8 +31,8 @@
<constraint primary="arm7" processor="ARM" endian="little" size="32" variant="v7" /> <constraint primary="arm7" processor="ARM" endian="little" size="32" variant="v7" />
</constraint> </constraint>
<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="windows"> <constraint loader="MS Common Object File Format (COFF)" compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" /> <constraint primary="448" processor="ARM" endian="little" size="32" variant="v7" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <constraint primary="450" processor="ARM" endian="little" size="32" variant="v7" />
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" /> <constraint primary="452" processor="ARM" endian="little" size="32" variant="v7" />
</constraint> </constraint>
</opinions> </opinions>

25
Ghidra/Processors/ARM/data/languages/ARM_win.cspec
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@ -23,9 +23,11 @@
<entry size="8" alignment="8" /> <entry size="8" alignment="8" />
</size_alignment_map> </size_alignment_map>
</data_organization> </data_organization>
<global> <global>
<range space="ram"/> <range space="ram"/>
</global> </global>
<stackpointer register="sp" space="ram"/> <stackpointer register="sp" space="ram"/>
<funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff --> <funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
@ -100,10 +102,16 @@
<register name="d13"/> <register name="d13"/>
<register name="d14"/> <register name="d14"/>
<register name="d15"/> <register name="d15"/>
<!-- Do we need to say something about q0-q15 instead of d?... -->
<register name="sp"/> <register name="sp"/>
</unaffected> </unaffected>
<killedbycall> <killedbycall>
<!-- Maybe r0, r1, r2, r3, r12... was only r1 -->
<register name="r0"/>
<register name="r1"/> <register name="r1"/>
<register name="r2"/>
<register name="r3"/>
<register name="r12"/>
<register name="d0"/> <register name="d0"/>
<register name="d1"/> <register name="d1"/>
<register name="d2"/> <register name="d2"/>
@ -112,6 +120,23 @@
<register name="d5"/> <register name="d5"/>
<register name="d6"/> <register name="d6"/>
<register name="d7"/> <register name="d7"/>
<!-- Maybe d16-d31 -->
<register name="d16"/>
<register name="d17"/>
<register name="d18"/>
<register name="d19"/>
<register name="d20"/>
<register name="d21"/>
<register name="d22"/>
<register name="d23"/>
<register name="d24"/>
<register name="d25"/>
<register name="d26"/>
<register name="d27"/>
<register name="d28"/>
<register name="d29"/>
<register name="d30"/>
<register name="d31"/>
</killedbycall> </killedbycall>
</prototype> </prototype>
</default_proto> </default_proto>