diff --git a/Ghidra/Processors/V850E2M/Module.manifest b/Ghidra/Processors/V850/Module.manifest similarity index 100% rename from Ghidra/Processors/V850E2M/Module.manifest rename to Ghidra/Processors/V850/Module.manifest diff --git a/Ghidra/Processors/V850/build.gradle b/Ghidra/Processors/V850/build.gradle new file mode 100644 index 0000000000..db5ae379d3 --- /dev/null +++ b/Ghidra/Processors/V850/build.gradle @@ -0,0 +1,7 @@ +apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" +apply from: "$rootProject.projectDir/gradle/javaProject.gradle" +apply from: "$rootProject.projectDir/gradle/processorProject.gradle" +apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle" +apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle" +apply plugin: 'eclipse' +eclipse.project.name = 'Processors v850' \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/certification.manifest b/Ghidra/Processors/V850/certification.manifest similarity index 85% rename from Ghidra/Processors/V850E2M/certification.manifest rename to Ghidra/Processors/V850/certification.manifest index 6234d7435a..ed4cb836fd 100644 --- a/Ghidra/Processors/V850E2M/certification.manifest +++ b/Ghidra/Processors/V850/certification.manifest @@ -1,10 +1,10 @@ ##VERSION: 2.0 Module.manifest||GHIDRA||||END| build.gradle||GHIDRA||||END| -data/languages/V850E2M.cspec||GHIDRA||||END| -data/languages/V850E2M.ldefs||GHIDRA||||END| -data/languages/V850E2M.pspec||GHIDRA||||END| -data/languages/V850E2M.slaspec||GHIDRA||||END| +data/languages/V850.cspec||GHIDRA||||END| +data/languages/V850.ldefs||GHIDRA||||END| +data/languages/V850.pspec||GHIDRA||||END| +data/languages/V850.slaspec||GHIDRA||||END| data/languages/Helpers/Conditions.sinc||GHIDRA||||END| data/languages/Helpers/Extras.sinc||GHIDRA||||END| data/languages/Helpers/Macros.sinc||GHIDRA||||END| diff --git a/Ghidra/Processors/V850E2M/data/languages/Helpers/Conditions.sinc b/Ghidra/Processors/V850/data/languages/Helpers/Conditions.sinc similarity index 94% rename from Ghidra/Processors/V850E2M/data/languages/Helpers/Conditions.sinc rename to Ghidra/Processors/V850/data/languages/Helpers/Conditions.sinc index 16ba1a09b2..c7e9a07de8 100644 --- a/Ghidra/Processors/V850E2M/data/languages/Helpers/Conditions.sinc +++ b/Ghidra/Processors/V850/data/languages/Helpers/Conditions.sinc @@ -13,7 +13,7 @@ c0003: "nh" is op0003=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; } c0003: "h" is op0003=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; } c0003: "n" is op0003=0x4 { tmp:1 = ($(S)) == 1; export tmp; } c0003: "p" is op0003=0xC { tmp:1 = ($(S)) == 0; export tmp; } -c0003: "r" is op0003=0x5 { tmp:1 = 1; export tmp; } +c0003: "t" is op0003=0x5 { tmp:1 = 1; export tmp; } c0003: "sa" is op0003=0xD { tmp:1 = ($(SAT)) == 1; export tmp; } c0003: "lt" is op0003=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; } c0003: "ge" is op0003=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; } @@ -30,7 +30,7 @@ c1720: "nh" is op1720=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; } c1720: "h" is op1720=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; } c1720: "n" is op1720=0x4 { tmp:1 = ($(S)) == 1; export tmp; } c1720: "p" is op1720=0xC { tmp:1 = ($(S)) == 0; export tmp; } -c1720: "r" is op1720=0x5 { tmp:1 = 1; export tmp; } +c1720: "t" is op1720=0x5 { tmp:1 = 1; export tmp; } c1720: "sa" is op1720=0xD { tmp:1 = ($(SAT)) == 1; export tmp; } c1720: "lt" is op1720=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; } c1720: "ge" is op1720=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; } diff --git a/Ghidra/Processors/V850E2M/data/languages/Helpers/Extras.sinc b/Ghidra/Processors/V850/data/languages/Helpers/Extras.sinc similarity index 97% rename from Ghidra/Processors/V850E2M/data/languages/Helpers/Extras.sinc rename to Ghidra/Processors/V850/data/languages/Helpers/Extras.sinc index dbfdde0841..9d78e038fd 100644 --- a/Ghidra/Processors/V850E2M/data/languages/Helpers/Extras.sinc +++ b/Ghidra/Processors/V850/data/languages/Helpers/Extras.sinc @@ -84,7 +84,7 @@ PrepList30: PrepList29 is prep00=0 & PrepList29 { } PrepList: { lp } is prep21=1 & prep2431=0 & prep2223=0 & prep00=0 & lp { push(lp); } PrepList: { PrepList30,lp } is prep21=1 & PrepList30 & lp { push(lp); } -PrepList: { PrepList30 } is prep21=0 & PrepList30 { push(lp); } +PrepList: { PrepList30 } is prep21=0 & PrepList30 { } @@ -122,4 +122,4 @@ DispList21: r21,DispList22 is DispList22 & prep26=1 & r21 { pop(r21); } DispList21: DispList22 is DispList22 & prep26=0 { } DispList: { r20,DispList21 } is DispList21 & prep27=1 & r20 { pop(r20); } -DispList: { DispList21 } is DispList21 & prep27=0 { pop(r20); } \ No newline at end of file +DispList: { DispList21 } is DispList21 & prep27=0 { } \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Helpers/Macros.sinc b/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc similarity index 73% rename from Ghidra/Processors/V850E2M/data/languages/Helpers/Macros.sinc rename to Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc index 5fdfc4e58d..6c22719974 100644 --- a/Ghidra/Processors/V850E2M/data/languages/Helpers/Macros.sinc +++ b/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc @@ -120,55 +120,61 @@ macro set_OV0_S_Z(var) ##### General-Macros ##### -macro either_or(res, cond, var_true, var_false) # if condition is != 0 +macro either_or(res, cond, true, false) # if condition is != 0 { - if (cond != 0) - goto ; - - res = var_false; - goto ; - - - res = var_true; - - + res = (true * zext(cond != 0)) + (false * zext(cond == 0)); } -macro either_or1(res, cond, var_true, var_false) # if condition is == 1 +macro either_or1(res, cond, true, false) # if condition is == 1 { - if (cond == 1) - goto ; - - res = var_false; - goto ; - - - res = var_true; - - + res = (true * zext(cond == 1)) + (false * zext(cond != 1)); } -macro shift_right_logic(res, var, shift) +macro shift_right_logic(res, var, shift_) { + local shift = (shift_ & 0x1f); + local mask = 0; + + if(shift == 0) + goto ; + + mask = var & (1 << (shift - 1)); res = var >> shift; + + set_OV0_S_Z(res); - local mask = var & (1 << (shift - 1)); $(CY) = ((mask != 0) && (shift != 0)); } -macro shift_right_arith(res, var, shift) +macro shift_right_arith(res, var, shift_) { + local shift = (shift_ & 0x1f); + local mask = 0; + + if(shift == 0) + goto ; + + mask = var & (1 << (shift - 1)); res = var s>> shift; + + set_OV0_S_Z(res); - local mask = var & (1 << (shift - 1)); $(CY) = ((mask != 0) && (shift != 0)); } -macro shift_left_logic(res, var, shift) +macro shift_left_logic(res, var, shift_) { + local shift = (shift_ & 0x1f); + local mask = 0; + + if(shift == 0) + goto ; + res = var << shift; + mask = var & (1 << (32 - shift)); + + set_OV0_S_Z(res); - local mask = var & (1 << (32 - shift)); $(CY) = ((mask != 0) && (shift != 0)); } @@ -232,26 +238,26 @@ macro SearchLeft(res, var, char) } -macro saturate(var) -{ - if (var s> 0x7FFFFFFF) - goto ; +# macro saturate(var) +# { +# if (var s> 0x7FFFFFFF) +# goto ; - if (var s< -0x80000000) - goto ; +# if (var s< -0x80000000) +# goto ; - goto ; +# goto ; - - var = 0x7FFFFFFF; - goto ; +# +# var = 0x7FFFFFFF; +# goto ; - - var = -0x80000000; - goto ; +# +# var = -0x80000000; +# goto ; - -} +# +# } ##### Float-Macros ##### diff --git a/Ghidra/Processors/V850E2M/data/languages/Helpers/Register.sinc b/Ghidra/Processors/V850/data/languages/Helpers/Register.sinc similarity index 91% rename from Ghidra/Processors/V850E2M/data/languages/Helpers/Register.sinc rename to Ghidra/Processors/V850/data/languages/Helpers/Register.sinc index 599aed893c..f8b5c5ab81 100644 --- a/Ghidra/Processors/V850E2M/data/languages/Helpers/Register.sinc +++ b/Ghidra/Processors/V850/data/languages/Helpers/Register.sinc @@ -27,7 +27,7 @@ define register offset=0x80 size=0x4 # offset = 0x80(128) = PreOffset define register offset=0x0 size=0x8 [ - r0r1 r2sp _ r6r7 r8r9 + r0r1 r2sp r4r5 r6r7 r8r9 r10r11 r12r13 r14r15 r16r17 r18r19 r20r21 r22r23 r24r25 r26r27 r28r29 _ diff --git a/Ghidra/Processors/V850E2M/data/languages/Helpers/Tokens.sinc b/Ghidra/Processors/V850/data/languages/Helpers/Tokens.sinc similarity index 96% rename from Ghidra/Processors/V850E2M/data/languages/Helpers/Tokens.sinc rename to Ghidra/Processors/V850/data/languages/Helpers/Tokens.sinc index 5552dce722..6a009352eb 100644 --- a/Ghidra/Processors/V850E2M/data/languages/Helpers/Tokens.sinc +++ b/Ghidra/Processors/V850/data/languages/Helpers/Tokens.sinc @@ -7,7 +7,6 @@ define token instr(16) op0000 = (0,0) op0003 = (0,3) op0004 = (0,4) - r0004 = (0,4) _R0004 = (0,4) SR0004 = (0,4) R0004x2 = (0,4) @@ -29,7 +28,6 @@ define token instr(16) op1113 = (11,13) op1114 = (11,14) op1115 = (11,15) - r1115 = (11,15) _R1115 = (11,15) SR1115 = (11,15) R1115x2 = (11,15) @@ -43,7 +41,6 @@ define token instr2(16) op1617 = (0,1) op1619 = (0,3) op1620 = (0,4) - r1620 = (0,4) R1620 = (0,4) R1620x2 = (0,4) op1626 = (0,10) @@ -87,7 +84,6 @@ define token prep(32) prep0105 = (1,5) prep0615 = (6,15) prep1620 = (16,20) - prep1620r = (16,20) prep21 = (21,21) prep22 = (22,22) prep2223 = (22,31) diff --git a/Ghidra/Processors/V850E2M/data/languages/Helpers/Variables.sinc b/Ghidra/Processors/V850/data/languages/Helpers/Variables.sinc similarity index 79% rename from Ghidra/Processors/V850E2M/data/languages/Helpers/Variables.sinc rename to Ghidra/Processors/V850/data/languages/Helpers/Variables.sinc index 6bb7bb96a0..bd15f2d8bd 100644 --- a/Ghidra/Processors/V850E2M/data/languages/Helpers/Variables.sinc +++ b/Ghidra/Processors/V850/data/languages/Helpers/Variables.sinc @@ -3,7 +3,7 @@ ##################################################### -attach variables [ _R0004 _R1115 _R2731 ] +attach variables [ _R0004 _R1115 _R2731 R1620 prep1620] [ r0 r1 r2 sp gp tp r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 @@ -11,17 +11,9 @@ attach variables [ _R0004 _R1115 _R2731 ] ep lp ]; -attach variables [ r0004 r1115 r1620 prep1620r ] -[ - _ r1 r2 sp gp tp r6 r7 r8 r9 - r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 - r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 - ep lp -]; - attach variables [ R0004x2 R1115x2 R1620x2 R2731x2 ] [ - r0r1 _ r2sp _ _ _ r6r7 _ r8r9 _ + r0r1 _ r2sp _ r4r5 _ r6r7 _ r8r9 _ r10r11 _ r12r13 _ r14r15 _ r16r17 _ r18r19 _ r20r21 _ r22r23 _ r24r25 _ r26r27 _ r28r29 _ _ _ diff --git a/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc b/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc new file mode 100644 index 0000000000..7cf8e85d73 --- /dev/null +++ b/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc @@ -0,0 +1,336 @@ +# (3) Multiply instructions +# (4) Multiply-accumulate instructions +# (5) Arithmetic instructions +# (7) Saturated operation instructions +# (11) Divide instructions +# (12) High-speed divide instructions + + + +##################################################### +##### Multiply ##### +##################################################### + + +# MUL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100000 +:mul R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x220 & R2731 +{ + local res:8 = sext(R1115) * sext(R0004); + R1115 = res:4; + R2731 = res[32,32]; +} + +# MUL imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII00 +:mul imm9, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2226=0x9 & op1617=0x0 & s1821 & R2731 +[ imm9 = (s1821 << 5) | s0004; ] +{ + local res:8 = sext(R1115) * imm9; + R1115 = res:4; + R2731 = res[32,32]; +} + +# MULH reg1, reg2 - rrrrr000111RRRRR +:mulh R0004, R1115 is op0510=0x07 & R0004 & R1115 & op1115!=0 +{ + R1115 = sext(R1115:2) * sext(R0004:2); +} + +# MULH imm5, reg2 - rrrrr010111iiiii +:mulh s0004, R1115 is op0510=0x17 & s0004 & R1115 +{ + R1115 = sext(R1115:2) * s0004; +} + +# MULHI imm16, reg1, reg2 - rrrrr110111RRRRR|iiiiiiiiiiiiiiii +:mulhi s1631, R0004, R1115 is op0510=0x37 & R1115 & R0004; s1631 +{ + R1115 = R0004 * s1631; +} + +# MULU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100010 +:mulu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x222 & R2731 +{ + local res:8 = zext(R1115) * zext(R0004); + R1115 = res:4; + R2731 = res[32,32]; +} + +# MULU imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII10 +:mulu imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x2 & op1821 & R2731 +[ imm9 = (op1821 << 5) | op0004; ] +{ + local res:8 = zext(R1115) * imm9; + R1115 = res:4; + R2731 = res[32,32]; +} + + + +##################################################### +##### MultiplyAccumulate ##### +##################################################### + + +# MAC reg1, reg2, reg3, reg4 - rrrrr111111RRRRR wwww0011110mmmm0 +:mac R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1E & op1616=0 & R1620x2 & R2731x2 +{ + R1620x2 = sext(R1115) * sext(R0004) + R2731x2; +} + +# MACU reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwww0011111mmmm0 +:macu R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1F & op1616=0 & R1620x2 & R2731x2 +{ + R1620x2 = zext(R1115) * zext(R0004) + R2731x2; +} + + + +##################################################### +##### Arithmetic ##### +##################################################### + + +# ADD reg1, reg2 - rrrrr001110RRRRR +:add R0004, R1115 is op0510=0x0E & R0004 & R1115 +{ + set_general_flags_pos(R0004, R1115); + R1115 = R1115 + R0004; +} + +# ADD imm5, reg2 - rrrrr010010iiiii +:add s0004, R1115 is op0510=0x12 & s0004 & R1115 +{ + set_general_flags_pos(s0004, R1115); + R1115 = R1115 + s0004; +} + +# ADDI imm16, reg1, reg2 - rrrrr110000RRRRR|iiiiiiiiiiiiiiii +:addi s1631, R0004, R1115 is op0510=0x30 & R1115 & R0004; s1631 +{ + set_general_flags_pos(R0004, s1631); + R1115 = R0004 + s1631; +} + +# CMP reg1, reg2 - rrrrr001111RRRRR +:cmp R0004, R1115 is op0510=0x0F & R0004 & R1115 +{ + set_general_flags_neg(R1115, R0004); +} + +# CMP imm5, reg2 - rrrrr010011iiiii +:cmp s0004, R1115 is op0510=0x13 & s0004 & R1115 +{ + set_general_flags_neg(R1115, s0004); +} + +# MOV reg1, reg2 - rrrrr000000RRRRR +:mov R0004, R1115 is op0510=0x00 & R0004 & R1115 +{ + R1115 = R0004; +} + +# MOV imm5, reg2 - rrrrr010000iiiii +:mov s0004, R1115 is op0510=0x10 & s0004 & R1115 & op1115!=0 +{ + R1115 = s0004; +} + +# MOV imm32, reg1 - 00000110001RRRRR|iiiiiiiiiiiiiiii|IIIIIIIIIIIIIIII +:mov imm32, R0004 is op0515=0x031 & R0004; op1631; op3247 +[ imm32 = (op3247 << 16) | op1631; ] +{ + R0004 = imm32; +} + +# MOVEA imm16, reg1, reg2 - rrrrr110001RRRRR|iiiiiiiiiiiiiiii +:movea s1631, R0004, R1115 is op0510=0x31 & op1115!=0 & R0004 & R1115; s1631 +{ + R1115 = R0004 + s1631; +} + +# MOVHI imm16, reg1, reg2 - rrrrr110010RRRRR|iiiiiiiiiiiiiiii +:movhi s1631, R0004, R1115 is op0510=0x32 & op1115!=0 & R0004 & R1115; s1631 +{ + R1115 = R0004 + (s1631 << 16); +} + +# SUB reg1, reg2 - rrrrr001101RRRRR +:sub R0004, R1115 is op0510=0x0D & R0004 & R1115 +{ + set_general_flags_neg(R1115, R0004); + R1115 = R1115 - R0004; +} + +# SUBR reg1, reg2 - rrrrr001100RRRRR +:subr R0004, R1115 is op0510=0x0C & R0004 & R1115 +{ + set_general_flags_neg(R0004, R1115); + R1115 = R0004 - R1115; +} + + + +##################################################### +##### Saturated ##### +##################################################### + + +define pcodeop __saturate; + +# SATADD reg1, reg2 - rrrrr000110RRRRR +:satadd R0004, R1115 is op0510=0x06 & R0004 & R1115 & op1115!=0 +{ + set_general_flags_pos(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + R1115 = R1115 + R0004; + __saturate(R1115); +} + +#SATADD imm5, reg2 - rrrrr010001iiiii +:satadd s0004, R1115 is op0510=0x11 & s0004 & R1115 & op1115!=0 +{ + set_general_flags_pos(R1115, s0004); + $(SAT) = $(SAT) || $(OV); + R1115 = R1115 + s0004; + __saturate(R1115); +} + +# SATADD reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110111010 +:satadd R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x3BA & R2731 +{ + set_general_flags_pos(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + R2731 = R1115 + R0004; + __saturate(R2731); +} + +# SATSUB reg1, reg2 - rrrrr000101RRRRR +:satsub R0004, R1115 is op0510=0x05 & R0004 & R1115 & op1115!=0 +{ + set_general_flags_neg(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + R1115 = R1115 - R0004; + __saturate(R1115); +} + +# SATSUB reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110011010 +:satsub R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x39A & R2731 +{ + set_general_flags_neg(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + R2731 = R1115 - R0004; + __saturate(R2731); +} + +# SATSUBI imm16, reg1, reg2 +:satsubi s1631, R0004, R1115 is op0510=0x33 & op1115!=0 & R0004 & R1115; s1631 +{ + set_general_flags_neg(R0004, s1631); + $(SAT) = $(SAT) || $(OV); + R1115 = R0004 - s1631; + __saturate(R1115); +} + +# SATSUBR reg1, reg2 +:satsubr R0004, R1115 is op0510=0x04 & R0004 & R1115 & op1115!=0 +{ + set_general_flags_neg(R0004, R1115); + $(SAT) = $(SAT) || $(OV); + R1115 = R0004 - R1115; + __saturate(R1115); +} + + + +##################################################### +##### Divide ##### +##################################################### + + +# DIV reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000000 +:div R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C0 & R2731 +{ + local quot:4 = R1115 s/ R0004; + local mod:4 = R1115 s% R0004; + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + set_Z(R1115); + set_S(R1115); + either_or(R1115, (R1115 == R2731), mod, quot); #if reg2 == reg3 the remainder is stored, if not the quotient is stored + R2731 = mod; +} + +# DIVH reg1, reg2 - rrrrr000010RRRRR +:divh R0004, R1115 is op0510=0x02 & R0004 & R1115 +{ + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + R1115 = R1115 / R0004; + set_Z(R1115); + set_S(R1115); +} + +# DIVH reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000000 +:divh R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x280 & R2731 +{ + local quot:4 = sext(R1115:2 s/ R0004:2); + local mod:4 = sext(R1115:2 s% R0004:2); + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + set_Z(R1115); + set_S(R1115); + either_or(R1115, (R1115 == R2731), mod, quot); + R2731 = mod; +} + +# DIVHU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000010 +:divhu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x282 & R2731 +{ + local quot:4 = sext(R1115:2 / R0004:2); + local mod:4 = sext(R1115:2 % R0004:2); + $(OV) = (R0004 == 0); + set_Z(R1115); + set_S(R1115); + either_or(R1115, (R1115 == R2731), mod, quot); + R2731 = mod; +} + +# DIVU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000010 +:divu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C2 & R2731 +{ + local quot:4 = R1115 / R0004; + local mod:4 = R1115 % R0004; + $(OV) = (R0004 == 0); + set_Z(R1115); + set_S(R1115); + either_or(R1115, (R1115 == R2731), mod, quot); + R2731 = mod; +} + + + +##################################################### +##### HighSpeedDivide ##### +##################################################### + + +# DIVQ reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111100 +:divq R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FC & R2731 +{ + local quot:4 = R1115 s/ R0004; + local mod:4 = R1115 s% R0004; + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + set_Z(R1115); + set_S(R1115); + R2731 = mod; + R1115 = quot; +} + +# DIVQU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111110 +:divqu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FE & R2731 +{ + local quot:4 = R1115 / R0004; + local mod:4 = R1115 % R0004; + $(OV) = (R0004 == 0); + set_Z(R1115); + set_S(R1115); + R2731 = mod; + R1115 = quot; +} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Float.sinc b/Ghidra/Processors/V850/data/languages/Instructions/Float.sinc similarity index 100% rename from Ghidra/Processors/V850E2M/data/languages/Instructions/Float.sinc rename to Ghidra/Processors/V850/data/languages/Instructions/Float.sinc diff --git a/Ghidra/Processors/V850/data/languages/Instructions/Load_Store.sinc b/Ghidra/Processors/V850/data/languages/Instructions/Load_Store.sinc new file mode 100644 index 0000000000..b0f6584064 --- /dev/null +++ b/Ghidra/Processors/V850/data/languages/Instructions/Load_Store.sinc @@ -0,0 +1,368 @@ +# (1) Load instructions +# (2) Store instructions +# (9) Data manipulation instructions + + + +##################################################### +##### Load ##### +##################################################### + + +# LD.B disp16[reg1], reg2 - rrrrr111000RRRRR|dddddddddddddddd +:ld.b s1631[R0004], R1115 is op0510=0x38 & R0004 & R1115; s1631 +{ + local adr:4 = R0004 + s1631; + R1115 = sext(*:1 adr); +} + +# LD.B disp23[reg1], reg3 - rrrrr111100RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD +:ld.b disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2026 & op1619=0x5; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = sext(*:1 adr); +} + +# LD.BU disp16[reg1], reg2 - rrrrr11110bRRRRR|ddddddddddddddd1 +:ld.bu disp16[R0004], R1115 is op0610=0x1E & R0004 & R1115 & op0505; op1616=0x1 & s1731 +[ disp16 = (s1731 << 1) | op0505; ] +{ + local adr:4 = R0004 + disp16; + R1115 = zext(*:1 adr); +} + +# LD.BU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD +:ld.bu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x5; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = zext(*:1 adr); +} + +# LD.H disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd0 +:ld.h s1631[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1631 & op1616=0x0 +{ + local adr:4 = R0004 + s1631; + R1115 = sext(*:2 adr); +} + +# LD.H disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD +:ld.h disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2126 & op1620=0x7; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + R2731 = sext(*:2 adr); +} + +# LD.HU disp16[reg1], reg2 - rrrrr111111RRRRR|ddddddddddddddd1 +:ld.hu disp16[R0004], R1115 is op0510=0x3F & R0004 & R1115; op1616=0x1 & s1731 +[ disp16 = s1731 << 1; ] +{ + local adr:4 = R0004 + disp16; + R1115 = zext(*:2 adr); +} + +# LD.HU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD +:ld.hu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x7; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = zext(*:2 adr); +} + +# LD.W disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd1 +:ld.w disp16[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1731 & op1616=0x1 +[ disp16 = s1731 * 2; ] +{ + local adr:4 = R0004 + disp16; + R1115 = *:4 adr; +} + +# LD.W disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd01001|DDDDDDDDDDDDDDDD +:ld.w disp23[R0004], R2731 is op0515=0x03C & R0004; R2731 & op2126 & op1620=0x9; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + R2731 = *:4 adr; +} + +# SLD.B disp7[ep], reg2 - rrrrr0110ddddddd +:sld.b op0006[ep], R1115 is op0710=0x06 & op0006 & R1115 & ep +{ + local adr:4 = ep + op0006; + R1115 = sext(*:1 adr); +} + +# SLD.BU disp4[ep], reg2 - rrrrr0000110dddd +:sld.bu op0003[ep], R1115 is op0410=0x06 & R1115 & op0003 & ep +{ + local adr:4 = ep + op0003; + R1115 = zext(*:1 adr); +} + +# SLD.H disp8[ep], reg2 - rrrrr1000ddddddd +:sld.h disp8[ep], R1115 is op0710=0x08 & op0006 & R1115 & ep +[ disp8 = op0006 * 2; ] +{ + local adr:4 = ep + disp8; + R1115 = sext(*:2 adr); +} + +# SLD.HU disp5[ep], reg2 - rrrrr0000111dddd +:sld.hu disp5[ep], R1115 is op0410=0x07 & R1115 & op0003 & ep +[ disp5 = op0003 * 2; ] +{ + local adr:4 = ep + disp5; + R1115 = zext(*:2 adr); +} + +# SLD.W disp8[ep], reg2 - rrrrr1010dddddd0 +:sld.w disp8[ep], R1115 is op0710=0x0A & op0000=0x0 & op0106 & R1115 & ep +[ disp8 = op0106 * 4; ] +{ + local adr:4 = ep + disp8; + R1115 = *:4 adr; +} + + + +##################################################### +##### Store ##### +##################################################### + + +# SST.B reg2, disp7[ep] - rrrrr0111ddddddd +:sst.b R1115, op0006[ep] is op0710=0x07 & op0006 & R1115 & ep +{ + local adr:4 = ep + op0006; + local tmp:4 = R1115; + *:1 adr = tmp:1; +} + +# SST.H reg2, disp8[ep] - rrrrr1001ddddddd +:sst.h R1115, disp8[ep] is op0710=0x09 & op0006 & R1115 & ep +[ disp8 = op0006 * 2; ] +{ + local adr:4 = ep + disp8; + local tmp:4 = R1115; + *:2 adr = tmp:2; +} + +# SST.W reg2, disp8[ep] - rrrrr1010dddddd1 +:sst.w R1115, disp8[ep] is op0710=0x0A & op0000=0x1 & op0106 & R1115 & ep +[ disp8 = op0106 * 4; ] +{ + local adr:4 = ep + disp8; + local tmp:4 = R1115; + *:4 adr = tmp; +} + +# ST.B reg2, disp16[reg1] - rrrrr111010RRRRR|dddddddddddddddd +:st.b R1115, s1631[R0004] is op0510=0x3A & R0004 & R1115; s1631 +{ + local adr:4 = R0004 + s1631; + local tmp:4 = R1115; + *:1 adr = tmp:1; +} + +# ST.B reg3, disp23[reg1] - 00000111100RRRRR|dddddddddddddddd +:st.b R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2026 & op1619=0xD; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:1 adr = tmp:1; +} + +# ST.H reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd0 +:st.h R1115, s1631[R0004] is op0510=0x3B & R0004 & R1115; s1631 & op1616=0x0 +{ + local adr:4 = R0004 + s1631; + local tmp:4 = R1115; + *:2 adr = tmp:2; +} + +# ST.H reg3, disp23[reg1] - 00000111101RRRRR|wwwwwdddddd01101|DDDDDDDDDDDDDDDD +:st.h R2731, disp23[R0004] is op0515=0x3D & R0004; R2731 & op2126 & op1620=0xD; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:2 adr = tmp:2; +} + +# ST.W reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd1 +:st.w R1115, disp16[R0004] is op0510=0x3B & R0004 & R1115; s1731 & op1616=0x1 +[ disp16 = s1731 * 2; ] +{ + local adr:4 = R0004 + disp16; + local tmp:4 = R1115; + *:4 adr = tmp; +} + +# ST.W reg3, disp23[reg1] - 00000111100RRRRR|wwwwwdddddd01111|DDDDDDDDDDDDDDDD +:st.w R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2126 & op1620=0xF; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:2 adr = tmp:2; +} + + + +##################################################### +##### DataManipulation ##### +##################################################### + + +# BSH reg2, reg3 - rrrrr11111100000|wwwww01101000010 +:bsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x342 & R2731 +{ + local x1 = R1115[0,8]; + local x2 = R1115[8,8]; + local x3 = R1115[16,8]; + local x4 = R1115[24,8]; + R2731 = zext(x3 << 24) | zext(x4 << 16) | zext(x1 << 8) | zext(x2); + set_S(R2731); + $(OV) = 0; + $(Z) = (x1 == 0) && (x2 == 0); + $(CY) = (x1 == 0) || (x2 == 0); +} + +# BSW reg2, reg3 - rrrrr11111100000|wwwww01101000000 +:bsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x340 & R2731 +{ + local x1 = R1115[0,8]; + local x2 = R1115[8,8]; + local x3 = R1115[16,8]; + local x4 = R1115[24,8]; + R2731 = zext(x1 << 24) | zext(x2 << 16) | zext(x3 << 8) | zext(x4); + set_OV0_S_Z(R2731); + $(CY) = (x1 == 0) || (x2 == 0) || (x3 == 0) || (x4 == 0); +} + +# CMOV cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011001cccc0 +:cmov^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x19 & op1616=0 & c1720 & R2731 +{ + local result:4 = zext(c1720); + R2731 = R0004 * zext(result != 0) + R1115 * zext(result == 0); +} + +# CMOV cccc, imm5, reg2, reg3 - rrrrr111111iiiii|wwwww011000cccc0 +:cmov^c1720 s0004, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2126=0x18 & op1616=0 & c1720 & R2731 +{ + local result:4 = zext(c1720); + R2731 = s0004 * zext(result != 0) + R1115 * zext(result == 0); +} + +# HSH reg2, reg3 - rrrrr11111100000|wwwww01101000110 +:hsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x346 & R2731 +{ + R2731 = R1115; + set_S(R2731); + $(OV) = 0; + $(Z) = (R2731:2 == 0); + $(CY) = $(Z); +} + +# HSW reg2, reg3 - rrrrr11111100000|wwwww01101000100 +:hsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x344 & R2731 +{ + local x1 = R1115:2; + local x2 = R1115[16,16]; + R2731 = zext(x1 << 16) | zext(x2); + set_OV0_S_Z(R2731); + $(CY) = (x1 == 0) || (x2 == 0); +} + +# SAR reg1, reg2 - rrrrr111111RRRRR|0000000010100000 +:sar R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xA0 +{ + shift_right_arith(R1115, R1115, R0004); +} + +# SAR imm5, reg2 - rrrrr010101iiiii +:sar op0004, R1115 is op0510=0x15 & op0004 & R1115 +{ + shift_right_arith(R1115, R1115, op0004:5); +} + +# SAR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010100010 +:sar R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xA2 & R2731 +{ + shift_right_arith(R2731, R1115, R0004); +} + +# SASF cccc, reg2 - rrrrr1111110cccc|0000001000000000 +:sasf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0200 +{ + R1115 = (R1115 << 1) | zext(c0003); +} + +# SETF cond, reg2 - rrrrr1111110cccc|0000000000000000 +:setf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0 +{ + R1115 = zext(c0003); +} + +# SHL reg1, reg2 - rrrrr111111RRRRR|0000000011000000 +:shl R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xC0 +{ + shift_left_logic(R1115, R1115, R0004); +} + +# SHL imm5, reg2 - rrrrr010110iiiii +:shl op0004, R1115 is op0510=0x16 & op0004 & R1115 +{ + shift_left_logic(R1115, R1115, op0004:5); +} + +# SHL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00011000010 +:shl R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xC2 & R2731 +{ + shift_left_logic(R2731, R1115, R0004); +} + +# SHR reg1, reg2 - rrrrr111111RRRRR|0000000010000000 +:shr R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0x80 +{ + shift_right_logic(R1115, R1115, R0004); +} + +# SHR imm5, reg2 - rrrrr010100iiiii +:shr op0004, R1115 is op0510=0x14 & op0004 & R1115 +{ + shift_right_logic(R1115, R1115, op0004:5); +} + +# SHR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010000010 +:shr R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x82 & R2731 +{ + shift_right_logic(R2731, R1115, R0004); +} + +# SXB reg1 - 00000000101RRRRR +:sxb R0004 is op0515=0x05 & R0004 +{ + R0004 = sext(R0004:1); +} + +# SXH reg1 - 00000000111RRRRR +:sxh R0004 is op0515=0x07 & R0004 +{ + R0004 = sext(R0004:2); +} + +# ZXB reg1 - 00000000100RRRRR +:zxb R0004 is op0515=0x004 & R0004 +{ + R0004 = zext(R0004:1); +} + +# ZXH reg1 - 00000000110RRRRR +:zxh R0004 is op0515=0x006 & R0004 +{ + R0004 = zext(R0004:2); +} \ No newline at end of file diff --git a/Ghidra/Processors/V850/data/languages/Instructions/Logic.sinc b/Ghidra/Processors/V850/data/languages/Instructions/Logic.sinc new file mode 100644 index 0000000000..7b86002964 --- /dev/null +++ b/Ghidra/Processors/V850/data/languages/Instructions/Logic.sinc @@ -0,0 +1,167 @@ +# (6) Conditional arithmetic instructions +# (8) Logical instructions +# (14) Bit manipulation instructions + + + +##################################################### +##### Conditional ##### +##################################################### + + +# ADF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011101cccc0 +:adf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1D & op1616=0 & c1720 & R2731 +{ + local cond = zext(c1720); + set_OV_pos2(R1115, R0004, cond); + set_CY_pos2(R1115, R0004, cond); + R2731 = R1115 + R0004 + cond; + set_S(R2731); + set_Z(R2731); +} + +# SBF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011100cccc0 +:sbf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1C & op1616=0 & c1720 & R2731 +{ + local cond = zext(c1720); + set_OV_neg2(R1115, R0004, cond); + set_CY_neg2(R1115, R0004, cond); + R2731 = R1115 - R0004 - cond; + set_S(R2731); + set_Z(R2731); +} + + + +##################################################### +##### Logic ##### +##################################################### + + +# AND reg1, reg2 - rrrrr001010RRRRR +:and R0004, R1115 is op0510=0x0A & R0004 & R1115 +{ + R1115 = R1115 & R0004; + set_OV0_S_Z(R1115); +} + +# ANDI imm16, reg1, reg2 - rrrrr110110RRRRR|iiiiiiiiiiiiiiii +:andi op1631, R0004, R1115 is op0510=0x36 & R1115 & R0004; op1631 +{ + R1115 = R0004 & op1631; + set_OV0_S_Z(R1115); +} + +# NOT reg1, reg2 - rrrrr000001RRRRR +:not R0004, R1115 is op0510=0x01 & R0004 & R1115 +{ + R1115 = ~R0004; + set_OV0_S_Z(R1115); +} + +# OR reg1, reg2 - rrrrr001000RRRRR +:or R0004, R1115 is op0510=0x08 & R0004 & R1115 +{ + R1115 = R1115 | R0004; + set_OV0_S_Z(R1115); +} + +# ORI imm16, reg1, reg2 - rrrrr110100RRRRR|iiiiiiiiiiiiiiii +:ori op1631, R0004, R1115 is op0510=0x34 & R1115 & R0004; op1631 +{ + R1115 = R0004 | op1631; + set_OV0_S_Z(R1115); +} + +# TST reg1, reg2 - rrrrr001011RRRRR +:tst R0004, R1115 is op0510=0x0B & R0004 & R1115 +{ + set_OV0_S_Z(R1115 & R0004); +} + +# XOR reg1, reg2 - rrrrr001001RRRRR +:xor R0004, R1115 is op0510=0x09 & R0004 & R1115 +{ + R1115 = R1115 ^ R0004; + set_OV0_S_Z(R1115); +} + +# XORI imm16, reg1, reg2 - rrrrr110101RRRRR|iiiiiiiiiiiiiiii +:xori op1631, R0004, R1115 is op0510=0x35 & R1115 & R0004; op1631 +{ + R1115 = R0004 ^ op1631; + set_OV0_S_Z(R1115); +} + + + +##################################################### +##### BitManipulation ##### +##################################################### + + +# CLR1 bit#3, disp16[reg1] - 10bbb111110RRRRR|dddddddddddddddd +:clr1 op1113, s1631[R0004] is op0510=0x3E & op1415=2 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn & ~(1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# CLR1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100100 +:clr1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE4 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn & ~(1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# NOT1 bit#3, disp16[reg1] - 01bbb111110RRRRR|dddddddddddddddd +:not1 op1113, s1631[R0004] is op0510=0x3E & op1415=1 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn ^ (1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# NOT1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100010 +:not1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE2 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn ^ (1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# SET1 bit#3, disp16[reg1] - 00bbb111110RRRRR|dddddddddddddddd +:set1 op1113, s1631[R0004] is op0510=0x3E & op1415=0 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn | (1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# SET1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100000 +:set1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE0 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn | (1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# TST1 bit#3, disp16[reg1] - 11bbb111110RRRRR|dddddddddddddddd +:tst1 op1113, s1631[R0004] is op0510=0x3E & op1415=3 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + set_Z(tkn & (1 << op1113)); +} + +# TST1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100110 +:tst1 R0004, [R1115] is op0510=0x3F & R0004 & R1115; op1631=0xE6 +{ + local tkn = *:1 R0004; + set_Z(tkn & (1 << R1115)); +} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Special.sinc b/Ghidra/Processors/V850/data/languages/Instructions/Special.sinc similarity index 63% rename from Ghidra/Processors/V850E2M/data/languages/Instructions/Special.sinc rename to Ghidra/Processors/V850/data/languages/Instructions/Special.sinc index 95557a95fb..d3270c57e1 100644 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Special.sinc +++ b/Ghidra/Processors/V850/data/languages/Instructions/Special.sinc @@ -1,3 +1,115 @@ +# (10) Bit search instructions +# (13) Branch instructions +# (15) Special instructions + + + +##################################################### +##### BitSearch ##### +##################################################### + + +# SCH0L reg2, reg3 - rrrrr11111100000|wwwww01101100100 +:sch0l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x364 & R2731 +{ + SearchLeft(R2731, R1115, 0); + $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found + $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found +} + +# SCH0R reg2, reg3 - rrrrr11111100000|wwwww01101100000 +:sch0r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x360 & R2731 +{ + SearchRight(R2731, R1115, 0); + $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found + $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found +} + +# SCH1L reg2, reg3 - rrrrr11111100000|wwwww01101100110 +:sch1l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x366 & R2731 +{ + SearchLeft(R2731, R1115, 1); + $(CY) = (R1115 != 0x0); # one bit found + $(Z) = (R1115 == 0x0); # one bit not found +} + +# SCH1R reg2, reg3 +:sch1r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x362 & R2731 +{ + SearchRight(R2731, R1115, 1); + $(CY) = (R1115 != 0x0); # one bit found + $(Z) = (R1115 == 0x0); # one bit not found +} + + + +##################################################### +##### Branch ##### +##################################################### + + +#Bcond adr9 - ddddd1011dddcccc +:b^c0003 adr9 is op0710=0xB & c0003 & adr9 +{ + if (c0003) + goto adr9; +} +:br adr9 is op0710=0xB & op0003=0x5 & adr9 +{ + goto adr9; +} + +# JARL disp22, reg2 - rrrrr11110dddddd|ddddddddddddddd0 +:jarl adr22, R1115 is (op0610=0x1E & R1115) ... & adr22 +{ + R1115 = inst_next; + PC = & adr22; + call adr22; +} + +# JARL disp32, reg1 - 00000010111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jarl adr32, R0004 is op0515=0x017 & R0004; adr32 +{ + R0004 = inst_next; + PC = & adr32; + call adr32; +} + +# JMP [reg1] - 00000000011RRRRR +:jmp [R0004] is op0515=0x03 & R0004 & op0004=0x1F +{ + PC = R0004; + return [R0004]; +} +:jmp [R0004] is op0515=0x03 & R0004 & op0004!=0x1F +{ + PC = R0004; + call [R0004]; +} + +# JMP disp32[reg1] - 00000110111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jmp adr32[R0004] is op0515=0x037 & R0004; adr32 +{ + local adr = adr32 + R0004; + goto [adr]; +} + +# JR disp22 - 00000111110ddddd|ddddddddddddddd0 +:jr adr22 is op0615=0x1E ... & adr22 +{ + PC = & adr22; + goto adr22; +} + +# JR disp32 - 0000001011100000|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jr adr32 is op0015=0x2E0; adr32 +{ + PC = & adr32; + goto adr32; +} + + + ##################################################### ##### Special ##### ##################################################### @@ -16,11 +128,11 @@ # CAXI [reg1], reg2, reg3 - rrrrr111111RRRRR|wwwww00011101110 :caxi [R0004], R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xEE & R2731 { - local token = *:4 R0004; - local result = R1115 - token; - *:4 R0004 = token * zext(result != 0) + R2731 * zext(result == 0); - R2731 = token; - set_general_flags_neg(R1115, token); + local tkn = *:4 (R0004 & ~(0x3)); + local result = R1115 - tkn; + *:4 R0004 = tkn * zext(result != 0) + R2731 * zext(result == 0); + R2731 = tkn; + set_general_flags_neg(R1115, tkn); } # CTRET - 0000011111100000|0000000101000100 @@ -47,11 +159,11 @@ define pcodeop __disable_irq; } # DISPOSE imm5, list12, [reg1] - 0000011001iiiiiL|LLLLLLLLLLLRRRRR -:dispose prep0105, DispList, [prep1620r] is prep0615=0x19 & prep1620r & prep0105 & DispList +:dispose prep0105, DispList, [prep1620] is prep0615=0x19 & prep1620 & prep0105 & DispList { sp = sp + (prep0105 << 2); build DispList; - PC = prep1620r; + PC = prep1620; return [PC]; } @@ -84,8 +196,8 @@ define pcodeop __enable_irq; { FEPC = inst_next; FEPSW = PSW; - $(FECC) = op1114 + 0x31; # exception code 0x31..0x3F - FEIC = op1114 + 0x31; # exception code 0x31..0x3F + $(FECC) = op1114 + 0x30; # exception code 0x30..0x3F + FEIC = op1114 + 0x30; # exception code 0x30..0x3F $(EP) = 1; $(ID) = 1; $(NP) = 1; @@ -209,9 +321,9 @@ define pcodeop __halt; } # SWITCH reg1 - 00000000010RRRRR -:switch r0004 is op0515=0x2 & r0004 +:switch R0004 is op0515=0x2 & R0004 { - local adr:4 = inst_next + (r0004 << 1); + local adr:4 = inst_next + (R0004 << 1); PC = inst_next + (sext(*:2 adr) << 1); goto [PC]; } diff --git a/Ghidra/Processors/V850E2M/data/languages/V850E2M.cspec b/Ghidra/Processors/V850/data/languages/V850.cspec similarity index 100% rename from Ghidra/Processors/V850E2M/data/languages/V850E2M.cspec rename to Ghidra/Processors/V850/data/languages/V850.cspec diff --git a/Ghidra/Processors/V850E2M/data/languages/V850E2M.ldefs b/Ghidra/Processors/V850/data/languages/V850.ldefs similarity index 61% rename from Ghidra/Processors/V850E2M/data/languages/V850E2M.ldefs rename to Ghidra/Processors/V850/data/languages/V850.ldefs index acc1a92e82..556c4add1f 100644 --- a/Ghidra/Processors/V850E2M/data/languages/V850E2M.ldefs +++ b/Ghidra/Processors/V850/data/languages/V850.ldefs @@ -4,13 +4,13 @@ Renesas V850E2M - + \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/V850E2M.pspec b/Ghidra/Processors/V850/data/languages/V850.pspec similarity index 100% rename from Ghidra/Processors/V850E2M/data/languages/V850E2M.pspec rename to Ghidra/Processors/V850/data/languages/V850.pspec diff --git a/Ghidra/Processors/V850E2M/data/languages/V850E2M.slaspec b/Ghidra/Processors/V850/data/languages/V850.slaspec similarity index 62% rename from Ghidra/Processors/V850E2M/data/languages/V850E2M.slaspec rename to Ghidra/Processors/V850/data/languages/V850.slaspec index 21cc5b2d09..b86ecc11a8 100644 --- a/Ghidra/Processors/V850E2M/data/languages/V850E2M.slaspec +++ b/Ghidra/Processors/V850/data/languages/V850.slaspec @@ -30,19 +30,8 @@ define space register type=register_space size=4; ##### Instructions ##### ##################################################### -@include "Instructions/Load.sinc" -@include "Instructions/Store.sinc" -@include "Instructions/Multiply.sinc" -@include "Instructions/MultiplyAccumulate.sinc" @include "Instructions/Arithmetic.sinc" -@include "Instructions/Conditional.sinc" -@include "Instructions/Saturated.sinc" +@include "Instructions/Float.sinc" +@include "Instructions/Load_Store.sinc" @include "Instructions/Logic.sinc" -@include "Instructions/DataManipulation.sinc" -@include "Instructions/BitSearch.sinc" -@include "Instructions/Divide.sinc" -@include "Instructions/HighSpeedDivide.sinc" -@include "Instructions/Branch.sinc" -@include "Instructions/BitManipulation.sinc" -@include "Instructions/Special.sinc" -@include "Instructions/Float.sinc" \ No newline at end of file +@include "Instructions/Special.sinc" \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/manuals/v850.idx b/Ghidra/Processors/V850/data/manuals/v850.idx similarity index 100% rename from Ghidra/Processors/V850E2M/data/manuals/v850.idx rename to Ghidra/Processors/V850/data/manuals/v850.idx diff --git a/Ghidra/Processors/V850E2M/build.gradle b/Ghidra/Processors/V850E2M/build.gradle deleted file mode 100644 index 2e8e16e958..0000000000 --- a/Ghidra/Processors/V850E2M/build.gradle +++ /dev/null @@ -1,4 +0,0 @@ -apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" -apply from: "$rootProject.projectDir/gradle/processorProject.gradle" -apply plugin: 'eclipse' -eclipse.project.name = 'Processors v850' \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Arithmetic.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Arithmetic.sinc deleted file mode 100644 index 0eca37e962..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Arithmetic.sinc +++ /dev/null @@ -1,82 +0,0 @@ -##################################################### -##### Arithmetic ##### -##################################################### - - -# ADD reg1, reg2 - rrrrr001110RRRRR -:add R0004, R1115 is op0510=0x0E & R0004 & R1115 -{ - set_general_flags_pos(R0004, R1115); - R1115 = R1115 + R0004; -} - -# ADD imm5, reg2 - rrrrr010010iiiii -:add s0004, R1115 is op0510=0x12 & s0004 & R1115 -{ - set_general_flags_pos(s0004, R1115); - R1115 = R1115 + s0004; -} - -# ADDI imm16, reg1, reg2 - rrrrr110000RRRRR|iiiiiiiiiiiiiiii -:addi s1631, R0004, R1115 is op0510=0x30 & R1115 & R0004; s1631 -{ - set_general_flags_pos(R0004, s1631); - R1115 = R0004 + s1631; -} - -# CMP reg1, reg2 - rrrrr001111RRRRR -:cmp R0004, R1115 is op0510=0x0F & R0004 & R1115 -{ - set_general_flags_neg(R1115, R0004); -} - -# CMP imm5, reg2 - rrrrr010011iiiii -:cmp s0004, R1115 is op0510=0x13 & s0004 & R1115 -{ - set_general_flags_neg(R1115, s0004); -} - -# MOV reg1, reg2 - rrrrr000000RRRRR -:mov R0004, r1115 is op0510=0x00 & R0004 & r1115 -{ - r1115 = R0004; -} - -# MOV imm5, reg2 - rrrrr010000iiiii -:mov s0004, r1115 is op0510=0x10 & s0004 & r1115 & op1115!=0 -{ - r1115 = s0004; -} - -# MOV imm32, reg1 - 00000110001RRRRR|iiiiiiiiiiiiiiii|IIIIIIIIIIIIIIII -:mov imm32, R0004 is op0515=0x031 & R0004; op1631; op3247 -[ imm32 = (op3247 << 16) | op1631; ] -{ - R0004 = imm32; -} - -# MOVEA imm16, reg1, reg2 - rrrrr110001RRRRR|iiiiiiiiiiiiiiii -:movea s1631, R0004, r1115 is op0510=0x31 & op1115!=0 & R0004 & r1115; s1631 -{ - r1115 = R0004 + s1631; -} - -# MOVHI imm16, reg1, reg2 - rrrrr110010RRRRR|iiiiiiiiiiiiiiii -:movhi s1631, R0004, r1115 is op0510=0x32 & op1115!=0 & R0004 & r1115; s1631 -{ - r1115 = R0004 + (s1631 << 16); -} - -# SUB reg1, reg2 - rrrrr001101RRRRR -:sub R0004, R1115 is op0510=0x0D & R0004 & R1115 -{ - set_general_flags_neg(R1115, R0004); - R1115 = R1115 - R0004; -} - -# SUBR reg1, reg2 - rrrrr001100RRRRR -:subr R0004, R1115 is op0510=0x0C & R0004 & R1115 -{ - set_general_flags_neg(R0004, R1115); - R1115 = R0004 - R1115; -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/BitManipulation.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/BitManipulation.sinc deleted file mode 100644 index f43ee3b5c5..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/BitManipulation.sinc +++ /dev/null @@ -1,70 +0,0 @@ -##################################################### -##### BitManipulation ##### -##################################################### - - -# CLR1 bit#3, disp16[reg1] - 10bbb111110RRRRR|dddddddddddddddd -:clr1 op1113, s1631[R0004] is op0510=0x3E & op1415=2 & op1113 & R0004; s1631 -{ - local adr:4 = R0004 + s1631; - local token = *:1 adr; - *:1 adr = token & ~(1 << op1113); - set_Z(token & (1 << op1113)); -} - -# CLR1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100100 -:clr1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE4 -{ - local token = *:1 R0004; - *:1 R0004 = token & ~(1 << R1115); - set_Z(token & (1 << R1115)); -} - -# NOT1 bit#3, disp16[reg1] - 01bbb111110RRRRR|dddddddddddddddd -:not1 op1113, s1631[R0004] is op0510=0x3E & op1415=1 & op1113 & R0004; s1631 -{ - local adr:4 = R0004 + s1631; - local token = *:1 adr; - *:1 adr = token ^ (1 << op1113); - set_Z(token & (1 << op1113)); -} - -# NOT1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100010 -:not1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE2 -{ - local token = *:1 R0004; - *:1 R0004 = token ^ (1 << R1115); - set_Z(token & (1 << R1115)); -} - -# SET1 bit#3, disp16[reg1] - 00bbb111110RRRRR|dddddddddddddddd -:set1 op1113, s1631[R0004] is op0510=0x3E & op1415=0 & op1113 & R0004; s1631 -{ - local adr:4 = R0004 + s1631; - local token = *:1 adr; - *:1 adr = token | (1 << op1113); - set_Z(token & (1 << op1113)); -} - -# SET1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100000 -:set1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE0 -{ - local token = *:1 R0004; - *:1 R0004 = token | (1 << R1115); - set_Z(token & (1 << R1115)); -} - -# TST1 bit#3, disp16[reg1] - 11bbb111110RRRRR|dddddddddddddddd -:tst1 op1113, s1631[R0004] is op0510=0x3E & op1415=3 & op1113 & R0004; s1631 -{ - local adr:4 = R0004 + s1631; - local token = *:1 adr; - set_Z(token & (1 << op1113)); -} - -# TST1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100110 -:tst1 R0004, [R1115] is op0510=0x3F & R0004 & R1115; op1631=0xE6 -{ - local token = *:1 R0004; - set_Z(token & (1 << R1115)); -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/BitSearch.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/BitSearch.sinc deleted file mode 100644 index 4a83963a37..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/BitSearch.sinc +++ /dev/null @@ -1,36 +0,0 @@ -##################################################### -##### BitSearch ##### -##################################################### - - -# SCH0L reg2, reg3 - rrrrr11111100000|wwwww01101100100 -:sch0l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x364 & R2731 -{ - SearchLeft(R2731, R1115, 0); - $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found - $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found -} - -# SCH0R reg2, reg3 - rrrrr11111100000|wwwww01101100000 -:sch0r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x360 & R2731 -{ - SearchRight(R2731, R1115, 0); - $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found - $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found -} - -# SCH1L reg2, reg3 - rrrrr11111100000|wwwww01101100110 -:sch1l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x366 & R2731 -{ - SearchLeft(R2731, R1115, 1); - $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found - $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found -} - -# SCH1R reg2, reg3 -:sch1r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x362 & R2731 -{ - SearchRight(R2731, R1115, 1); - $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found - $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Branch.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Branch.sinc deleted file mode 100644 index 7a7d1b4698..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Branch.sinc +++ /dev/null @@ -1,64 +0,0 @@ -##################################################### -##### Branch ##### -##################################################### - - -#Bcond adr9 - ddddd1011dddcccc -:b^c0003 adr9 is op0710=0xB & c0003 & adr9 -{ - if (c0003) - goto adr9; -} -:br adr9 is op0710=0xB & op0003=0x5 & adr9 -{ - goto adr9; -} - -# JARL disp22, reg2 - rrrrr11110dddddd|ddddddddddddddd0 -:jarl adr22, r1115 is (op0610=0x1E & r1115) ... & adr22 -{ - r1115 = inst_next; - PC = & adr22; - call adr22; -} - -# JARL disp32, reg1 - 00000010111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD -:jarl adr32, r0004 is op0515=0x017 & r0004; adr32 -{ - r0004 = inst_next; - PC = & adr32; - call adr32; -} - -# JMP [reg1] - 00000000011RRRRR -:jmp [R0004] is op0515=0x03 & R0004 & op0004=0x1F -{ - PC = R0004; - return [R0004]; -} -:jmp [R0004] is op0515=0x03 & R0004 & op0004!=0x1F -{ - PC = R0004; - call [R0004]; -} - -# JMP disp32[reg1] - 00000110111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD -:jmp adr32[R0004] is op0515=0x037 & R0004; adr32 -{ - local adr = adr32 + R0004; - goto [adr]; -} - -# JR disp22 - 00000111110ddddd|ddddddddddddddd0 -:jr adr22 is op0615=0x1E ... & adr22 -{ - PC = & adr22; - goto adr22; -} - -# JR disp32 - 0000001011100000|ddddddddddddddd0|DDDDDDDDDDDDDDDD -:jr adr32 is op0015=0x2E0; adr32 -{ - PC = & adr32; - goto adr32; -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Conditional.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Conditional.sinc deleted file mode 100644 index f210b23e37..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Conditional.sinc +++ /dev/null @@ -1,26 +0,0 @@ -##################################################### -##### Conditional ##### -##################################################### - - -# ADF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011101cccc0 -:adf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1D & op1616=0 & c1720 & R2731 -{ - local cond = zext(c1720); - set_OV_pos2(R1115, R0004, cond); - set_CY_pos2(R1115, R0004, cond); - R2731 = R1115 + R0004 + cond; - set_S(R2731); - set_Z(R2731); -} - -# SBF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011100cccc0 -:sbf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1C & op1616=0 & c1720 & R2731 -{ - local cond = zext(c1720); - set_OV_neg2(R1115, R0004, cond); - set_CY_neg2(R1115, R0004, cond); - R2731 = R1115 - R0004 - cond; - set_S(R2731); - set_Z(R2731); -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/DataManipulation.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/DataManipulation.sinc deleted file mode 100644 index b1d85d06df..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/DataManipulation.sinc +++ /dev/null @@ -1,150 +0,0 @@ -##################################################### -##### DataManipulation ##### -##################################################### - - -# BSH reg2, reg3 - rrrrr11111100000|wwwww01101000010 -:bsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x342 & R2731 -{ - local x1 = R1115[0,8]; - local x2 = R1115[8,8]; - local x3 = R1115[16,8]; - local x4 = R1115[24,8]; - R2731 = zext(x3 << 24) | zext(x4 << 16) | zext(x1 << 8) | zext(x2); - set_OV0_S_Z(R2731); - $(CY) = (x1 == 0) || (x2 == 0); -} - -# BSW reg2, reg3 - rrrrr11111100000|wwwww01101000000 -:bsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x340 & R2731 -{ - local x1 = R1115[0,8]; - local x2 = R1115[8,8]; - local x3 = R1115[16,8]; - local x4 = R1115[24,8]; - R2731 = zext(x1 << 24) | zext(x2 << 16) | zext(x3 << 8) | zext(x4); - set_OV0_S_Z(R2731); - $(CY) = (x1 == 0) || (x2 == 0) || (x3 == 0) || (x4 == 0); -} - -# CMOV cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011001cccc0 -:cmov^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x19 & op1616=0 & c1720 & R2731 -{ - local result:4 = zext(c1720); - R2731 = R0004 * zext(result != 0) + R1115 * zext(result == 0); -} - -# CMOV cccc, imm5, reg2, reg3 - rrrrr111111iiiii|wwwww011000cccc0 -:cmov^c1720 s0004, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2126=0x18 & op1616=0 & c1720 & R2731 -{ - local result:4 = zext(c1720); - R2731 = s0004 * zext(result != 0) + R1115 * zext(result == 0); -} - -# HSH reg2, reg3 - rrrrr11111100000|wwwww01101000110 -:hsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x346 & R2731 -{ - R2731 = R1115; - set_OV0_S_Z(R2731); - $(CY) = (R2731[0,16] == 0); -} - -# HSW reg2, reg3 - rrrrr11111100000|wwwww01101000100 -:hsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x344 & R2731 -{ - local x1 = R1115[0,16]; - local x2 = R1115[16,16]; - R2731 = zext(x1 << 16) | zext(x2); - set_OV0_S_Z(R2731); - $(CY) = (x1 == 0) || (x2 == 0); -} - -# SAR reg1, reg2 - rrrrr111111RRRRR|0000000010100000 -:sar R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xA0 -{ - shift_right_arith(R1115, R1115, R0004); -} - -# SAR imm5, reg2 - rrrrr010101iiiii -:sar op0004, R1115 is op0510=0x15 & op0004 & R1115 -{ - shift_right_arith(R1115, R1115, op0004:5); -} - -# SAR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010100010 -:sar R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xA2 & R2731 -{ - shift_right_arith(R2731, R1115, R0004); -} - -# SASF cccc, reg2 - rrrrr1111110cccc|0000001000000000 -:sasf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0200 -{ - R1115 = (R1115 << 1) | zext(c0003); -} - -# SETF cond, reg2 - rrrrr1111110cccc|0000000000000000 -:setf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0 -{ - R1115 = zext(c0003); -} - -# SHL reg1, reg2 - rrrrr111111RRRRR|0000000011000000 -:shl R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xC0 -{ - shift_left_logic(R1115, R1115, R0004); -} - -# SHL imm5, reg2 - rrrrr010110iiiii -:shl op0004, R1115 is op0510=0x16 & op0004 & R1115 -{ - shift_left_logic(R1115, R1115, op0004:5); -} - -# SHL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00011000010 -:shl R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xC2 & R2731 -{ - shift_left_logic(R2731, R1115, R0004); -} - -# SHR reg1, reg2 - rrrrr111111RRRRR|0000000010000000 -:shr R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0x80 -{ - shift_right_logic(R1115, R1115, R0004); -} - -# SHR imm5, reg2 - rrrrr010100iiiii -:shr op0004, R1115 is op0510=0x14 & op0004 & R1115 -{ - shift_right_logic(R1115, R1115, op0004:5); -} - -# SHR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010000010 -:shr R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x82 & R2731 -{ - shift_right_logic(R2731, R1115, R0004); -} - -# SXB reg1 - 00000000101RRRRR -:sxb R0004 is op0515=0x05 & R0004 -{ - R0004 = sext(R0004[0,8]); -} - -# SXH reg1 - 00000000111RRRRR -:sxh R0004 is op0515=0x07 & R0004 -{ - R0004 = sext(R0004[0,16]); -} - -# ZXB reg1 - 00000000100RRRRR -:zxb R0004 is op0515=0x004 & R0004 -{ - R0004 = zext(R0004[0,8]); -} - -# ZXH reg1 - 00000000110RRRRR -:zxh R0004 is op0515=0x006 & R0004 -{ - R0004 = zext(R0004[0,16]); -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Divide.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Divide.sinc deleted file mode 100644 index da469f07ae..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Divide.sinc +++ /dev/null @@ -1,61 +0,0 @@ -##################################################### -##### Divide ##### -##################################################### - - -# DIV reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000000 -:div R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C0 & R2731 -{ - local quot:4 = R1115 s/ R0004; - local mod:4 = R1115 s% R0004; - $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); - set_Z(R1115); - set_S(R1115); - R2731 = mod; - R1115 = quot; -} - -# DIVH reg1, reg2 - rrrrr000010RRRRR -:divh r0004, r1115 is op0510=0x02 & r0004 & r1115 -{ - $(OV) = ((r1115 == 0x80000000 && r0004 == 0xFFFFFFFF) || r0004 == 0x0); - r1115 = r1115 / r0004; - set_Z(r1115); - set_S(r1115); -} - -# DIVH reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000000 -:divh R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x280 & R2731 -{ - local quot:4 = R1115 s/ R0004; - local mod:4 = R1115 s% R0004; - $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); - set_Z(R1115); - set_S(R1115); - R2731 = mod; - R1115 = quot; -} - -# DIVHU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000010 -:divhu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x282 & R2731 -{ - local quot:4 = R1115 s/ R0004; - local mod:4 = R1115 s% R0004; - $(OV) = (R0004 == 0); - set_Z(R1115); - set_S(R1115); - R2731 = mod; - R1115 = quot; -} - -# DIVU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000010 -:divu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C2 & R2731 -{ - local quot:4 = R1115 s/ R0004; - local mod:4 = R1115 s% R0004; - $(OV) = (R0004 == 0); - set_Z(R1115); - set_S(R1115); - R2731 = mod; - R1115 = quot; -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/HighSpeedDivide.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/HighSpeedDivide.sinc deleted file mode 100644 index 649ab2a2db..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/HighSpeedDivide.sinc +++ /dev/null @@ -1,28 +0,0 @@ -##################################################### -##### HighSpeedDivide ##### -##################################################### - - -# DIVQ reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111100 -:div R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FC & R2731 -{ - local quot:4 = R1115 s/ R0004; - local mod:4 = R1115 s% R0004; - $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); - set_Z(R1115); - set_S(R1115); - R2731 = mod; - R1115 = quot; -} - -# DIVQU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111110 -:divqu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FE & R2731 -{ - local quot:4 = R1115 s/ R0004; - local mod:4 = R1115 s% R0004; - $(OV) = (R0004 == 0); - set_Z(R1115); - set_S(R1115); - R2731 = mod; - R1115 = quot; -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Load.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Load.sinc deleted file mode 100644 index 5e065b7cc8..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Load.sinc +++ /dev/null @@ -1,120 +0,0 @@ -##################################################### -##### Load ##### -##################################################### - - -# LD.B disp16[reg1], reg2 - rrrrr111000RRRRR|dddddddddddddddd -:ld.b s1631[R0004], R1115 is op0510=0x38 & R0004 & R1115; s1631 -{ - local adr:4 = R0004 + s1631; - R1115 = sext(*:1 adr); -} - -# LD.B disp23[reg1], reg3 - rrrrr111100RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD -:ld.b disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2026 & op1619=0x5; s3247 -[ disp23 = (s3247 << 7) | op2026; ] -{ - local adr:4 = R0004 + disp23; - R2731 = sext(*:1 adr); -} - -# LD.BU disp16[reg1], reg2 - rrrrr11110bRRRRR|ddddddddddddddd1 -:ld.bu disp16[R0004], r1115 is op0610=0x1E & R0004 & r1115 & op0505; op1616=0x1 & s1731 -[ disp16 = (s1731 << 1) | op0505; ] -{ - local adr:4 = R0004 + disp16; - r1115 = zext(*:1 adr); -} - -# LD.BU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD -:ld.bu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x5; s3247 -[ disp23 = (s3247 << 7) | op2026; ] -{ - local adr:4 = R0004 + disp23; - R2731 = zext(*:1 adr); -} - -# LD.H disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd0 -:ld.h s1631[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1631 & op1616=0x0 -{ - local adr:4 = R0004 + s1631; - R1115 = sext(*:2 adr); -} - -# LD.H disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD -:ld.h disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2126 & op1620=0x7; s3247 -[ disp23 = (s3247 << 7) | (op2126 << 1); ] -{ - local adr:4 = R0004 + disp23; - R2731 = sext(*:2 adr); -} - -# LD.HU disp16[reg1], reg2 - rrrrr111111RRRRR|ddddddddddddddd1 -:ld.hu disp16[R0004], r1115 is op0510=0x3F & R0004 & r1115; op1616=0x1 & s1731 -[ disp16 = s1731 << 1; ] -{ - local adr:4 = R0004 + disp16; - r1115 = zext(*:2 adr); -} - -# LD.HU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD -:ld.hu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x7; s3247 -[ disp23 = (s3247 << 7) | op2026; ] -{ - local adr:4 = R0004 + disp23; - R2731 = zext(*:2 adr); -} - -# LD.W disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd1 -:ld.w disp16[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1731 & op1616=0x1 -[ disp16 = s1731 * 2; ] -{ - local adr:4 = R0004 + disp16; - R1115 = *:4 adr; -} - -# LD.W disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd01001|DDDDDDDDDDDDDDDD -:ld.w disp23[R0004], R2731 is op0515=0x03C & R0004; R2731 & op2126 & op1620=0x9; s3247 -[ disp23 = (s3247 << 7) | (op2126 << 1); ] -{ - local adr:4 = R0004 + disp23; - R2731 = *:4 adr; -} - -# SLD.B disp7[ep], reg2 - rrrrr0110ddddddd -:sld.b op0006[ep], R1115 is op0710=0x06 & op0006 & R1115 & ep -{ - local adr:4 = ep + op0006; - R1115 = zext(*:1 adr); -} - -# SLD.BU disp4[ep], reg2 - rrrrr0000110dddd -:sld.bu op0003[ep], r1115 is op0410=0x06 & r1115 & op0003 & ep -{ - local adr:4 = ep + op0003; - r1115 = zext(*:1 adr); -} - -# SLD.H disp8[ep], reg2 - rrrrr1000ddddddd -:sld.h disp8[ep], R1115 is op0710=0x08 & op0006 & R1115 & ep -[ disp8 = op0006 * 2; ] -{ - local adr:4 = ep + disp8; - R1115 = zext(*:2 adr); -} - -# SLD.HU disp5[ep], reg2 - rrrrr0000111dddd -:sld.hu disp5[ep], r1115 is op0410=0x07 & r1115 & op0003 & ep -[ disp5 = op0003 * 2; ] -{ - local adr:4 = ep + disp5; - r1115 = zext(*:2 adr); -} - -# SLD.W disp8[ep], reg2 - rrrrr1010dddddd0 -:sld.w disp8[ep], R1115 is op0710=0x0A & op0000=0x0 & op0106 & R1115 & ep -[ disp8 = op0106 * 4; ] -{ - local adr:4 = ep + disp8; - R1115 = *:4 adr; -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Logic.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Logic.sinc deleted file mode 100644 index f23264e9f2..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Logic.sinc +++ /dev/null @@ -1,59 +0,0 @@ -##################################################### -##### Logic ##### -##################################################### - - -# AND reg1, reg2 - rrrrr001010RRRRR -:and R0004, R1115 is op0510=0x0A & R0004 & R1115 -{ - R1115 = R1115 & R0004; - set_OV0_S_Z(R1115); -} - -# ANDI imm16, reg1, reg2 - rrrrr110110RRRRR|iiiiiiiiiiiiiiii -:andi op1631, R0004, R1115 is op0510=0x36 & R1115 & R0004; op1631 -{ - R1115 = R0004 & op1631; - set_OV0_S_Z(R1115); -} - -# NOT reg1, reg2 - rrrrr000001RRRRR -:not R0004, R1115 is op0510=0x01 & R0004 & R1115 -{ - R1115 = ~R0004; - set_OV0_S_Z(R1115); -} - -# OR reg1, reg2 - rrrrr001000RRRRR -:or R0004, R1115 is op0510=0x08 & R0004 & R1115 -{ - R1115 = R1115 | R0004; - set_OV0_S_Z(R1115); -} - -# ORI imm16, reg1, reg2 - rrrrr110100RRRRR|iiiiiiiiiiiiiiii -:ori op1631, R0004, R1115 is op0510=0x34 & R1115 & R0004; op1631 -{ - R1115 = R0004 | op1631; - set_OV0_S_Z(R1115); -} - -# TST reg1, reg2 - rrrrr001011RRRRR -:tst R0004, R1115 is op0510=0x0B & R0004 & R1115 -{ - set_OV0_S_Z(R1115 & R0004); -} - -# XOR reg1, reg2 - rrrrr001001RRRRR -:xor R0004, R1115 is op0510=0x09 & R0004 & R1115 -{ - R1115 = R1115 ^ R0004; - set_OV0_S_Z(R1115); -} - -# XORI imm16, reg1, reg2 - rrrrr110101RRRRR|iiiiiiiiiiiiiiii -:xori op1631, R0004, R1115 is op0510=0x35 & R1115 & R0004; op1631 -{ - R1115 = R0004 ^ op1631; - set_OV0_S_Z(R1115); -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Multiply.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Multiply.sinc deleted file mode 100644 index b7b36cf750..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Multiply.sinc +++ /dev/null @@ -1,57 +0,0 @@ -##################################################### -##### Multiply ##### -##################################################### - - -# MUL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100000 -:mul R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x220 & R2731 -{ - local res:8 = sext(R1115) * sext(R0004); - R1115 = res[0,32]; - R2731 = res[32,32]; -} - -# MUL imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII00 -:mul imm9, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2226=0x9 & op1617=0x0 & s1821 & R2731 -[ imm9 = (s1821 << 5) | s0004; ] -{ - local res:8 = sext(R1115) * imm9; - R1115 = res[0,32]; - R2731 = res[32,32]; -} - -# MULH reg1, reg2 - rrrrr000111RRRRR -:mulh R0004, r1115 is op0510=0x07 & R0004 & r1115 & op1115!=0 -{ - r1115 = sext(r1115:2) * sext(R0004:2); -} - -# MULH imm5, reg2 - rrrrr010111iiiii -:mulh s0004, r1115 is op0510=0x17 & s0004 & r1115 -{ - r1115 = sext(r1115:2) * s0004; -} - -# MULHI imm16, reg1, reg2 - rrrrr110111RRRRR|iiiiiiiiiiiiiiii -:mulhi s1631, R0004, r1115 is op0510=0x37 & r1115 & R0004; s1631 -{ - r1115 = R0004 * s1631; -} - -# MULU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100010 -:mulu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x222 & R2731 -{ - local res:8 = zext(R1115) * zext(R0004); - R1115 = res[0,32]; - R2731 = res[32,32]; -} - -# MULU imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII10 -:mulu imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x2 & op1821 & R2731 -[ imm9 = (op1821 << 5) | op0004; ] -{ - local res:8 = zext(R1115) * imm9; - R1115 = res[0,32]; - R2731 = res[32,32]; -} - diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/MultiplyAccumulate.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/MultiplyAccumulate.sinc deleted file mode 100644 index fd36b83b71..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/MultiplyAccumulate.sinc +++ /dev/null @@ -1,16 +0,0 @@ -##################################################### -##### MultiplyAccumulate ##### -##################################################### - - -# MAC reg1, reg2, reg3, reg4 - rrrrr111111RRRRR wwww0011110mmmm0 -:mac R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1E & op1616=0 & R1620x2 & R2731x2 -{ - R1620x2 = sext(R1115) * sext(R0004) + R2731x2; -} - -# MACU reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwww0011111mmmm0 -:macu R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1F & op1616=0 & R1620x2 & R2731x2 -{ - R1620x2 = zext(R1115) * zext(R0004) + R2731x2; -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Saturated.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Saturated.sinc deleted file mode 100644 index 8971eaae44..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Saturated.sinc +++ /dev/null @@ -1,67 +0,0 @@ -##################################################### -##### Saturated ##### -##################################################### - - -# SATADD reg1, reg2 - rrrrr000110RRRRR -:satadd R0004, r1115 is op0510=0x06 & R0004 & r1115 & op1115!=0 -{ - set_general_flags_pos(r1115, R0004); - $(SAT) = $(SAT) || $(OV); - r1115 = r1115 + R0004; - saturate(r1115); -} - -#SATADD imm5, reg2 - rrrrr010001iiiii -:satadd s0004, r1115 is op0510=0x11 & s0004 & r1115 & op1115!=0 -{ - set_general_flags_pos(r1115, s0004); - $(SAT) = $(SAT) || $(OV); - r1115 = r1115 + s0004; - saturate(r1115); -} - -# SATADD reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110111010 -:satadd R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x3BA & R2731 -{ - set_general_flags_pos(R1115, R0004); - $(SAT) = $(SAT) || $(OV); - R2731 = R1115 + R0004; - saturate(R2731); -} - -# SATSUB reg1, reg2 - rrrrr000101RRRRR -:satsub R0004, r1115 is op0510=0x05 & R0004 & r1115 & op1115!=0 -{ - set_general_flags_neg(r1115, R0004); - $(SAT) = $(SAT) || $(OV); - r1115 = r1115 - R0004; - saturate(r1115); -} - -# SATSUB reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110011010 -:satsub R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x39A & R2731 -{ - set_general_flags_neg(R1115, R0004); - $(SAT) = $(SAT) || $(OV); - R2731 = R1115 - R0004; - saturate(R2731); -} - -# SATSUBI imm16, reg1, reg2 -:satsubi s1631, R0004, r1115 is op0510=0x33 & op1115!=0 & R0004 & r1115; s1631 -{ - set_general_flags_neg(R0004, s1631); - $(SAT) = $(SAT) || $(OV); - r1115 = R0004 - s1631; - saturate(r1115); -} - -# SATSUBR reg1, reg2 -:satsubr R0004, r1115 is op0510=0x04 & R0004 & r1115 & op1115!=0 -{ - set_general_flags_neg(R0004, r1115); - $(SAT) = $(SAT) || $(OV); - r1115 = R0004 - r1115; - saturate(r1115); -} \ No newline at end of file diff --git a/Ghidra/Processors/V850E2M/data/languages/Instructions/Store.sinc b/Ghidra/Processors/V850E2M/data/languages/Instructions/Store.sinc deleted file mode 100644 index 3b4e011049..0000000000 --- a/Ghidra/Processors/V850E2M/data/languages/Instructions/Store.sinc +++ /dev/null @@ -1,73 +0,0 @@ -##################################################### -##### Store ##### -##################################################### - - -# SST.B reg2, disp7[ep] - rrrrr0111ddddddd -:sst.b R1115, op0006[ep] is op0710=0x07 & op0006 & R1115 & ep -{ - local adr:4 = ep + op0006; - *:1 adr = R1115:1; -} - -# SST.H reg2, disp8[ep] - rrrrr1001ddddddd -:sst.h R1115, disp8[ep] is op0710=0x09 & op0006 & R1115 & ep -[ disp8 = op0006 * 2; ] -{ - local adr:4 = ep + disp8; - *:2 adr = R1115:2; -} - -# SST.W reg2, disp8[ep] - rrrrr1010dddddd1 -:sst.w R1115, disp8[ep] is op0710=0x0A & op0000=0x1 & op0106 & R1115 & ep -[ disp8 = op0106 * 4; ] -{ - local adr:4 = ep + disp8; - *:4 adr = R1115; -} - -# ST.B reg2, disp16[reg1] - rrrrr111010RRRRR|dddddddddddddddd -:st.b R1115, s1631[R0004] is op0510=0x3A & R0004 & R1115; s1631 -{ - local adr:4 = R0004 + s1631; - *:1 adr = R1115:1; -} - -# ST.B reg3, disp23[reg1] - 00000111100RRRRR|dddddddddddddddd -:st.b R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2026 & op1619=0xD; s3247 -[ disp23 = (s3247 << 7) | op2026; ] -{ - local adr:4 = R0004 + disp23; - *:1 adr = R2731:1; -} - -# ST.H reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd0 -:st.h R1115, s1631[R0004] is op0510=0x3B & R0004 & R1115; s1631 & op1616=0x0 -{ - local adr:4 = R0004 + s1631; - *:2 adr = R1115:2; -} - -# ST.H reg3, disp23[reg1] - 00000111101RRRRR|wwwwwdddddd01101|DDDDDDDDDDDDDDDD -:st.h R2731, disp23[R0004] is op0515=0x3D & R0004; R2731 & op2126 & op1620=0xD; s3247 -[ disp23 = (s3247 << 7) | (op2126 << 1); ] -{ - local adr:4 = R0004 + disp23; - *:2 adr = R2731:2; -} - -# ST.W reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd1 -:st.w R1115, disp16[R0004] is op0510=0x3B & R0004 & R1115; s1731 & op1616=0x1 -[ disp16 = s1731 * 2; ] -{ - local adr:4 = R0004 + disp16; - *:4 adr = R1115; -} - -# ST.W reg3, disp23[reg1] - 00000111100RRRRR|wwwwwdddddd01111|DDDDDDDDDDDDDDDD -:st.w R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2126 & op1620=0xF; s3247 -[ disp23 = (s3247 << 7) | (op2126 << 1); ] -{ - local adr:4 = R0004 + disp23; - *:2 adr = R2731:2; -} \ No newline at end of file