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GP-3211: Code review fix
This commit is contained in:
ghidorahrex
parent
81fb89e259
commit
aa754f482b
@ -392,7 +392,10 @@ public interface ElfConstants {
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public static final short EM_TI_C2000 = 141;
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/** The Texas Instruments TMS320C55x DSP family */
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public static final short EM_TI_C5500 = 142;
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// 143 - 159 reserved
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// 143 reserved
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/** exas Instruments Programmable Realtime Unit */
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public static final short EM_TI_PRU = 144;
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// 145 - 159 reserved
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/** STMicroelectronics 64bit VLIW Data Signal Processor */
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public static final short EM_MMDSP_PLUS = 160;
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/** Cypress M8C microprocessor */
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@ -439,9 +442,10 @@ public interface ElfConstants {
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public static final short EM_L10M = 180;
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/** Intel K10M */
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public static final short EM_K10M = 181;
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// 182 reserved
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// 182 reserved by Intel
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/** AARCH64 Architecture */
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public static final short EM_AARCH64 = 183;
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// 184 reserved by ARM
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/** Atmel Corporation 32-bit microprocessor family */
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public static final short EM_AVR32 = 185;
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/** STMicroeletronics STM8 8-bit microcontroller */
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@ -480,7 +484,9 @@ public interface ElfConstants {
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public static final short EM_XCORE = 203;
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/** Microchip 8-bit PIC(r) family */
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public static final short EM_MCHP_PIC = 204;
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// 205 - 209 reserved by Intel
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/** Intel Graphics Technology */
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public static final short EM_INTELGT = 205;
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// 206 - 209 reserved by Intel
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/** KM211 KM32 32-bit processor */
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public static final short EM_KM32 = 210;
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/** KM211 KMX32 32-bit processor */
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@ -501,16 +507,57 @@ public interface ElfConstants {
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public static final short EM_NORC = 218;
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/** CSR Kalimba architecture family */
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public static final short EM_CSR_KALIMBA = 219;
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// 220 - 223 reserved
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/** Zilog Z80 */
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public static final short EM_Z80 = 220;
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/** Controls and Data Services VISIUMcore processor */
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public static final short EM_VISIUM = 221;
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/** FTDI Chip FT32 high performance 32-bit RISC architecture */
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public static final short EM_FT32 = 222;
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/** Moxie processor family */
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public static final short EM_MOXIE = 223;
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/** AMD GPU architecture */
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public static final short EM_AMDGPU = 224;
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/** RISC-V */
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public static final short EM_RISCV = 243;
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/** Lanai 32-bit processor */
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public static final short EM_LANAI = 244;
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/** CEVA Processor Architecture Family */
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public static final short EM_CEVA = 245;
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/** CEVA X2 Processor Family */
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public static final short EM_CEVA_X2 = 246;
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/** Linux kernel bpf virtual machine */
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public static final short EM_BPF = 247;
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/** Graphcore Intelligent Processing Unit */
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public static final short EM_GRAPHCORE_IPU = 248;
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/** Imagination Technologies */
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public static final short EM_IMG1 = 249;
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/** Netronome Flow Processor. */
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public static final short EM_NFP = 250;
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/** NEC Vector Engine */
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public static final short EM_VE = 251;
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/** C-SKY processor family. */
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public static final short EM_CSKY = 252;
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/** Synopsys ARCv2.3 64-bit */
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public static final short EM_ARC_COMPACT3_64 = 253;
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/** MOS Technology MCS 6502 processor */
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public static final short EM_MCS6502 = 254;
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/** Synopsys ARCv2.3 32-bit */
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public static final short EM_ARC_COMPACT3 = 255;
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/** Kalray VLIW core of the MPPA processor family */
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public static final short EM_KVX = 256;
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/** WDC 65816/65C816 */
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public static final short EM_65816 = 257;
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/** LoongArch*/
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public static final short EM_LOONGARCH = 258;
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/** ChipON KungFu32 */
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public static final short EM_KF32 = 259;
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/** Linux kernel bpf virtual machine */
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public static final short EM_U16_U8CORE = 260;
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/** Tachyum */
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public static final short EM_TACHYUM = 261;
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/** NXP 56800EF Digital Signal Controller (DSC) */
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public static final short EM_56800EF = 262;
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/** used by NetBSD/avr32 - AVR 32-bit */
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public static final short EM_AVR32_unofficial = 0x18ad;
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@ -3,11 +3,12 @@ define endian=little;
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define alignment=4;
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define space ram type=ram_space size=$(REGSIZE) default;
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define space register type=register_space size=4;
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define space ram type=ram_space size=$(REGSIZE) default;
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define space iocsr type=ram_space size=$(REGSIZE);
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define space register type=register_space size=4;
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define register offset=0x0 size=8 [
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pc scr0 scr1 scr2 scr3
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pc scr0 scr1 scr2 scr3
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];
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define register offset=0x40 size=1 [
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@ -38,11 +39,11 @@ define register offset=0x100 size=4 [
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r0_lo r0_hi ra_lo ra_hi tp_lo tp_hi sp_lo sp_hi
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a0_lo a0_hi a1_lo a1_hi a2_lo a2_hi a3_lo a3_hi
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a4_lo a4_hi a5_lo a5_hi a6_lo a6_hi a7_lo a7_hi
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t0_lo t0_hi t1_lo t1_hi t2_lo t2_hi t3_lo t3_hi
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t4_lo t4_hi t5_lo t5_hi t6_lo t6_hi t7_lo t7_hi
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t8_lo t8_hi r21_lo r21_hi fp_lo fp_hi s0_lo s0_hi
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s1_lo s1_hi s2_lo s2_hi s3_lo s3_hi s4_lo s4_hi
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s5_lo s5_hi s6_lo s6_hi s7_lo s7_hi s8_lo s8_hi
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t0_lo t0_hi t1_lo t1_hi t2_lo t2_hi t3_lo t3_hi
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t4_lo t4_hi t5_lo t5_hi t6_lo t6_hi t7_lo t7_hi
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t8_lo t8_hi r21_lo r21_hi fp_lo fp_hi s0_lo s0_hi
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s1_lo s1_hi s2_lo s2_hi s3_lo s3_hi s4_lo s4_hi
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s5_lo s5_hi s6_lo s6_hi s7_lo s7_hi s8_lo s8_hi
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];
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@endif
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@ -133,45 +134,44 @@ define register offset=0x1000 size=32 [
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@define CSR_OFFSET "0x2000" #used for the csr instructions csrxchg/cssrd/cssrw
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define register offset=$(CSR_OFFSET) size=$(REGSIZE) [
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crmd prmd euen misc ecfg estat era badv
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badi csr9 csr10 csr11 eentry csr13 csr14 csr15
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tlbidx tlbehi tlbelo0 tlbelo1 csr20 csr21 csr22 csr23
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asid pgdl pgdh pgd pwcl pwch stlbps rvacfg
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cpuid prcfg1 prcfg2 prcfg3 csr36 csr37 csr38 csr39
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csr40 csr41 csr42 csr43 csr44 csr45 csr46 csr47
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save0 save1 save2 save3 save4 save5 save6 save7
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save8 save9 save10 save11 save12 save13 save14 save15
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tid tcfg tval cntc ticlr csr69 csr70 csr71
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csr72 csr73 csr74 csr75 csr76 csr78 csr79
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csr80 csr81 csr82 csr83 csr84 csr85 csr86 csr87
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csr88 csr89 csr90 csr91 csr92 csr93 csr94 csr95
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llbctl csr97 csr98 csr99 csr100 csr101 csr102 csr103
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csr104 csr105 csr106 csr107 csr108 csr109 csr110 csr111
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csr112 csr113 csr114 csr115 csr116 csr117 csr118 csr119
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csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127
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impctl1 impctl2 csr130 csr131 csr132 csr133 csr134 csr135
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tlbrentry tlbrbadv tlbrera tlbrsave tlbrelo0 tlbrelo1 tlbrehi tlbrprmd
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merrctl merrinfo1 merrinfo2 merrentry merrera merrsave csr150 csr151
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ctag csr153 csr154 csr155 csr156 csr157 csr158 csr159
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csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167
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csr168 csr169 csr170 csr171 csr172 csr173 csr174 csr175
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csr176 csr177 csr178 csr179 csr180 csr181 csr182 csr183
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csr184 csr185 csr186 csr187 csr188 csr189 csr190 csr191
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csr192 csr193 csr194 csr195 csr196 csr197 csr198 csr199
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csr200 csr201 csr202 csr203 csr204 csr205 csr206 csr207
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csr208 csr209 csr210 csr211 csr212 csr213 csr214 csr215
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csr216 csr217 csr218 csr219 csr220 csr221 csr222 csr223
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csr224 csr225 csr226 csr227 csr228 csr229 csr230 csr231
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csr232 csr233 csr234 csr235 csr236 csr237 csr238 csr239
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csr240 csr241 csr242 csr243 csr244 csr245 csr246 csr247
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csr248 csr249 csr250 csr251 csr252 csr253 csr254 csr255
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csr256 csr257 csr258 csr259 csr260 csr261 csr262 csr263
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crmd prmd euen misc ecfg estat era badv
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badi csr9 csr10 csr11 eentry csr13 csr14 csr15
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tlbidx tlbehi tlbelo0 tlbelo1 csr20 csr21 csr22 csr23
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asid pgdl pgdh pgd pwcl pwch stlbps rvacfg
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cpuid prcfg1 prcfg2 prcfg3 csr36 csr37 csr38 csr39
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csr40 csr41 csr42 csr43 csr44 csr45 csr46 csr47
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save0 save1 save2 save3 save4 save5 save6 save7
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save8 save9 save10 save11 save12 save13 save14 save15
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tid tcfg tval cntc ticlr csr69 csr70 csr71
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csr72 csr73 csr74 csr75 csr76 csr78 csr79
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csr80 csr81 csr82 csr83 csr84 csr85 csr86 csr87
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csr88 csr89 csr90 csr91 csr92 csr93 csr94 csr95
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llbctl csr97 csr98 csr99 csr100 csr101 csr102 csr103
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csr104 csr105 csr106 csr107 csr108 csr109 csr110 csr111
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csr112 csr113 csr114 csr115 csr116 csr117 csr118 csr119
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csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127
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impctl1 impctl2 csr130 csr131 csr132 csr133 csr134 csr135
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tlbrentry tlbrbadv tlbrera tlbrsave tlbrelo0 tlbrelo1 tlbrehi tlbrprmd
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merrctl merrinfo1 merrinfo2 merrentry merrera merrsave csr150 csr151
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ctag csr153 csr154 csr155 csr156 csr157 csr158 csr159
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csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167
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csr168 csr169 csr170 csr171 csr172 csr173 csr174 csr175
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csr176 csr177 csr178 csr179 csr180 csr181 csr182 csr183
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csr184 csr185 csr186 csr187 csr188 csr189 csr190 csr191
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csr192 csr193 csr194 csr195 csr196 csr197 csr198 csr199
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csr200 csr201 csr202 csr203 csr204 csr205 csr206 csr207
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csr208 csr209 csr210 csr211 csr212 csr213 csr214 csr215
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csr216 csr217 csr218 csr219 csr220 csr221 csr222 csr223
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csr224 csr225 csr226 csr227 csr228 csr229 csr230 csr231
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csr232 csr233 csr234 csr235 csr236 csr237 csr238 csr239
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csr240 csr241 csr242 csr243 csr244 csr245 csr246 csr247
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csr248 csr249 csr250 csr251 csr252 csr253 csr254 csr255
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csr256 csr257 csr258 csr259 csr260 csr261 csr262 csr263
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];
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# Dummy registers for floating point comparison
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define register offset=0x5000 size=4 [
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FCMP1 FCMP2
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FCMP1 FCMP2
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];
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define register offset=0x5008 size=1 [
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@ -179,7 +179,7 @@ define register offset=0x5008 size=1 [
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];
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define register offset=0x5100 size=8 [
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DCMP1 DCMP2
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DCMP1 DCMP2
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];
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define register offset=0x5110 size=1 [
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@ -187,9 +187,9 @@ define register offset=0x5110 size=1 [
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];
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define register offset=0x50 size=4 contextreg;
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define context contextreg
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phase = (0,1)
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;
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phase = (0,1) ;
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define token instr(32)
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instword = ( 0,31)
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@ -224,9 +224,9 @@ define token instr(32)
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op0_4 = ( 0, 4)
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op0_31 = ( 0,31)
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ccf = (16,19)
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ccf_s = (15,15)
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ccf = (16,19)
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ccf_s = (15,15)
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simm5_20 = ( 5,24) signed
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simm5_13 = ( 5,17) signed
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simm10_9 = (10,18) signed
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@ -239,7 +239,7 @@ define token instr(32)
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simm10_10 = (10,19) signed
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simm0_5 = ( 0, 4) signed
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simm0_10 = ( 0, 9) signed
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rK = (10,14)
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rK32 = (10,14)
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@ -249,16 +249,16 @@ define token instr(32)
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rD = ( 0, 4)
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rD32 = ( 0, 4)
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xrK = (10,14)
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xrJ = ( 5, 9)
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xrD = ( 0, 4)
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xrA = (15,19)
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vrK = (10,14)
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vrJ = ( 5, 9)
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vrD = ( 0, 4)
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vrA = (15,19)
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xrK = (10,14)
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xrJ = ( 5, 9)
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xrD = ( 0, 4)
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xrA = (15,19)
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vrK = (10,14)
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vrJ = ( 5, 9)
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vrD = ( 0, 4)
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vrA = (15,19)
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lbtrJ = ( 5, 6)
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lbtrD = ( 0, 1)
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@ -272,9 +272,9 @@ define token instr(32)
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drD = ( 0, 4)
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drA = (15,19)
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fccJ = ( 5, 7)
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fccD = ( 0, 2)
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fccA = (15,17)
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fccJ = ( 5, 7)
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fccD = ( 0, 2)
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fccA = (15,17)
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imm5_5 = ( 5, 9)
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imm5_3 = ( 5, 7)
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@ -389,6 +389,7 @@ attach variables [xrD xrJ xrK xrA] [
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attach variables [ fccD fccJ fccA] [
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fcc0 fcc1 fcc2 fcc3 fcc4 fcc5 fcc6 fcc7
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];
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# Register subconstructors
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RD: rD is rD { export rD; }
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@ -421,13 +422,21 @@ RK32src: rK is rK & rK32 { export rK32; }
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RK32src: rK is rK & rK32=0 { export 0:4; }
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@if FREGSIZE == "8"
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FRD: drD is drD { export drD; }
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FRJ: drJ is drJ { export drJ; }
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FRK: drK is drK { export drK; }
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FRD: drD is drD { export drD; }
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FRJ: drJ is drJ { export drJ; }
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FRK: drK is drK { export drK; }
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@else
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FRD: frD is frD { export frD; }
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FRJ: frJ is frJ { export frJ; }
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FRK: frK is frK { export frK; }
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FRD: frD is frD { export frD; }
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FRJ: frJ is frJ { export frJ; }
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FRK: frK is frK { export frK; }
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@endif
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# Immediate operand sub-constructors
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@ -443,17 +452,21 @@ ldstx_addr: RJsrc(RKsrc) is RJsrc & RKsrc { local vaddr:$(REGSIZE) = RJsrc + RK
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pcadd2: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 2);] { export *[const]:$(REGSIZE) reloffs; }
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pcadd12: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; }
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pcala12: reloffs is simm5_20 [reloffs = (inst_start & ~0xfff) + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; }
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pcadd18: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 18);] { export *[const]:$(REGSIZE) reloffs; }
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Rel16: reloc is simm10_16 [ reloc = inst_start + (simm10_16 << 2); ] { export *:$(ADDRSIZE) reloc; }
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Rel16: reloc is simm10_16 [ reloc = inst_start + (simm10_16 << 2); ] { export *:$(ADDRSIZE) reloc; }
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Rel21: reloc is imm10_16 & simm0_5 [ reloc = inst_start + (((simm0_5 << 16) + imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; }
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Rel26: reloc is imm10_16 & simm0_10 [ reloc = inst_start + (((simm0_10 << 16) | imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; }
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RelJ16: RJsrc, simm10_16 is RJsrc & simm10_16 { local tmp:$(ADDRSIZE) = RJsrc + (simm10_16 << 2); export tmp; }
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simm12i: immed is simm5_20 [immed = simm5_20 << 12; ] { export *[const]:$(REGSIZE) immed; }
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simm32i: immed is simm5_20 [immed = simm5_20 << 32; ] { export *[const]:$(REGSIZE) immed; }
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simm52i: immed is simm10_12 [immed = simm10_12 << 52; ] { export *[const]:$(REGSIZE) immed; }
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# general pcodeops
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@ -57,7 +57,7 @@ seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; }
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#la-privileged-32.txt iocsrrd.b mask=0x06480000
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#0x06480000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0']
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:iocsrrd.b RD, RJsrc is op10_31=0x19200 & RD & RJsrc {
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local val:1 = iocsrrd(RJsrc, 1:1);
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local val:1 = *[iocsr]:1 RJsrc;
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RD = sext(val);
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}
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@ -65,7 +65,7 @@ seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; }
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#la-privileged-32.txt iocsrrd.h mask=0x06480400
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#0x06480400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0']
|
||||
:iocsrrd.h RD, RJsrc is op10_31=0x19201 & RD & RJsrc {
|
||||
local val:2 = iocsrrd(RJsrc, 2:1);
|
||||
local val:2 = *[iocsr]:2 RJsrc;
|
||||
RD = sext(val);
|
||||
}
|
||||
|
||||
@ -73,7 +73,7 @@ seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; }
|
||||
#la-privileged-32.txt iocsrrd.w mask=0x06480800
|
||||
#0x06480800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0']
|
||||
:iocsrrd.w RD, RJsrc is op10_31=0x19202 & RD & RJsrc {
|
||||
local val:4 = iocsrrd(RJsrc, 4:1);
|
||||
local val:4 = *[iocsr]:4 RJsrc;
|
||||
RD = sext(val);
|
||||
}
|
||||
|
||||
@ -81,22 +81,25 @@ seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; }
|
||||
|
||||
#la-privileged-32.txt iocsrwr.b mask=0x06481000
|
||||
#0x06481000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0']
|
||||
:iocsrwr.b RD, RJsrc is op10_31=0x19204 & RD & RJsrc {
|
||||
iocsrwr(RD, RJsrc, 1:1);
|
||||
:iocsrwr.b RDsrc, RJsrc is op10_31=0x19204 & RDsrc & RJsrc {
|
||||
local val:1 = RDsrc:1;
|
||||
*[iocsr]:1 RJsrc = val;
|
||||
}
|
||||
|
||||
|
||||
#la-privileged-32.txt iocsrwr.h mask=0x06481400
|
||||
#0x06481400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0']
|
||||
:iocsrwr.h RD, RJsrc is op10_31=0x19205 & RD & RJsrc {
|
||||
iocsrwr(RD, RJsrc, 2:1);
|
||||
:iocsrwr.h RDsrc, RJsrc is op10_31=0x19205 & RDsrc & RJsrc {
|
||||
local val:2= RDsrc:2;
|
||||
*[iocsr]:2 RJsrc = val;
|
||||
}
|
||||
|
||||
|
||||
#la-privileged-32.txt iocsrwr.w mask=0x06481800
|
||||
#0x06481800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0']
|
||||
:iocsrwr.w RD, RJsrc is op10_31=0x19206 & RD & RJsrc {
|
||||
iocsrwr(RD, RJsrc, 4:1);
|
||||
:iocsrwr.w RDsrc, RJsrc is op10_31=0x19206 & RDsrc & RJsrc {
|
||||
local val:4= RDsrc:4;
|
||||
*[iocsr]:4 RJsrc = val;
|
||||
}
|
||||
|
||||
|
||||
@ -152,7 +155,7 @@ define pcodeop ertn;
|
||||
#la-privileged-32.txt eret mask=0x06483800 [@orig_name=ertn, @primary]
|
||||
#0x06483800 0xffffffff
|
||||
:ertn is instword=0x06483800 {
|
||||
local ret = ertn();
|
||||
local ret:$(REGSIZE) = ertn();
|
||||
return [ret];
|
||||
}
|
||||
|
||||
|
||||
@ -1,14 +1,14 @@
|
||||
#la-privileged-64.txt iocsrrd.d mask=0x06480c00
|
||||
#0x06480c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0']
|
||||
:iocsrrd.d RD, RJsrc is op10_31=0x19203 & RD & RJsrc {
|
||||
RD = iocsrrd(RJsrc, 8:1);
|
||||
RD = *[iocsr]:8 RJsrc;
|
||||
}
|
||||
|
||||
|
||||
#la-privileged-64.txt iocsrwr.d mask=0x06481c00
|
||||
#0x06481c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0']
|
||||
:iocsrwr.d RD, RJsrc is op10_31=0x19207 & RD & RJsrc {
|
||||
iocsrwr(RD, RJsrc, 64:1);
|
||||
:iocsrwr.d RDsrc, RJsrc is op10_31=0x19207 & RDsrc & RJsrc {
|
||||
*[iocsr]:8 RJsrc = RDsrc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user