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Merge remote-tracking branch 'origin/GP-1763_ghidorahrex_PR-4011_astrelsky_arm_bfi'
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d3b189d8b2
@ -1344,12 +1344,13 @@ macro th_set_carry_for_asr(op1,shift_count) {
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Rd0811 = Rd0811 & clearMask;
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}
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:bfi^ItCond Rd0811,Rn0003,thLsbImm,thBitWidth is TMode=1 & ItCond & op4=0xf36 & Rn0003; thc1515=0 & Rd0811 & thc0505=0 & thLsbImm & thMsbImm & thBitWidth
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:bfi^ItCond Rd0811,Rn0003,thLsbImm,thBitWidth is TMode=1 & ItCond & op4=0xf36 & Rn0003; thc1515=0 & Rd0811 & thc0505=0 & thLsbImm & thBitWidth
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{
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build ItCond;
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clearMask:4 = (-1 << (thMsbImm + 1)) | (-1 >> (32 - thLsbImm));
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bits:4 = (Rn0003 << thLsbImm) & ~clearMask;
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Rd0811 = (Rd0811 & clearMask) | bits;
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vmask:4 = (1 << thBitWidth) - 1;
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clear:4 = ~(vmask << thLsbImm);
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bits:4 = (Rn0003 & vmask) << thLsbImm;
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Rd0811 = (Rd0811 & clear) | bits;
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}
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@endif # VERSION_6T2 || VERSION_7
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@ -2166,14 +2166,14 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate
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Rd = Rd & clearMask;
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}
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:bfi^COND Rd,Rm,lsbImm,bitWidth is $(AMODE) & COND & c2127=0x3e & msbImm & Rd & Rm & lsbImm & bitWidth & c0406=1 {
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:bfi^COND Rd,Rm,lsbImm,bitWidth is $(AMODE) & COND & c2127=0x3e & Rd & Rm & lsbImm & bitWidth & c0406=1 {
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build COND;
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build lsbImm;
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build msbImm;
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build bitWidth;
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clearMask:4 = (-1 << (msbImm + 1)) | (-1 >> (32 - lsbImm));
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bits:4 = (Rm << lsbImm) & ~clearMask;
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Rd = (Rd & clearMask) | bits;
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vmask:4 = (1 << bitWidth) - 1;
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clear:4 = ~(vmask << lsbImm);
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bits:4 = (Rm & vmask) << lsbImm;
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Rd = (Rd & clear) | bits;
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}
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@endif # VERSION_6T2
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