From e8151da0fcb2f99249be15bea95d8922b5866c1f Mon Sep 17 00:00:00 2001
From: ghidorahrex <ghidorahrex@users.noreply.github.com>
Date: Tue, 13 Jun 2023 16:52:05 +0000
Subject: [PATCH] GP-3181: Fixed HC05 ldefs and calling conventions for
 HC05/HCS08

---
 .../Processors/HCS08/certification.manifest   |  1 +
 .../HCS08/data/languages/HC05-M68HC05TB.pspec | 30 ++++-----
 .../HCS08/data/languages/HC05.cspec           | 38 ++++++++++++
 .../HCS08/data/languages/HC05.ldefs           |  8 +--
 .../HCS08/data/languages/HC05.pspec           | 12 ++--
 .../HCS08/data/languages/HCS08.cspec          | 61 ++++++++-----------
 .../HCS08/data/languages/HCS_HC.sinc          | 26 +++-----
 7 files changed, 99 insertions(+), 77 deletions(-)
 create mode 100644 Ghidra/Processors/HCS08/data/languages/HC05.cspec

diff --git a/Ghidra/Processors/HCS08/certification.manifest b/Ghidra/Processors/HCS08/certification.manifest
index 2a2f7ef95a..7da80ef97b 100644
--- a/Ghidra/Processors/HCS08/certification.manifest
+++ b/Ghidra/Processors/HCS08/certification.manifest
@@ -1,6 +1,7 @@
 ##VERSION: 2.0
 Module.manifest||GHIDRA||||END|
 data/languages/HC05-M68HC05TB.pspec||GHIDRA||||END|
+data/languages/HC05.cspec||GHIDRA||||END|
 data/languages/HC05.ldefs||GHIDRA||||END|
 data/languages/HC05.pspec||GHIDRA||||END|
 data/languages/HC05.slaspec||GHIDRA||||END|
diff --git a/Ghidra/Processors/HCS08/data/languages/HC05-M68HC05TB.pspec b/Ghidra/Processors/HCS08/data/languages/HC05-M68HC05TB.pspec
index ba3c607c46..333cbc4bf8 100644
--- a/Ghidra/Processors/HCS08/data/languages/HC05-M68HC05TB.pspec
+++ b/Ghidra/Processors/HCS08/data/languages/HC05-M68HC05TB.pspec
@@ -6,6 +6,7 @@
   <programcounter register="PC"/>
   <volatile outputop="write_volatile" inputop="read_volatile">
     <range space="RAM" first="0x0"    last="0x1F"/>
+    <range space="RAM" first="0x20"   last="0x8F"/>
   </volatile>
   <default_symbols>
     <symbol name="PORTA" address="0"/>
@@ -40,21 +41,22 @@
     <symbol name="Reserved_1D"  address="1D"/>
     <symbol name="Reserved_1E"  address="1E"/>
     <symbol name="Reserved_1F"  address="1F"/>
-    <symbol name="COP_Register"            address="1FF0" entry="true" type="code_ptr"/>
-    <symbol name="MaskOption"              address="1FF1" entry="true" type="code_ptr"/>
-    <symbol name="Reserved_1FF2"           address="1FF2" entry="true" type="code_ptr"/>
-    <symbol name="Reserved_1FF3"           address="1FF3" entry="true" type="code_ptr"/>
-    <symbol name="Reserved_1FF4"           address="1FF4" entry="true" type="code_ptr"/>
-    <symbol name="Reserved_1FF5"           address="1FF5" entry="true" type="code_ptr"/>
-    <symbol name="Reserved_1FF6"           address="1FF6" entry="true" type="code_ptr"/>
-    <symbol name="Reserved_1FF7"           address="1FF7" entry="true" type="code_ptr"/>
-    <symbol name="VECTOR_On-Chip_Timer"           address="1FF8" entry="true" type="code_ptr"/>
-    <symbol name="VECTOR_IRQ"                     address="1FFA" entry="true" type="code_ptr"/>
-    <symbol name="VECTOR_SWI"                     address="1FFC" entry="true" type="code_ptr"/>
-    <symbol name="VECTOR_Reset"                   address="1FFE" entry="true" type="code_ptr"/>
+    <symbol name="COP_Register"            address="07F0" entry="true" type="code_ptr"/>
+    <symbol name="MaskOption"              address="07F1" entry="true" type="code_ptr"/>
+    <symbol name="Reserved_07F2"           address="07F2" entry="true" type="code_ptr"/>
+    <symbol name="Reserved_07F3"           address="07F3" entry="true" type="code_ptr"/>
+    <symbol name="Reserved_07F4"           address="07F4" entry="true" type="code_ptr"/>
+    <symbol name="Reserved_07F5"           address="07F5" entry="true" type="code_ptr"/>
+    <symbol name="Reserved_07F6"           address="07F6" entry="true" type="code_ptr"/>
+    <symbol name="Reserved_07F7"           address="07F7" entry="true" type="code_ptr"/>
+    <symbol name="VECTOR_On-Chip_Timer"           address="07F8" entry="true" type="code_ptr"/>
+    <symbol name="VECTOR_IRQ"                     address="07FA" entry="true" type="code_ptr"/>
+    <symbol name="VECTOR_SWI"                     address="07FC" entry="true" type="code_ptr"/>
+    <symbol name="VECTOR_Reset"                   address="07FE" entry="true" type="code_ptr"/>
   </default_symbols>
   <default_memory_blocks>
-    <memory_block name="IO"      start_address="0"    length="0x20" initialized="false"/>
-    <memory_block name="LOW_RAM" start_address="0xC0" length="0x40" initialized="false"/>
+    <memory_block name="IO"       start_address="0"    length="0x20" initialized="false"/>
+    <memory_block name="USER_RAM" start_address="0x20" length="0x60" initialized="false"/>
+    <memory_block name="LOW_RAM"  start_address="0xC0" length="0x40" initialized="false"/>
   </default_memory_blocks>
 </processor_spec>
diff --git a/Ghidra/Processors/HCS08/data/languages/HC05.cspec b/Ghidra/Processors/HCS08/data/languages/HC05.cspec
new file mode 100644
index 0000000000..002e896f20
--- /dev/null
+++ b/Ghidra/Processors/HCS08/data/languages/HC05.cspec
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<compiler_spec>
+  <global>
+    <range space="RAM"/>
+  </global>
+  <stackpointer register="SP" space="RAM" growth="negative"/>
+  <returnaddress>
+    <varnode space="stack" offset="1" size="2"/>
+  </returnaddress>
+  <default_proto>
+  <prototype name="__stdcall" extrapop="2" stackshift="2" strategy="register">
+      <input>
+        <pentry minsize="1" maxsize="1">
+          <register name="A"/>
+        </pentry>
+        <pentry minsize="2" maxsize="2">
+          <addr space="join" piece1="X" piece2="A"/>
+        </pentry>
+        <pentry minsize="1" maxsize="500" align="1">
+          <addr offset="2" space="stack"/>
+        </pentry>
+      </input>
+      <output>
+        <pentry minsize="1" maxsize="1">
+          <register name="A"/>
+        </pentry>
+        <pentry minsize="2" maxsize="2">
+          <addr space="join" piece1="X" piece2="A"/>
+        </pentry>
+      </output>
+      <unaffected>
+        <register name="SP"/>
+        <register name="X"/>
+      </unaffected>
+  </prototype>
+  </default_proto>
+</compiler_spec>
diff --git a/Ghidra/Processors/HCS08/data/languages/HC05.ldefs b/Ghidra/Processors/HCS08/data/languages/HC05.ldefs
index 4caea38800..e0c26671f9 100644
--- a/Ghidra/Processors/HCS08/data/languages/HC05.ldefs
+++ b/Ghidra/Processors/HCS08/data/languages/HC05.ldefs
@@ -6,23 +6,23 @@
             size="16"
             variant="default"
             version="1.0"
-            slafile="HC08.sla"
+            slafile="HC05.sla"
             processorspec="HC05.pspec"
             manualindexfile="../manuals/HC05.idx"
             id="HC05:BE:16:default">
     <description>HC05 (6805) Microcontroller Family</description>
-    <compiler name="default" spec="HCS08.cspec" id="default"/>
+    <compiler name="default" spec="HC05.cspec" id="default"/>
   </language>
     <language processor="HC05"
             endian="big"
             size="16"
             variant="M68HC05TB"
             version="1.0"
-            slafile="HC08.sla"
+            slafile="HC05.sla"
             processorspec="HC05-M68HC05TB.pspec"
             manualindexfile="../manuals/HC05.idx"
             id="HC05:BE:16:M68HC05TB">
     <description>HC05 (6805) Microcontroller Family - M68HC05TB</description>
-    <compiler name="default" spec="HCS08.cspec" id="default"/>
+    <compiler name="default" spec="HC05.cspec" id="default"/>
   </language>
 </language_definitions>
diff --git a/Ghidra/Processors/HCS08/data/languages/HC05.pspec b/Ghidra/Processors/HCS08/data/languages/HC05.pspec
index 1b96212e9a..60c42e87ba 100644
--- a/Ghidra/Processors/HCS08/data/languages/HC05.pspec
+++ b/Ghidra/Processors/HCS08/data/languages/HC05.pspec
@@ -19,12 +19,12 @@
     <symbol name="SPCR"  address="A"/>
     <symbol name="SPSR"  address="B"/>
     <symbol name="SPDR"  address="C"/>
-    <symbol name="COP_Register"            address="1FF0" entry="true" type="code_ptr"/>
-    <symbol name="MaskOption"              address="1FF1" entry="true" type="code_ptr"/>
-    <symbol name="VECTOR_On-Chip_Timer"           address="1FF8" entry="true" type="code_ptr"/>
-    <symbol name="VECTOR_IRQ"                     address="1FFA" entry="true" type="code_ptr"/>
-    <symbol name="VECTOR_SWI"                     address="1FFC" entry="true" type="code_ptr"/>
-    <symbol name="VECTOR_Reset"                   address="1FFE" entry="true" type="code_ptr"/>
+    <symbol name="COP_Register"            address="7F0" entry="true" type="code_ptr"/>
+    <symbol name="MaskOption"              address="7F1" entry="true" type="code_ptr"/>
+    <symbol name="VECTOR_On-Chip_Timer"           address="7F8" entry="true" type="code_ptr"/>
+    <symbol name="VECTOR_IRQ"                     address="7FA" entry="true" type="code_ptr"/>
+    <symbol name="VECTOR_SWI"                     address="7FC" entry="true" type="code_ptr"/>
+    <symbol name="VECTOR_Reset"                   address="7FE" entry="true" type="code_ptr"/>
   </default_symbols>
   <default_memory_blocks>
     <memory_block name="IO"      start_address="0"    length="0x20" initialized="false"/>
diff --git a/Ghidra/Processors/HCS08/data/languages/HCS08.cspec b/Ghidra/Processors/HCS08/data/languages/HCS08.cspec
index f0c0752202..451d0d541d 100644
--- a/Ghidra/Processors/HCS08/data/languages/HCS08.cspec
+++ b/Ghidra/Processors/HCS08/data/languages/HCS08.cspec
@@ -6,45 +6,32 @@
   </global>
   <stackpointer register="SP" space="RAM" growth="negative"/>
   <returnaddress>
-    <varnode space="stack" offset="0" size="2"/>
+    <varnode space="stack" offset="1" size="2"/>
   </returnaddress>
   <default_proto>
-    <prototype name="__fastcall" extrapop="2" stackshift="2">
-      <input>
-        <pentry minsize="1" maxsize="1">
-          <register name="A"/>
-        </pentry>
-      </input>
-      <output>
-        <pentry minsize="1" maxsize="1">
-          <register name="A"/>
-        </pentry>
-      </output>
-      <unaffected>
-        <register name="SP"/>
-        <register name="HIX"/>
-      </unaffected>
+    <prototype name="__stdcall" extrapop="2" stackshift="2" strategy="register">
+        <input>
+          <pentry minsize="1" maxsize="1">
+            <register name="A"/>
+          </pentry>
+          <pentry minsize="2" maxsize="2">
+            <register name="HIX"/>
+          </pentry>
+          <pentry minsize="1" maxsize="500" align="1">
+            <addr offset="3" space="stack"/>
+          </pentry>
+        </input>
+        <output>
+          <pentry minsize="1" maxsize="1">
+            <register name="A"/>
+          </pentry>
+          <pentry minsize="2" maxsize="2">
+            <register name="HIX"/>
+          </pentry>
+        </output>
+        <unaffected>
+          <register name="SP"/>
+        </unaffected>
     </prototype>
   </default_proto>
-  <prototype name="__stdcall" extrapop="2" stackshift="2">
-	  <input>
-	    <pentry minsize="1" maxsize="500" align="1">
-	      <addr offset="3" space="stack"/>
-	    </pentry>
-	  </input>
-	  <output>
-	    <pentry minsize="1" maxsize="1">
-	      <register name="A"/>
-	    </pentry>
-	  </output>
-	  <unaffected>
-	    <register name="SP"/>
-	    <register name="HIX"/>
-	  </unaffected>
-  </prototype>
-  <resolveprototype name="__fastcall/__stdcall">
-     <model name="__stdcall"/>      <!-- The default case -->
-     <model name="__fastcall"/>
-  </resolveprototype>
-  <eval_current_prototype name="__fastcall/__stdcall"/>
 </compiler_spec>
diff --git a/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc b/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc
index 567207d182..3e6d10db34 100644
--- a/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc
+++ b/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc
@@ -108,25 +108,26 @@ oprx16_8_SP:	imm16,SP is imm16 & SP { address:2 = SP  + imm16:2;      export *:1
 
 @if  defined(HCS08)
 opr16a_16:	    imm16    is imm16      { export *:2 imm16; }
-oprx8_16_SP:	imm8,SP  is imm8 & SP  { address:2 = SP  + zext(imm8:1); export *:2 address; }
+oprx8_16_SP:	imm8,SP  is imm8 & SP  { address:2 = SP  + imm8;  export *:2 address; }
 @endif
 
 # X or HIX addressing
 
 @if defined(HC05)
-oprx8_8_X:		imm8,X   is imm8 & X   { address:1 = X   + imm8:1;       export *:1 address; }
-comma_X:		","X     is X		   { address:1 = X;                  export *:1 address; }
+oprx8_8_X:		imm8,X   is imm8 & X   { address:2 = zext(X) + imm8;   export *:1 address; }
+oprx16_8_X:		imm16,X  is imm16 & X  { address:2 = zext(X) + imm16;  export *:1 address; }
+comma_X:		","X     is X		   { address:2 = zext(X);          export *:1 address; }
 @endif
 
 @if defined(HCS08) || defined(HC08)
-oprx8_8_X:		imm8,X   is imm8 & X   { address:2 = HIX + zext(imm8:1); export *:1 address; }
-oprx16_8_X:		imm16,X  is imm16 & X  { address:2 = HIX + imm16:2;      export *:1 address; }
-comma_X:		","X     is X		   { address:2 = HIX;                export *:1 address; }
+oprx8_8_X:		imm8,X   is imm8 & X   { address:2 = HIX + imm8;       export *:1 address; }
+oprx16_8_X:		imm16,X  is imm16 & X  { address:2 = HIX + imm16;      export *:1 address; }
+comma_X:		","X     is X		   { address:2 = HIX;              export *:1 address; }
 @endif
 
 @if  defined(HCS08)
-oprx8_16_X:		imm8,X   is imm8 & X   { address:2 = HIX + zext(imm8:1); export *:2 address; }
-oprx16_16_X:	imm16,X  is imm16 & X  { address:2 = HIX + imm16:2;      export *:2 address; }
+oprx8_16_X:		imm8,X   is imm8 & X   { address:2 = HIX + imm8;       export *:2 address; }
+oprx16_16_X:	imm16,X  is imm16 & X  { address:2 = HIX + imm16;      export *:2 address; }
 @endif
 
 
@@ -135,11 +136,7 @@ oprx16_16_X:	imm16,X  is imm16 & X  { address:2 = HIX + imm16:2;      export *:2
 OP1: iopr8i		is op4_6=2; iopr8i       { export iopr8i; }
 OP1: opr8a_8	is op4_6=3; opr8a_8      { export opr8a_8; }
 OP1: opr16a_8	is op4_6=4; opr16a_8     { export opr16a_8; }
-
-@if defined(HCS08) || defined(HC08)
 OP1: oprx16_8_X	is op4_6=5; oprx16_8_X   { export oprx16_8_X; }
-@endif
-
 OP1: oprx8_8_X	is op4_6=6; oprx8_8_X    { export oprx8_8_X; }
 OP1: comma_X	is op4_6=7 & comma_X     { export comma_X; }
 
@@ -151,10 +148,7 @@ op2_opr8a: imm8     is imm8       { export *:1 imm8; }
 ADDR: opr8a_8		is op4_6=3; opr8a_8		{ export opr8a_8; }
 ADDR: opr16a_8		is op4_6=4; opr16a_8	{ export opr16a_8; }
 
-@if defined(HCS08) || defined(HC08)
 ADDRI: oprx16_8_X	is op4_6=5; oprx16_8_X	{ export oprx16_8_X; }
-@endif
-
 ADDRI: oprx8_8_X	is op4_6=6; oprx8_8_X	{ export oprx8_8_X; }
 ADDRI: comma_X		is op4_6=7 & comma_X	{ export comma_X; }
 
@@ -1772,7 +1766,7 @@ macro Push2(operand) {
 @if  defined(HCS08) || defined(HC08) || defined(HC05)
 :RSP                     is op = 0x9C
 {
-	SPL = 0xff;
+	SP = 0xff;
 }
 @endif