diff --git a/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
index baf5902ddf58..c6ed48967291 100644
--- a/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
@@ -84,7 +84,7 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
       return;
     }
   }
-  
+
   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
     O << "\tmr ";
@@ -94,7 +94,7 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
     printAnnotation(O, Annot);
     return;
   }
-  
+
   if (MI->getOpcode() == PPC::RLDICR ||
       MI->getOpcode() == PPC::RLDICR_32) {
     unsigned char SH = MI->getOperand(2).getImm();
@@ -161,7 +161,7 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
       return;
     }
   }
-  
+
   if (!printAliasInstr(MI, O))
     printInstruction(MI, O);
   printAnnotation(O, Annot);
@@ -259,7 +259,7 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
     }
     llvm_unreachable("Invalid predicate code");
   }
-  
+
   assert(StringRef(Modifier) == "reg" &&
          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
   printOperand(MI, OpNo+1, O);
@@ -448,9 +448,24 @@ void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
 
 /// stripRegisterPrefix - This method strips the character prefix from a
 /// register name so that only the number is left.  Used by for linux asm.
-static const char *stripRegisterPrefix(const char *RegName) {
-  if (FullRegNames || ShowVSRNumsAsVR)
+static const char *stripRegisterPrefix(const char *RegName, unsigned RegNum,
+                                       unsigned RegEncoding) {
+  if (FullRegNames) {
+    if (RegNum >= PPC::CR0EQ && RegNum <= PPC::CR7UN) {
+      const char *CRBits[] =
+      { "lt", "gt", "eq", "un",
+        "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
+        "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
+        "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
+        "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
+        "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
+        "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
+        "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
+      };
+      return CRBits[RegEncoding];
+    }
     return RegName;
+  }
 
   switch (RegName[0]) {
   case 'r':
@@ -462,7 +477,7 @@ static const char *stripRegisterPrefix(const char *RegName) {
     return RegName + 1;
   case 'c': if (RegName[1] == 'r') return RegName + 2;
   }
-  
+
   return RegName;
 }
 
@@ -490,17 +505,17 @@ void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
     const char *RegName = getRegisterName(Reg);
     // The linux and AIX assembler does not take register prefixes.
     if (!isDarwinSyntax())
-      RegName = stripRegisterPrefix(RegName);
-    
+      RegName = stripRegisterPrefix(RegName, Reg, MRI.getEncodingValue(Reg));
+
     O << RegName;
     return;
   }
-  
+
   if (Op.isImm()) {
     O << Op.getImm();
     return;
   }
-  
+
   assert(Op.isExpr() && "unknown operand kind in printOperand");
   Op.getExpr()->print(O, &MAI);
 }
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
index 3ad432872c0e..d71460b8d9a8 100644
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -1,11 +1,15 @@
-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \
-; RUN:   < %s | FileCheck %s -check-prefix=P9BE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN:   < %s | FileCheck %s -check-prefix=P9LE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \
-; RUN:   < %s | FileCheck %s -check-prefix=P8BE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN:   < %s | FileCheck %s -check-prefix=P8LE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P9BE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P9LE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P8BE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P8LE -implicit-check-not frsp
 
 ; This test case comes from the following C test case (included as it may be
 ; slightly more readable than the LLVM IR.
diff --git a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
index 5fe69ebcf58e..a8ed09c18974 100644
--- a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
@@ -122,7 +122,7 @@ _ZNK4llvm9StringRef6substrEmm.exit:               ; preds = %_ZNK4llvm9StringRef
 ; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
 ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
 ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel.ll b/llvm/test/CodeGen/PowerPC/expand-isel.ll
index c8707bda8e84..608f0367cbc5 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-isel.ll
@@ -12,7 +12,7 @@ entry:
 ; CHECK-LABEL: @testExpandISELToIfElse
 ; CHECK: addi r5, r3, 1
 ; CHECK-NEXT: cmpwi cr0, r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
@@ -32,7 +32,7 @@ entry:
 
 ; CHECK-LABEL: @testExpandISELToIf
 ; CHECK: cmpwi	 r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: blr
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r4, 0
@@ -48,7 +48,7 @@ entry:
 
 ; CHECK-LABEL: @testExpandISELToElse
 ; CHECK: cmpwi	 r3, 0
-; CHECK-NEXT: bclr 12, 1, 0
+; CHECK-NEXT: bclr 12, gt, 0
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: blr
 }
@@ -95,7 +95,7 @@ entry:
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs
 ; CHECK: cmpwi r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r12, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@@ -121,7 +121,7 @@ entry:
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r12, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@@ -148,7 +148,7 @@ entry:
 
 ; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r5, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
@@ -176,7 +176,7 @@ entry:
 
 ; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r4, r3, 0
diff --git a/llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll b/llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll
index 5a507e9ff678..7da978990bac 100644
--- a/llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll
+++ b/llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll
@@ -18,7 +18,7 @@ define signext i32 @logic_ne_32(i32 signext %a, i32 signext %b, i32 signext %c)
 ; CHECK-NEXT:    srwi r6, r6, 5
 ; CHECK-NEXT:    srwi r5, r5, 5
 ; CHECK-NEXT:    or. r5, r6, r5
-; CHECK-NEXT:    bc 4, 1
+; CHECK-NEXT:    bc 4, gt
 entry:
   %tobool = icmp eq i32 %a, %b
   %tobool1 = icmp eq i32 %b, 0
@@ -45,7 +45,7 @@ define void @neg_truncate_i32_eq(i32 *%ptr) {
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
 ; CHECK-NEXT:    rldicl. r3, r3, 0, 63
-; CHECK-NEXT:    bclr 12, 2, 0
+; CHECK-NEXT:    bclr 12, eq, 0
 ; CHECK-NEXT:  # BB#1: # %if.end29.thread136
 ; CHECK-NEXT:  .LBB1_2: # %if.end29
 entry:
@@ -77,7 +77,7 @@ define i64 @logic_eq_64(i64 %a, i64 %b, i64 %c) {
 ; CHECK-NEXT:    rldicl r6, r6, 58, 63
 ; CHECK-NEXT:    rldicl r5, r5, 58, 63
 ; CHECK-NEXT:    or. r5, r6, r5
-; CHECK-NEXT:    bc 4, 1
+; CHECK-NEXT:    bc 4, gt
 entry:
   %tobool = icmp eq i64 %a, %b
   %tobool1 = icmp eq i64 %b, 0
@@ -104,7 +104,7 @@ define void @neg_truncate_i64_eq(i64 *%ptr) {
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    rldicl. r3, r3, 0, 63
-; CHECK-NEXT:    bclr 12, 2, 0
+; CHECK-NEXT:    bclr 12, eq, 0
 ; CHECK-NEXT:  # BB#1: # %if.end29.thread136
 ; CHECK-NEXT:  .LBB3_2: # %if.end29
 entry:
@@ -138,7 +138,7 @@ define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) {
 ; CHECK-NEXT:    subfe r6, r12, r4
 ; CHECK-NEXT:    and r6, r7, r6
 ; CHECK-NEXT:    or. r5, r6, r5
-; CHECK-NEXT:    bc 4, 1
+; CHECK-NEXT:    bc 4, gt
 entry:
   %tobool = icmp ne i64 %a, %b
   %tobool1 = icmp ne i64 %b, 0
@@ -165,7 +165,7 @@ define void @neg_truncate_i64_ne(i64 *%ptr) {
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    andi. r3, r3, 1
-; CHECK-NEXT:    bclr 12, 1, 0
+; CHECK-NEXT:    bclr 12, gt, 0
 ; CHECK-NEXT:  # BB#1: # %if.end29.thread136
 ; CHECK-NEXT:  .LBB5_2: # %if.end29
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/mtvsrdd.ll b/llvm/test/CodeGen/PowerPC/mtvsrdd.ll
index 1d6a3553b2a1..a4a3d829f2d3 100644
--- a/llvm/test/CodeGen/PowerPC/mtvsrdd.ll
+++ b/llvm/test/CodeGen/PowerPC/mtvsrdd.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN:   < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 
 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
 
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
index 6d19d7f0d629..f5319b24d457 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
@@ -20,8 +20,8 @@
 ; RUN:   FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd
 
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:   -mcpu=pwr9 -ppc-vsr-nums-as-vr < %s | FileCheck %s \
-; RUN:   -check-prefix=CHECK-P9 --implicit-check-not xxswapd
+; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd
 
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \