mirror of
https://github.com/capstone-engine/llvm-capstone.git
synced 2024-11-27 15:41:46 +00:00
[RISCV] Fix typo, use addImm instead of addReg.
This commit is contained in:
parent
d47dd11071
commit
020df692d8
@ -1391,7 +1391,7 @@ Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
|
||||
uint32_t ShiftAmount = Log2_32(NumOfVReg + 1);
|
||||
BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), ScaledRegister)
|
||||
.addReg(VL)
|
||||
.addReg(ShiftAmount);
|
||||
.addImm(ShiftAmount);
|
||||
BuildMI(MBB, II, DL, TII->get(RISCV::SUB), VL)
|
||||
.addReg(ScaledRegister, RegState::Kill)
|
||||
.addReg(VL, RegState::Kill);
|
||||
|
@ -304,7 +304,7 @@ define void @lmul_1_2_4_8() nounwind {
|
||||
; CHECK-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
|
||||
; CHECK-NEXT: addi s0, sp, 64
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: slli a1, a0, vl
|
||||
; CHECK-NEXT: slli a1, a0, 4
|
||||
; CHECK-NEXT: sub a0, a1, a0
|
||||
; CHECK-NEXT: sub sp, sp, a0
|
||||
; CHECK-NEXT: andi sp, sp, -64
|
||||
|
Loading…
Reference in New Issue
Block a user