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https://github.com/capstone-engine/llvm-capstone.git
synced 2024-11-27 23:51:56 +00:00
[RISCV] Group the legal vector types into lists we can iterator over in the RISCVISelLowering constructor
Remove the RISCVVMVTs namespace because I don't think it provides a lot of value. If we change the mappings we'd likely have to add or remove things from the list anyway. Add a wrapper around addRegisterClass that can determine the register class from the fixed size of the type. Reviewed By: frasercrmck, rogfer01 Differential Revision: https://reviews.llvm.org/D95491
This commit is contained in:
Craig Topper
parent
f30c523660
commit
04570e98c8
@ -18,7 +18,6 @@
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/MachineValueType.h"
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namespace llvm {
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@ -257,62 +256,6 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits);
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} // namespace RISCVFeatures
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namespace RISCVVMVTs {
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constexpr MVT vint8mf8_t = MVT::nxv1i8;
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constexpr MVT vint8mf4_t = MVT::nxv2i8;
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constexpr MVT vint8mf2_t = MVT::nxv4i8;
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constexpr MVT vint8m1_t = MVT::nxv8i8;
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constexpr MVT vint8m2_t = MVT::nxv16i8;
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constexpr MVT vint8m4_t = MVT::nxv32i8;
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constexpr MVT vint8m8_t = MVT::nxv64i8;
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constexpr MVT vint16mf4_t = MVT::nxv1i16;
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constexpr MVT vint16mf2_t = MVT::nxv2i16;
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constexpr MVT vint16m1_t = MVT::nxv4i16;
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constexpr MVT vint16m2_t = MVT::nxv8i16;
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constexpr MVT vint16m4_t = MVT::nxv16i16;
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constexpr MVT vint16m8_t = MVT::nxv32i16;
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constexpr MVT vint32mf2_t = MVT::nxv1i32;
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constexpr MVT vint32m1_t = MVT::nxv2i32;
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constexpr MVT vint32m2_t = MVT::nxv4i32;
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constexpr MVT vint32m4_t = MVT::nxv8i32;
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constexpr MVT vint32m8_t = MVT::nxv16i32;
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constexpr MVT vint64m1_t = MVT::nxv1i64;
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constexpr MVT vint64m2_t = MVT::nxv2i64;
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constexpr MVT vint64m4_t = MVT::nxv4i64;
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constexpr MVT vint64m8_t = MVT::nxv8i64;
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constexpr MVT vfloat16mf4_t = MVT::nxv1f16;
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constexpr MVT vfloat16mf2_t = MVT::nxv2f16;
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constexpr MVT vfloat16m1_t = MVT::nxv4f16;
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constexpr MVT vfloat16m2_t = MVT::nxv8f16;
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constexpr MVT vfloat16m4_t = MVT::nxv16f16;
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constexpr MVT vfloat16m8_t = MVT::nxv32f16;
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constexpr MVT vfloat32mf2_t = MVT::nxv1f32;
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constexpr MVT vfloat32m1_t = MVT::nxv2f32;
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constexpr MVT vfloat32m2_t = MVT::nxv4f32;
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constexpr MVT vfloat32m4_t = MVT::nxv8f32;
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constexpr MVT vfloat32m8_t = MVT::nxv16f32;
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constexpr MVT vfloat64m1_t = MVT::nxv1f64;
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constexpr MVT vfloat64m2_t = MVT::nxv2f64;
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constexpr MVT vfloat64m4_t = MVT::nxv4f64;
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constexpr MVT vfloat64m8_t = MVT::nxv8f64;
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constexpr MVT vbool1_t = MVT::nxv64i1;
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constexpr MVT vbool2_t = MVT::nxv32i1;
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constexpr MVT vbool4_t = MVT::nxv16i1;
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constexpr MVT vbool8_t = MVT::nxv8i1;
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constexpr MVT vbool16_t = MVT::nxv4i1;
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constexpr MVT vbool32_t = MVT::nxv2i1;
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constexpr MVT vbool64_t = MVT::nxv1i1;
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} // namespace RISCVVMVTs
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enum class RISCVVSEW {
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SEW_8 = 0,
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SEW_16,
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@ -90,64 +90,56 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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if (Subtarget.hasStdExtD())
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addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
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static const MVT::SimpleValueType BoolVecVTs[] = {
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MVT::nxv1i1, MVT::nxv2i1, MVT::nxv4i1, MVT::nxv8i1,
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MVT::nxv16i1, MVT::nxv32i1, MVT::nxv64i1};
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static const MVT::SimpleValueType IntVecVTs[] = {
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MVT::nxv1i8, MVT::nxv2i8, MVT::nxv4i8, MVT::nxv8i8, MVT::nxv16i8,
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MVT::nxv32i8, MVT::nxv64i8, MVT::nxv1i16, MVT::nxv2i16, MVT::nxv4i16,
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MVT::nxv8i16, MVT::nxv16i16, MVT::nxv32i16, MVT::nxv1i32, MVT::nxv2i32,
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MVT::nxv4i32, MVT::nxv8i32, MVT::nxv16i32, MVT::nxv1i64, MVT::nxv2i64,
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MVT::nxv4i64, MVT::nxv8i64};
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static const MVT::SimpleValueType F16VecVTs[] = {
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MVT::nxv1f16, MVT::nxv2f16, MVT::nxv4f16,
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MVT::nxv8f16, MVT::nxv16f16, MVT::nxv32f16};
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static const MVT::SimpleValueType F32VecVTs[] = {
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MVT::nxv1f32, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv8f32, MVT::nxv16f32};
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static const MVT::SimpleValueType F64VecVTs[] = {
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MVT::nxv1f64, MVT::nxv2f64, MVT::nxv4f64, MVT::nxv8f64};
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if (Subtarget.hasStdExtV()) {
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addRegisterClass(RISCVVMVTs::vbool64_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vbool32_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vbool16_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vbool8_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vbool4_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vbool2_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vbool1_t, &RISCV::VRRegClass);
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auto addRegClassForRVV = [this](MVT VT) {
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unsigned Size = VT.getSizeInBits().getKnownMinValue();
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assert(Size <= 512 && isPowerOf2_32(Size));
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const TargetRegisterClass *RC;
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if (Size <= 64)
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RC = &RISCV::VRRegClass;
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else if (Size == 128)
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RC = &RISCV::VRM2RegClass;
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else if (Size == 256)
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RC = &RISCV::VRM4RegClass;
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else
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RC = &RISCV::VRM8RegClass;
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addRegisterClass(RISCVVMVTs::vint8mf8_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint8mf4_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint8mf2_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint8m1_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint8m2_t, &RISCV::VRM2RegClass);
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addRegisterClass(RISCVVMVTs::vint8m4_t, &RISCV::VRM4RegClass);
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addRegisterClass(RISCVVMVTs::vint8m8_t, &RISCV::VRM8RegClass);
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addRegisterClass(VT, RC);
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};
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addRegisterClass(RISCVVMVTs::vint16mf4_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint16mf2_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint16m1_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint16m2_t, &RISCV::VRM2RegClass);
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addRegisterClass(RISCVVMVTs::vint16m4_t, &RISCV::VRM4RegClass);
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addRegisterClass(RISCVVMVTs::vint16m8_t, &RISCV::VRM8RegClass);
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for (MVT VT : BoolVecVTs)
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addRegClassForRVV(VT);
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for (MVT VT : IntVecVTs)
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addRegClassForRVV(VT);
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addRegisterClass(RISCVVMVTs::vint32mf2_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint32m1_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint32m2_t, &RISCV::VRM2RegClass);
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addRegisterClass(RISCVVMVTs::vint32m4_t, &RISCV::VRM4RegClass);
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addRegisterClass(RISCVVMVTs::vint32m8_t, &RISCV::VRM8RegClass);
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if (Subtarget.hasStdExtZfh())
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for (MVT VT : F16VecVTs)
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addRegClassForRVV(VT);
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addRegisterClass(RISCVVMVTs::vint64m1_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vint64m2_t, &RISCV::VRM2RegClass);
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addRegisterClass(RISCVVMVTs::vint64m4_t, &RISCV::VRM4RegClass);
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addRegisterClass(RISCVVMVTs::vint64m8_t, &RISCV::VRM8RegClass);
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if (Subtarget.hasStdExtF())
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for (MVT VT : F32VecVTs)
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addRegClassForRVV(VT);
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if (Subtarget.hasStdExtZfh()) {
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addRegisterClass(RISCVVMVTs::vfloat16mf4_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vfloat16mf2_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vfloat16m1_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vfloat16m2_t, &RISCV::VRM2RegClass);
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addRegisterClass(RISCVVMVTs::vfloat16m4_t, &RISCV::VRM4RegClass);
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addRegisterClass(RISCVVMVTs::vfloat16m8_t, &RISCV::VRM8RegClass);
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}
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if (Subtarget.hasStdExtF()) {
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addRegisterClass(RISCVVMVTs::vfloat32mf2_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vfloat32m1_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vfloat32m2_t, &RISCV::VRM2RegClass);
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addRegisterClass(RISCVVMVTs::vfloat32m4_t, &RISCV::VRM4RegClass);
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addRegisterClass(RISCVVMVTs::vfloat32m8_t, &RISCV::VRM8RegClass);
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}
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if (Subtarget.hasStdExtD()) {
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addRegisterClass(RISCVVMVTs::vfloat64m1_t, &RISCV::VRRegClass);
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addRegisterClass(RISCVVMVTs::vfloat64m2_t, &RISCV::VRM2RegClass);
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addRegisterClass(RISCVVMVTs::vfloat64m4_t, &RISCV::VRM4RegClass);
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addRegisterClass(RISCVVMVTs::vfloat64m8_t, &RISCV::VRM8RegClass);
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}
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if (Subtarget.hasStdExtD())
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for (MVT VT : F64VecVTs)
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addRegClassForRVV(VT);
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}
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// Compute derived properties from the register classes.
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@ -379,9 +371,22 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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if (Subtarget.is64Bit()) {
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
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} else {
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// We must custom-lower certain vXi64 operations on RV32 due to the vector
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// element type being illegal.
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setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::i64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i64, Custom);
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}
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for (auto VT : MVT::integer_scalable_vector_valuetypes()) {
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for (MVT VT : BoolVecVTs) {
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setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
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// Mask VTs are custom-expanded into a series of standard nodes
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setOperationAction(ISD::TRUNCATE, VT, Custom);
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}
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for (MVT VT : IntVecVTs) {
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setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
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setOperationAction(ISD::SMIN, VT, Legal);
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@ -392,30 +397,18 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::ROTL, VT, Expand);
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setOperationAction(ISD::ROTR, VT, Expand);
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if (isTypeLegal(VT)) {
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// Custom-lower extensions and truncations from/to mask types.
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setOperationAction(ISD::ANY_EXTEND, VT, Custom);
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setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
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setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
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// Custom-lower extensions and truncations from/to mask types.
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setOperationAction(ISD::ANY_EXTEND, VT, Custom);
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setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
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setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
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// We custom-lower all legally-typed vector truncates:
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// 1. Mask VTs are custom-expanded into a series of standard nodes
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// 2. Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR"
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// nodes which truncate by one power of two at a time.
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setOperationAction(ISD::TRUNCATE, VT, Custom);
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// Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR"
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// nodes which truncate by one power of two at a time.
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setOperationAction(ISD::TRUNCATE, VT, Custom);
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// Custom-lower insert/extract operations to simplify patterns.
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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}
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}
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// We must custom-lower certain vXi64 operations on RV32 due to the vector
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// element type being illegal.
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if (!Subtarget.is64Bit()) {
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setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::i64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i64, Custom);
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// Custom-lower insert/extract operations to simplify patterns.
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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}
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// Expand various CCs to best match the RVV ISA, which natively supports UNE
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@ -441,25 +434,17 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setCondCodeAction(CC, VT, Expand);
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};
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if (Subtarget.hasStdExtZfh()) {
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for (auto VT : {RISCVVMVTs::vfloat16mf4_t, RISCVVMVTs::vfloat16mf2_t,
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RISCVVMVTs::vfloat16m1_t, RISCVVMVTs::vfloat16m2_t,
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RISCVVMVTs::vfloat16m4_t, RISCVVMVTs::vfloat16m8_t})
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if (Subtarget.hasStdExtZfh())
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for (MVT VT : F16VecVTs)
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SetCommonVFPActions(VT);
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}
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if (Subtarget.hasStdExtF()) {
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for (auto VT : {RISCVVMVTs::vfloat32mf2_t, RISCVVMVTs::vfloat32m1_t,
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RISCVVMVTs::vfloat32m2_t, RISCVVMVTs::vfloat32m4_t,
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RISCVVMVTs::vfloat32m8_t})
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if (Subtarget.hasStdExtF())
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for (MVT VT : F32VecVTs)
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SetCommonVFPActions(VT);
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}
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if (Subtarget.hasStdExtD()) {
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for (auto VT : {RISCVVMVTs::vfloat64m1_t, RISCVVMVTs::vfloat64m2_t,
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RISCVVMVTs::vfloat64m4_t, RISCVVMVTs::vfloat64m8_t})
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if (Subtarget.hasStdExtD())
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for (MVT VT : F64VecVTs)
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SetCommonVFPActions(VT);
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}
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}
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// Function alignments.
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