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[Hexagon] Make p0 an explicit operand in VA1_clr* subinstructions, NFC

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llvm-svn: 279255
This commit is contained in:
Krzysztof Parzyszek 2016-08-19 15:17:19 +00:00
parent 6ce82951c3
commit 0b8672269c
2 changed files with 15 additions and 10 deletions
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20
llvm/lib/Target/Hexagon/HexagonIsetDx.td
View File

@ -93,8 +93,8 @@ def V4_SS2_storebi0: SUBInst <
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_clrtnew: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"if (p0.new) $Rd = #0"> {
(ins PredRegs:$Pu),
"if ($Pu.new) $Rd = #0"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
@ -336,7 +336,7 @@ let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_setin1: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"$Rd = #-1"> {
"$Rd = #{-1}"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
@ -409,8 +409,8 @@ def V4_SA1_sxtb: SUBInst <
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_clrf: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"if (!p0) $Rd = #0"> {
(ins PredRegs:$Pu),
"if (!$Pu) $Rd = #0"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
@ -547,8 +547,8 @@ def V4_SL2_jumpr31_fnew: SUBInst <
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_clrt: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"if (p0) $Rd = #0"> {
(ins PredRegs:$Pu),
"if ($Pu) $Rd = #0"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
@ -571,7 +571,7 @@ let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_dec: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = add($Rs,#-1)"> {
"$Rd = add($Rs,#{-1})"> {
bits<4> Rd;
bits<4> Rs;
@ -609,8 +609,8 @@ def V4_SL2_jumpr31_t: SUBInst <
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_clrfnew: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"if (!p0.new) $Rd = #0"> {
(ins PredRegs:$Pu),
"if (!$Pu.new) $Rd = #0"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;

5
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
View File

@ -673,6 +673,7 @@ inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
case Hexagon::D9:
case Hexagon::D10:
case Hexagon::D11:
case Hexagon::P0:
subInstPtr.addOperand(Inst.getOperand(opNum));
break;
}
@ -943,18 +944,22 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
case Hexagon::C2_cmovenewif:
Result.setOpcode(Hexagon::V4_SA1_clrfnew);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (!p0.new) $Rd = #0
case Hexagon::C2_cmovenewit:
Result.setOpcode(Hexagon::V4_SA1_clrtnew);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (p0.new) $Rd = #0
case Hexagon::C2_cmoveif:
Result.setOpcode(Hexagon::V4_SA1_clrf);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (!p0) $Rd = #0
case Hexagon::C2_cmoveit:
Result.setOpcode(Hexagon::V4_SA1_clrt);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (p0) $Rd = #0
case Hexagon::A2_tfrsi:
Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);