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Remove bit-rotten CppBackend.

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This backend was supposed to generate C++ code which will re-construct
the LLVM IR passed as input. This seems to me to have very marginal
usefulness in the first place.

However, the code has never been updated to use IRBuilder, which makes
its current value negative -- people who look at the output may be
steered to use the *wrong* C++ APIs to construct IR.

Furthermore, it's generated code that doesn't compile since at least
2013.

Differential Revision: http://reviews.llvm.org/D19942

llvm-svn: 268631
This commit is contained in:
James Y Knight 2016-05-05 14:35:40 +00:00
parent 996fc133b7
commit 0c145c0c3a
20 changed files with 8 additions and 2457 deletions
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1
llvm/CMakeLists.txt
View File

@ -226,7 +226,6 @@ set(LLVM_ALL_TARGETS
AMDGPU
ARM
BPF
CppBackend
Hexagon
Mips
MSP430

12
llvm/docs/CodeGenerator.rst
View File

@ -1771,13 +1771,11 @@ table that summarizes what features are supported by each target.
Target Feature Matrix
---------------------
Note that this table does not include the C backend or Cpp backends, since they
do not use the target independent code generator infrastructure. It also
doesn't list features that are not supported fully by any target yet. It
considers a feature to be supported if at least one subtarget supports it. A
feature being supported means that it is useful and works for most cases, it
does not indicate that there are zero known bugs in the implementation. Here is
the key:
Note that this table does not list features that are not supported fully by any
target yet. It considers a feature to be supported if at least one subtarget
supports it. A feature being supported means that it is useful and works for
most cases, it does not indicate that there are zero known bugs in the
implementation. Here is the key:
:raw-html:`<table border="1" cellspacing="0">`
:raw-html:`<tr>`

6
llvm/docs/GettingStarted.rst
View File

@ -730,9 +730,9 @@ used by people developing LLVM.
| | the configure script. The default list is defined |
| | as ``LLVM_ALL_TARGETS``, and can be set to include |
| | out-of-tree targets. The default value includes: |
| | ``AArch64, AMDGPU, ARM, BPF, CppBackend, Hexagon, |
| | Mips, MSP430, NVPTX, PowerPC, Sparc, SystemZ |
| | X86, XCore``. |
| | ``AArch64, AMDGPU, ARM, BPF, Hexagon, Mips, |
| | MSP430, NVPTX, PowerPC, Sparc, SystemZ, X86, |
| | XCore``. |
+-------------------------+----------------------------------------------------+
| LLVM_ENABLE_DOXYGEN | Build doxygen-based documentation from the source |
| | code This is disabled by default because it is |

5
llvm/lib/Target/CppBackend/CMakeLists.txt
View File

@ -1,5 +0,0 @@
add_llvm_target(CppBackendCodeGen
CPPBackend.cpp
)
add_subdirectory(TargetInfo)

2145
llvm/lib/Target/CppBackend/CPPBackend.cpp
View File

File diff suppressed because it is too large Load Diff

44
llvm/lib/Target/CppBackend/CPPTargetMachine.h
View File

@ -1,44 +0,0 @@
//===-- CPPTargetMachine.h - TargetMachine for the C++ backend --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the TargetMachine that is used by the C++ backend.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_CPPBACKEND_CPPTARGETMACHINE_H
#define LLVM_LIB_TARGET_CPPBACKEND_CPPTARGETMACHINE_H
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
namespace llvm {
class formatted_raw_ostream;
struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
: TargetMachine(T, "", TT, CPU, FS, Options) {}
public:
bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
CodeGenFileType FileType, bool DisableVerify,
AnalysisID StartBefore, AnalysisID StartAfter,
AnalysisID StopAfter,
MachineFunctionInitializer *MFInitializer) override;
};
extern Target TheCppBackendTarget;
} // End llvm namespace
#endif

31
llvm/lib/Target/CppBackend/LLVMBuild.txt
View File

@ -1,31 +0,0 @@
;===- ./lib/Target/CppBackend/LLVMBuild.txt --------------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[common]
subdirectories = TargetInfo
[component_0]
type = TargetGroup
name = CppBackend
parent = Target
[component_1]
type = Library
name = CppBackendCodeGen
parent = CppBackend
required_libraries = Core CppBackendInfo Support Target
add_to_library_groups = CppBackend

3
llvm/lib/Target/CppBackend/TargetInfo/CMakeLists.txt
View File

@ -1,3 +0,0 @@
add_llvm_library(LLVMCppBackendInfo
CppBackendTargetInfo.cpp
)

29
llvm/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp
View File

@ -1,29 +0,0 @@
//===-- CppBackendTargetInfo.cpp - CppBackend Target Implementation -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "CPPTargetMachine.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
Target llvm::TheCppBackendTarget;
static bool CppBackend_TripleMatchQuality(Triple::ArchType Arch) {
// This backend doesn't correspond to any architecture. It must be explicitly
// selected with -march.
return false;
}
extern "C" void LLVMInitializeCppBackendTargetInfo() {
TargetRegistry::RegisterTarget(TheCppBackendTarget, "cpp",
"C++ backend",
&CppBackend_TripleMatchQuality);
}
extern "C" void LLVMInitializeCppBackendTargetMC() {}

23
llvm/lib/Target/CppBackend/TargetInfo/LLVMBuild.txt
View File

@ -1,23 +0,0 @@
;===- ./lib/Target/CppBackend/TargetInfo/LLVMBuild.txt ---------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = CppBackendInfo
parent = CppBackend
required_libraries = Support
add_to_library_groups = CppBackend

1
llvm/lib/Target/LLVMBuild.txt
View File

@ -24,7 +24,6 @@ subdirectories =
AArch64
AVR
BPF
CppBackend
Lanai
Hexagon
MSP430

7
llvm/test/CodeGen/CPP/2007-06-16-Funcname.ll
View File

@ -1,7 +0,0 @@
; RUN: llc < %s -march=cpp -cppfname=WAKKA | not grep makeLLVMModule
; PR1515
define void @foo() {
ret void
}

13
llvm/test/CodeGen/CPP/2009-05-01-Long-Double.ll
View File

@ -1,13 +0,0 @@
; RUN: llc < %s -march=cpp -cppgen=program -o %t
define x86_fp80 @some_func() nounwind {
entry:
%retval = alloca x86_fp80 ; <x86_fp80*> [#uses=2]
%call = call i32 (...) @other_func() ; <i32> [#uses=1]
%conv = sitofp i32 %call to x86_fp80 ; <x86_fp80> [#uses=1]
store x86_fp80 %conv, x86_fp80* %retval
%0 = load x86_fp80, x86_fp80* %retval ; <x86_fp80> [#uses=1]
ret x86_fp80 %0
}
declare i32 @other_func(...)

28
llvm/test/CodeGen/CPP/2009-05-04-CondBr.ll
View File

@ -1,28 +0,0 @@
; RUN: llc < %s -march=cpp -cppgen=program -o %t
; RUN: grep "BranchInst::Create(label_if_then, label_if_end, int1_cmp, label_entry);" %t
define i32 @some_func(i32 %a) nounwind {
entry:
%retval = alloca i32 ; <i32*> [#uses=2]
%a.addr = alloca i32 ; <i32*> [#uses=8]
store i32 %a, i32* %a.addr
%tmp = load i32, i32* %a.addr ; <i32> [#uses=1]
%inc = add i32 %tmp, 1 ; <i32> [#uses=1]
store i32 %inc, i32* %a.addr
%tmp1 = load i32, i32* %a.addr ; <i32> [#uses=1]
%cmp = icmp slt i32 %tmp1, 3 ; <i1> [#uses=1]
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
store i32 7, i32* %a.addr
br label %if.end
if.end: ; preds = %if.then, %entry
%tmp2 = load i32, i32* %a.addr ; <i32> [#uses=1]
%inc3 = add i32 %tmp2, 1 ; <i32> [#uses=1]
store i32 %inc3, i32* %a.addr
%tmp4 = load i32, i32* %a.addr ; <i32> [#uses=1]
store i32 %tmp4, i32* %retval
%0 = load i32, i32* %retval ; <i32> [#uses=1]
ret i32 %0
}

6
llvm/test/CodeGen/CPP/2012-02-05-UnitVarCrash.ll
View File

@ -1,6 +0,0 @@
; RUN: llc < %s -march=cpp
declare void @foo(<4 x i32>)
define void @bar() {
call void @foo(<4 x i32> <i32 0, i32 1, i32 2, i32 3>)
ret void
}

89
llvm/test/CodeGen/CPP/atomic.ll
View File

@ -1,89 +0,0 @@
; RUN: llc -march=cpp -o - %s | FileCheck %s
define void @test_atomicrmw(i32* %addr, i32 %inc) {
%inst0 = atomicrmw xchg i32* %addr, i32 %inc seq_cst
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, SequentiallyConsistent, CrossThread
; CHECK: [[INST]]->setName("inst0");
; CHECK: [[INST]]->setVolatile(false);
%inst1 = atomicrmw add i32* %addr, i32 %inc seq_cst
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, SequentiallyConsistent, CrossThread
; CHECK: [[INST]]->setName("inst1");
; CHECK: [[INST]]->setVolatile(false);
%inst2 = atomicrmw volatile sub i32* %addr, i32 %inc singlethread monotonic
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.*}}, Monotonic, SingleThread
; CHECK: [[INST]]->setName("inst2");
; CHECK: [[INST]]->setVolatile(true);
%inst3 = atomicrmw and i32* %addr, i32 %inc acq_rel
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.*}}, AcquireRelease, CrossThread
; CHECK: [[INST]]->setName("inst3");
; CHECK: [[INST]]->setVolatile(false);
%inst4 = atomicrmw nand i32* %addr, i32 %inc release
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Nand, {{.*}}, Release, CrossThread
; CHECK: [[INST]]->setName("inst4");
; CHECK: [[INST]]->setVolatile(false);
%inst5 = atomicrmw volatile or i32* %addr, i32 %inc singlethread seq_cst
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.*}}, SequentiallyConsistent, SingleThread
; CHECK: [[INST]]->setName("inst5");
; CHECK: [[INST]]->setVolatile(true);
%inst6 = atomicrmw xor i32* %addr, i32 %inc release
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xor, {{.*}}, Release, CrossThread
; CHECK: [[INST]]->setName("inst6");
; CHECK: [[INST]]->setVolatile(false);
%inst7 = atomicrmw volatile max i32* %addr, i32 %inc singlethread monotonic
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Max, {{.*}}, Monotonic, SingleThread
; CHECK: [[INST]]->setName("inst7");
; CHECK: [[INST]]->setVolatile(true);
%inst8 = atomicrmw min i32* %addr, i32 %inc acquire
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Min, {{.*}}, Acquire, CrossThread
; CHECK: [[INST]]->setName("inst8");
; CHECK: [[INST]]->setVolatile(false);
%inst9 = atomicrmw volatile umax i32* %addr, i32 %inc monotonic
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMax, {{.*}}, Monotonic, CrossThread
; CHECK: [[INST]]->setName("inst9");
; CHECK: [[INST]]->setVolatile(true);
%inst10 = atomicrmw umin i32* %addr, i32 %inc singlethread release
; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMin, {{.*}}, Release, SingleThread
; CHECK: [[INST]]->setName("inst10");
; CHECK: [[INST]]->setVolatile(false);
ret void
}
define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
%inst0 = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread
; CHECK: [[INST]]->setName("inst0");
; CHECK: [[INST]]->setVolatile(false);
; CHECK: [[INST]]->setWeak(false);
%inst1 = cmpxchg volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire
; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread
; CHECK: [[INST]]->setName("inst1");
; CHECK: [[INST]]->setVolatile(true);
; CHECK: [[INST]]->setWeak(false);
%inst2 = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread
; CHECK: [[INST]]->setName("inst2");
; CHECK: [[INST]]->setVolatile(false);
; CHECK: [[INST]]->setWeak(true);
%inst3 = cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire
; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread
; CHECK: [[INST]]->setName("inst3");
; CHECK: [[INST]]->setVolatile(true);
; CHECK: [[INST]]->setWeak(true);
ret void
}

7
llvm/test/CodeGen/CPP/attributes.ll
View File

@ -1,7 +0,0 @@
; RUN: llc < %s -march=cpp | FileCheck %s
define void @f1(i8* byval, i8* inalloca) {
; CHECK: ByVal
; CHECK: InAlloca
ret void
}

10
llvm/test/CodeGen/CPP/gep.ll
View File

@ -1,10 +0,0 @@
; RUN: llc -march=cpp -o - %s | FileCheck %s
define void @f1(i32* %addr) {
%x = getelementptr i32, i32* %addr, i32 1
; CHECK: ConstantInt* [[INT_1:.*]] = ConstantInt::get(mod->getContext(), APInt(32, StringRef("1"), 10));
; CHECK: GetElementPtrInst::Create(IntegerType::get(mod->getContext(), 32), ptr_addr,
; CHECK-NEXT: [[INT_1]]
; CHECK-NEXT: }, "x", label_3);
ret void
}

3
llvm/test/CodeGen/CPP/lit.local.cfg
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@ -1,3 +0,0 @@
if not 'CppBackend' in config.root.targets:
config.unsupported = True

2
llvm/utils/GenLibDeps.pl
View File

@ -96,7 +96,6 @@ if ($PEROBJ) {
$libpath =~ s/^AsmPrinter/CodeGen\/AsmPrinter/;
$libpath =~ s/^BitReader/Bitcode\/Reader/;
$libpath =~ s/^BitWriter/Bitcode\/Writer/;
$libpath =~ s/^CppBackend/Target\/CppBackend/;
$libpath =~ s/^MSIL/Target\/MSIL/;
$libpath =~ s/^Core/IR/;
$libpath =~ s/^Instrumentation/Transforms\/Instrumentation/;
@ -137,7 +136,6 @@ if ($PEROBJ) {
$libpath =~ s/^AsmPrinter/CodeGen\/AsmPrinter/;
$libpath =~ s/^BitReader/Bitcode\/Reader/;
$libpath =~ s/^BitWriter/Bitcode\/Writer/;
$libpath =~ s/^CppBackend/Target\/CppBackend/;
$libpath =~ s/^MSIL/Target\/MSIL/;
$libpath =~ s/^Core/VMCore/;
$libpath =~ s/^Instrumentation/Transforms\/Instrumentation/;