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[RISCV] Add support for selecting vrgather.vx/vi for fixed vector splat shuffles.
The test cases extract a fixed element from a vector and splat it into a vector. This gets DAG combined into a splat shuffle. I've used some very wide vectors in the test to make sure we have at least a couple tests where the element doesn't fit into the uimm5 immediate of vrgather.vi so we fall back to vrgather.vx. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D96186
This commit is contained in:
Craig Topper
parent
2193e8be3e
commit
0c254b4a69
@ -524,6 +524,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::LOAD, VT, Custom);
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setOperationAction(ISD::STORE, VT, Custom);
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@ -554,6 +555,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::LOAD, VT, Custom);
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setOperationAction(ISD::STORE, VT, Custom);
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@ -853,6 +855,36 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
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const RISCVSubtarget &Subtarget) {
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SDValue V1 = Op.getOperand(0);
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SDLoc DL(Op);
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MVT VT = Op.getSimpleValueType();
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ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
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if (SVN->isSplat()) {
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int Lane = SVN->getSplatIndex();
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if (Lane >= 0) {
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MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
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V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
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assert(Lane < (int)VT.getVectorNumElements() && "Unexpected lane!");
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MVT XLenVT = Subtarget.getXLenVT();
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SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT);
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MVT MaskVT =
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MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount());
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SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
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SDValue Gather =
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DAG.getNode(RISCVISD::VRGATHER_VX_VL, DL, ContainerVT, V1,
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DAG.getConstant(Lane, DL, XLenVT), Mask, VL);
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return convertFromScalableVector(VT, Gather, DAG, Subtarget);
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}
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}
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return SDValue();
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}
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SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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@ -1102,6 +1134,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerFPVECREDUCE(Op, DAG);
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case ISD::BUILD_VECTOR:
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return lowerBUILD_VECTOR(Op, DAG, Subtarget);
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case ISD::VECTOR_SHUFFLE:
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return lowerVECTOR_SHUFFLE(Op, DAG, Subtarget);
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case ISD::LOAD:
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return lowerFixedLengthVectorLoadToRVV(Op, DAG);
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case ISD::STORE:
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@ -4638,6 +4672,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(FMA_VL)
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NODE_NAME_CASE(VMCLR_VL)
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NODE_NAME_CASE(VMSET_VL)
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NODE_NAME_CASE(VRGATHER_VX_VL)
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NODE_NAME_CASE(VLE_VL)
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NODE_NAME_CASE(VSE_VL)
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}
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@ -167,6 +167,9 @@ enum NodeType : unsigned {
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VMCLR_VL,
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VMSET_VL,
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// Matches the semantics of vrgather.vx with an extra operand for VL.
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VRGATHER_VX_VL,
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// Memory opcodes start here.
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VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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VSE_VL,
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@ -79,6 +79,14 @@ def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
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SDTCisVT<5, XLenVT>]>;
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def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL>;
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def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL",
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SDTypeProfile<1, 4, [SDTCisVec<0>,
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SDTCisSameAs<0, 1>,
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SDTCisVT<2, XLenVT>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisVT<4, XLenVT>]>>;
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def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCisVec<0>,
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SDTCVecEltisVT<0, i1>,
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SDTCisVT<1, XLenVT>]>;
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@ -211,6 +219,41 @@ foreach vti = AllFloatVectors in {
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} // Predicates = [HasStdExtV, HasStdExtF]
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// 17.4. Vector Register GAther Instruction
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let Predicates = [HasStdExtV] in {
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foreach vti = AllIntegerVectors in {
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX)
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vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX)
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vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.SEW)>;
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}
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} // Predicates = [HasStdExtV]
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let Predicates = [HasStdExtV, HasStdExtF] in {
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foreach vti = AllFloatVectors in {
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX)
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vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX)
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vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.SEW)>;
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}
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} // Predicates = [HasStdExtV, HasStdExtF]
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//===----------------------------------------------------------------------===//
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// Miscellaneous RISCVISD SDNodes
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//===----------------------------------------------------------------------===//
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177
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
Normal file
177
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
Normal file
@ -0,0 +1,177 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
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define void @gather_const_v8f16(<8 x half>* %x) {
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; CHECK-LABEL: gather_const_v8f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, zero, 8
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; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
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; CHECK-NEXT: vle16.v v25, (a0)
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; CHECK-NEXT: vrgather.vi v26, v25, 5
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; CHECK-NEXT: vse16.v v26, (a0)
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; CHECK-NEXT: ret
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%a = load <8 x half>, <8 x half>* %x
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%b = extractelement <8 x half> %a, i32 5
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%c = insertelement <8 x half> undef, half %b, i32 0
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%d = shufflevector <8 x half> %c, <8 x half> undef, <8 x i32> zeroinitializer
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store <8 x half> %d, <8 x half>* %x
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ret void
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}
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define void @gather_const_v4f32(<4 x float>* %x) {
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; CHECK-LABEL: gather_const_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, zero, 4
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; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
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; CHECK-NEXT: vle32.v v25, (a0)
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; CHECK-NEXT: vrgather.vi v26, v25, 2
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; CHECK-NEXT: vse32.v v26, (a0)
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; CHECK-NEXT: ret
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%a = load <4 x float>, <4 x float>* %x
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%b = extractelement <4 x float> %a, i32 2
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%c = insertelement <4 x float> undef, float %b, i32 0
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%d = shufflevector <4 x float> %c, <4 x float> undef, <4 x i32> zeroinitializer
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store <4 x float> %d, <4 x float>* %x
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ret void
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}
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define void @gather_const_v2f64(<2 x double>* %x) {
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; CHECK-LABEL: gather_const_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, zero, 2
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; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
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; CHECK-NEXT: vle64.v v25, (a0)
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; CHECK-NEXT: vrgather.vi v26, v25, 0
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; CHECK-NEXT: vse64.v v26, (a0)
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; CHECK-NEXT: ret
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%a = load <2 x double>, <2 x double>* %x
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%b = extractelement <2 x double> %a, i32 0
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%c = insertelement <2 x double> undef, double %b, i32 0
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%d = shufflevector <2 x double> %c, <2 x double> undef, <2 x i32> zeroinitializer
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store <2 x double> %d, <2 x double>* %x
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ret void
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}
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define void @gather_const_v64f16(<64 x half>* %x) {
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; LMULMAX8-LABEL: gather_const_v64f16:
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; LMULMAX8: # %bb.0:
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; LMULMAX8-NEXT: addi a1, zero, 64
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; LMULMAX8-NEXT: vsetvli a1, a1, e16,m8,ta,mu
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; LMULMAX8-NEXT: vle16.v v8, (a0)
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; LMULMAX8-NEXT: addi a1, zero, 47
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; LMULMAX8-NEXT: vrgather.vx v16, v8, a1
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; LMULMAX8-NEXT: vse16.v v16, (a0)
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; LMULMAX8-NEXT: ret
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;
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; LMULMAX1-LABEL: gather_const_v64f16:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: addi a1, a0, 80
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; LMULMAX1-NEXT: addi a2, zero, 8
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; LMULMAX1-NEXT: vsetvli a2, a2, e16,m1,ta,mu
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; LMULMAX1-NEXT: vle16.v v25, (a1)
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; LMULMAX1-NEXT: addi a6, a0, 16
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; LMULMAX1-NEXT: addi a7, a0, 48
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; LMULMAX1-NEXT: addi a4, a0, 32
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; LMULMAX1-NEXT: addi a5, a0, 64
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; LMULMAX1-NEXT: addi a2, a0, 112
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; LMULMAX1-NEXT: addi a3, a0, 96
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; LMULMAX1-NEXT: vrgather.vi v26, v25, 7
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; LMULMAX1-NEXT: vse16.v v26, (a3)
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; LMULMAX1-NEXT: vse16.v v26, (a2)
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; LMULMAX1-NEXT: vse16.v v26, (a5)
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; LMULMAX1-NEXT: vse16.v v26, (a1)
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; LMULMAX1-NEXT: vse16.v v26, (a4)
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; LMULMAX1-NEXT: vse16.v v26, (a7)
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; LMULMAX1-NEXT: vse16.v v26, (a0)
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; LMULMAX1-NEXT: vse16.v v26, (a6)
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; LMULMAX1-NEXT: ret
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%a = load <64 x half>, <64 x half>* %x
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%b = extractelement <64 x half> %a, i32 47
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%c = insertelement <64 x half> undef, half %b, i32 0
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%d = shufflevector <64 x half> %c, <64 x half> undef, <64 x i32> zeroinitializer
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store <64 x half> %d, <64 x half>* %x
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ret void
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}
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define void @gather_const_v32f32(<32 x float>* %x) {
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; LMULMAX8-LABEL: gather_const_v32f32:
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; LMULMAX8: # %bb.0:
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; LMULMAX8-NEXT: addi a1, zero, 32
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; LMULMAX8-NEXT: vsetvli a1, a1, e32,m8,ta,mu
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; LMULMAX8-NEXT: vle32.v v8, (a0)
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; LMULMAX8-NEXT: vrgather.vi v16, v8, 17
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; LMULMAX8-NEXT: vse32.v v16, (a0)
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; LMULMAX8-NEXT: ret
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;
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; LMULMAX1-LABEL: gather_const_v32f32:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: addi a1, a0, 64
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; LMULMAX1-NEXT: addi a2, zero, 4
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; LMULMAX1-NEXT: vsetvli a2, a2, e32,m1,ta,mu
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; LMULMAX1-NEXT: vle32.v v25, (a1)
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; LMULMAX1-NEXT: addi a6, a0, 16
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; LMULMAX1-NEXT: addi a7, a0, 48
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; LMULMAX1-NEXT: addi a4, a0, 32
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; LMULMAX1-NEXT: addi a5, a0, 80
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; LMULMAX1-NEXT: addi a2, a0, 112
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; LMULMAX1-NEXT: addi a3, a0, 96
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; LMULMAX1-NEXT: vrgather.vi v26, v25, 1
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; LMULMAX1-NEXT: vse32.v v26, (a3)
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; LMULMAX1-NEXT: vse32.v v26, (a2)
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; LMULMAX1-NEXT: vse32.v v26, (a1)
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; LMULMAX1-NEXT: vse32.v v26, (a5)
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; LMULMAX1-NEXT: vse32.v v26, (a4)
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; LMULMAX1-NEXT: vse32.v v26, (a7)
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; LMULMAX1-NEXT: vse32.v v26, (a0)
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; LMULMAX1-NEXT: vse32.v v26, (a6)
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; LMULMAX1-NEXT: ret
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%a = load <32 x float>, <32 x float>* %x
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%b = extractelement <32 x float> %a, i32 17
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%c = insertelement <32 x float> undef, float %b, i32 0
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%d = shufflevector <32 x float> %c, <32 x float> undef, <32 x i32> zeroinitializer
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store <32 x float> %d, <32 x float>* %x
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ret void
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}
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define void @gather_const_v16f64(<16 x double>* %x) {
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; LMULMAX8-LABEL: gather_const_v16f64:
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; LMULMAX8: # %bb.0:
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; LMULMAX8-NEXT: addi a1, zero, 16
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; LMULMAX8-NEXT: vsetvli a1, a1, e64,m8,ta,mu
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; LMULMAX8-NEXT: vle64.v v8, (a0)
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; LMULMAX8-NEXT: vrgather.vi v16, v8, 10
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; LMULMAX8-NEXT: vse64.v v16, (a0)
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; LMULMAX8-NEXT: ret
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;
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; LMULMAX1-LABEL: gather_const_v16f64:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: addi a1, a0, 80
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; LMULMAX1-NEXT: addi a2, zero, 2
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; LMULMAX1-NEXT: vsetvli a2, a2, e64,m1,ta,mu
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; LMULMAX1-NEXT: vle64.v v25, (a1)
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; LMULMAX1-NEXT: addi a6, a0, 16
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; LMULMAX1-NEXT: addi a7, a0, 48
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; LMULMAX1-NEXT: addi a4, a0, 32
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; LMULMAX1-NEXT: addi a5, a0, 64
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; LMULMAX1-NEXT: addi a2, a0, 112
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; LMULMAX1-NEXT: addi a3, a0, 96
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; LMULMAX1-NEXT: vrgather.vi v26, v25, 0
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; LMULMAX1-NEXT: vse64.v v26, (a3)
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; LMULMAX1-NEXT: vse64.v v26, (a2)
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; LMULMAX1-NEXT: vse64.v v26, (a5)
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; LMULMAX1-NEXT: vse64.v v26, (a1)
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; LMULMAX1-NEXT: vse64.v v26, (a4)
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; LMULMAX1-NEXT: vse64.v v26, (a7)
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; LMULMAX1-NEXT: vse64.v v26, (a0)
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; LMULMAX1-NEXT: vse64.v v26, (a6)
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; LMULMAX1-NEXT: ret
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%a = load <16 x double>, <16 x double>* %x
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%b = extractelement <16 x double> %a, i32 10
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%c = insertelement <16 x double> undef, double %b, i32 0
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%d = shufflevector <16 x double> %c, <16 x double> undef, <16 x i32> zeroinitializer
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store <16 x double> %d, <16 x double>* %x
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ret void
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}
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202
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
Normal file
202
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
Normal file
@ -0,0 +1,202 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
|
||||
|
||||
define void @gather_const_v16i8(<16 x i8>* %x) {
|
||||
; CHECK-LABEL: gather_const_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a1, zero, 16
|
||||
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
|
||||
; CHECK-NEXT: vle8.v v25, (a0)
|
||||
; CHECK-NEXT: vrgather.vi v26, v25, 12
|
||||
; CHECK-NEXT: vse8.v v26, (a0)
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <16 x i8>, <16 x i8>* %x
|
||||
%b = extractelement <16 x i8> %a, i32 12
|
||||
%c = insertelement <16 x i8> undef, i8 %b, i32 0
|
||||
%d = shufflevector <16 x i8> %c, <16 x i8> undef, <16 x i32> zeroinitializer
|
||||
store <16 x i8> %d, <16 x i8>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @gather_const_v8i16(<8 x i16>* %x) {
|
||||
; CHECK-LABEL: gather_const_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a1, zero, 8
|
||||
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vle16.v v25, (a0)
|
||||
; CHECK-NEXT: vrgather.vi v26, v25, 5
|
||||
; CHECK-NEXT: vse16.v v26, (a0)
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <8 x i16>, <8 x i16>* %x
|
||||
%b = extractelement <8 x i16> %a, i32 5
|
||||
%c = insertelement <8 x i16> undef, i16 %b, i32 0
|
||||
%d = shufflevector <8 x i16> %c, <8 x i16> undef, <8 x i32> zeroinitializer
|
||||
store <8 x i16> %d, <8 x i16>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @gather_const_v4i32(<4 x i32>* %x) {
|
||||
; CHECK-LABEL: gather_const_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a1, zero, 4
|
||||
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vle32.v v25, (a0)
|
||||
; CHECK-NEXT: vrgather.vi v26, v25, 3
|
||||
; CHECK-NEXT: vse32.v v26, (a0)
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <4 x i32>, <4 x i32>* %x
|
||||
%b = extractelement <4 x i32> %a, i32 3
|
||||
%c = insertelement <4 x i32> undef, i32 %b, i32 0
|
||||
%d = shufflevector <4 x i32> %c, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
store <4 x i32> %d, <4 x i32>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @gather_const_v2i64(<2 x i64>* %x) {
|
||||
; CHECK-LABEL: gather_const_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a1, zero, 2
|
||||
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vle64.v v25, (a0)
|
||||
; CHECK-NEXT: vrgather.vi v26, v25, 1
|
||||
; CHECK-NEXT: vse64.v v26, (a0)
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <2 x i64>, <2 x i64>* %x
|
||||
%b = extractelement <2 x i64> %a, i32 1
|
||||
%c = insertelement <2 x i64> undef, i64 %b, i32 0
|
||||
%d = shufflevector <2 x i64> %c, <2 x i64> undef, <2 x i32> zeroinitializer
|
||||
store <2 x i64> %d, <2 x i64>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @gather_const_v64i8(<64 x i8>* %x) {
|
||||
; LMULMAX4-LABEL: gather_const_v64i8:
|
||||
; LMULMAX4: # %bb.0:
|
||||
; LMULMAX4-NEXT: addi a1, zero, 64
|
||||
; LMULMAX4-NEXT: vsetvli a1, a1, e8,m4,ta,mu
|
||||
; LMULMAX4-NEXT: vle8.v v28, (a0)
|
||||
; LMULMAX4-NEXT: addi a1, zero, 32
|
||||
; LMULMAX4-NEXT: vrgather.vx v8, v28, a1
|
||||
; LMULMAX4-NEXT: vse8.v v8, (a0)
|
||||
; LMULMAX4-NEXT: ret
|
||||
;
|
||||
; LMULMAX1-LABEL: gather_const_v64i8:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: addi a1, a0, 32
|
||||
; LMULMAX1-NEXT: addi a2, zero, 16
|
||||
; LMULMAX1-NEXT: vsetvli a2, a2, e8,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vle8.v v25, (a1)
|
||||
; LMULMAX1-NEXT: addi a2, a0, 16
|
||||
; LMULMAX1-NEXT: addi a3, a0, 48
|
||||
; LMULMAX1-NEXT: vrgather.vi v26, v25, 0
|
||||
; LMULMAX1-NEXT: vse8.v v26, (a1)
|
||||
; LMULMAX1-NEXT: vse8.v v26, (a3)
|
||||
; LMULMAX1-NEXT: vse8.v v26, (a0)
|
||||
; LMULMAX1-NEXT: vse8.v v26, (a2)
|
||||
; LMULMAX1-NEXT: ret
|
||||
%a = load <64 x i8>, <64 x i8>* %x
|
||||
%b = extractelement <64 x i8> %a, i32 32
|
||||
%c = insertelement <64 x i8> undef, i8 %b, i32 0
|
||||
%d = shufflevector <64 x i8> %c, <64 x i8> undef, <64 x i32> zeroinitializer
|
||||
store <64 x i8> %d, <64 x i8>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @gather_const_v16i16(<32 x i16>* %x) {
|
||||
; LMULMAX4-LABEL: gather_const_v16i16:
|
||||
; LMULMAX4: # %bb.0:
|
||||
; LMULMAX4-NEXT: addi a1, zero, 32
|
||||
; LMULMAX4-NEXT: vsetvli a1, a1, e16,m4,ta,mu
|
||||
; LMULMAX4-NEXT: vle16.v v28, (a0)
|
||||
; LMULMAX4-NEXT: vrgather.vi v8, v28, 25
|
||||
; LMULMAX4-NEXT: vse16.v v8, (a0)
|
||||
; LMULMAX4-NEXT: ret
|
||||
;
|
||||
; LMULMAX1-LABEL: gather_const_v16i16:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: addi a1, a0, 48
|
||||
; LMULMAX1-NEXT: addi a2, zero, 8
|
||||
; LMULMAX1-NEXT: vsetvli a2, a2, e16,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vle16.v v25, (a1)
|
||||
; LMULMAX1-NEXT: addi a2, a0, 16
|
||||
; LMULMAX1-NEXT: addi a3, a0, 32
|
||||
; LMULMAX1-NEXT: vrgather.vi v26, v25, 1
|
||||
; LMULMAX1-NEXT: vse16.v v26, (a3)
|
||||
; LMULMAX1-NEXT: vse16.v v26, (a1)
|
||||
; LMULMAX1-NEXT: vse16.v v26, (a0)
|
||||
; LMULMAX1-NEXT: vse16.v v26, (a2)
|
||||
; LMULMAX1-NEXT: ret
|
||||
%a = load <32 x i16>, <32 x i16>* %x
|
||||
%b = extractelement <32 x i16> %a, i32 25
|
||||
%c = insertelement <32 x i16> undef, i16 %b, i32 0
|
||||
%d = shufflevector <32 x i16> %c, <32 x i16> undef, <32 x i32> zeroinitializer
|
||||
store <32 x i16> %d, <32 x i16>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @gather_const_v16i32(<16 x i32>* %x) {
|
||||
; LMULMAX4-LABEL: gather_const_v16i32:
|
||||
; LMULMAX4: # %bb.0:
|
||||
; LMULMAX4-NEXT: addi a1, zero, 16
|
||||
; LMULMAX4-NEXT: vsetvli a1, a1, e32,m4,ta,mu
|
||||
; LMULMAX4-NEXT: vle32.v v28, (a0)
|
||||
; LMULMAX4-NEXT: vrgather.vi v8, v28, 9
|
||||
; LMULMAX4-NEXT: vse32.v v8, (a0)
|
||||
; LMULMAX4-NEXT: ret
|
||||
;
|
||||
; LMULMAX1-LABEL: gather_const_v16i32:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: addi a1, a0, 32
|
||||
; LMULMAX1-NEXT: addi a2, zero, 4
|
||||
; LMULMAX1-NEXT: vsetvli a2, a2, e32,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vle32.v v25, (a1)
|
||||
; LMULMAX1-NEXT: addi a2, a0, 16
|
||||
; LMULMAX1-NEXT: addi a3, a0, 48
|
||||
; LMULMAX1-NEXT: vrgather.vi v26, v25, 1
|
||||
; LMULMAX1-NEXT: vse32.v v26, (a1)
|
||||
; LMULMAX1-NEXT: vse32.v v26, (a3)
|
||||
; LMULMAX1-NEXT: vse32.v v26, (a0)
|
||||
; LMULMAX1-NEXT: vse32.v v26, (a2)
|
||||
; LMULMAX1-NEXT: ret
|
||||
%a = load <16 x i32>, <16 x i32>* %x
|
||||
%b = extractelement <16 x i32> %a, i32 9
|
||||
%c = insertelement <16 x i32> undef, i32 %b, i32 0
|
||||
%d = shufflevector <16 x i32> %c, <16 x i32> undef, <16 x i32> zeroinitializer
|
||||
store <16 x i32> %d, <16 x i32>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @gather_const_v8i64(<8 x i64>* %x) {
|
||||
; LMULMAX4-LABEL: gather_const_v8i64:
|
||||
; LMULMAX4: # %bb.0:
|
||||
; LMULMAX4-NEXT: addi a1, zero, 8
|
||||
; LMULMAX4-NEXT: vsetvli a1, a1, e64,m4,ta,mu
|
||||
; LMULMAX4-NEXT: vle64.v v28, (a0)
|
||||
; LMULMAX4-NEXT: vrgather.vi v8, v28, 3
|
||||
; LMULMAX4-NEXT: vse64.v v8, (a0)
|
||||
; LMULMAX4-NEXT: ret
|
||||
;
|
||||
; LMULMAX1-LABEL: gather_const_v8i64:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: addi a1, a0, 16
|
||||
; LMULMAX1-NEXT: addi a2, zero, 2
|
||||
; LMULMAX1-NEXT: vsetvli a2, a2, e64,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vle64.v v25, (a1)
|
||||
; LMULMAX1-NEXT: addi a2, a0, 48
|
||||
; LMULMAX1-NEXT: addi a3, a0, 32
|
||||
; LMULMAX1-NEXT: vrgather.vi v26, v25, 1
|
||||
; LMULMAX1-NEXT: vse64.v v26, (a3)
|
||||
; LMULMAX1-NEXT: vse64.v v26, (a2)
|
||||
; LMULMAX1-NEXT: vse64.v v26, (a0)
|
||||
; LMULMAX1-NEXT: vse64.v v26, (a1)
|
||||
; LMULMAX1-NEXT: ret
|
||||
%a = load <8 x i64>, <8 x i64>* %x
|
||||
%b = extractelement <8 x i64> %a, i32 3
|
||||
%c = insertelement <8 x i64> undef, i64 %b, i32 0
|
||||
%d = shufflevector <8 x i64> %c, <8 x i64> undef, <8 x i32> zeroinitializer
|
||||
store <8 x i64> %d, <8 x i64>* %x
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user