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AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users

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Use TII::getRegClass to return a valid regclass or a nullptr
if the RC is unknown for a given OpIdx. This fixes a potential
crash occurred while getting the RC from a variadic instruction.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D120813
This commit is contained in:
Christudasan Devadasan 2022-03-02 12:16:29 +05:30
parent 4de9a752d6
commit 0d849b8249
2 changed files with 54 additions and 2 deletions
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5
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
View File

@ -1602,8 +1602,9 @@ bool SIFoldOperands::tryFoldRegSequence(MachineInstr &MI) {
unsigned OpIdx = Op - &UseMI->getOperand(0);
const MCInstrDesc &InstDesc = UseMI->getDesc();
if (!TRI->isVectorSuperClass(
TRI->getRegClass(InstDesc.OpInfo[OpIdx].RegClass)))
const TargetRegisterClass *OpRC =
TII->getRegClass(InstDesc, OpIdx, TRI, *MI.getMF());
if (!OpRC || !TRI->isVectorSuperClass(OpRC))
return false;
const auto *NewDstRC = TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg));

51
llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir Normal file
View File

@ -0,0 +1,51 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
# Skip folding a REG_SEQUENCE to its user when the regclasses for the user operands can't be
# fully determined from the instruction description.
---
name: regsequence_with_regsequence_use_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $agpr0, $agpr1
; GCN-LABEL: name: regsequence_with_regsequence_use_op
; GCN: liveins: $agpr0, $agpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF]], %subreg.sub2
; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
%0:vgpr_32 = COPY $agpr0
%1:vgpr_32 = COPY $agpr1
%2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1
%3:vgpr_32 = IMPLICIT_DEF
%4:vreg_96_align2 = REG_SEQUENCE killed %2:vreg_64_align2, %subreg.sub0_sub1, killed %3:vgpr_32, %subreg.sub2
S_ENDPGM 0, implicit %4
...
---
name: insert_subreg_with_regsequence_use_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $agpr0, $agpr1
; GCN-LABEL: name: insert_subreg_with_regsequence_use_op
; GCN: liveins: $agpr0, $agpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: S_NOP 0, implicit-def %3
; GCN-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64_align2 = INSERT_SUBREG %3, [[REG_SEQUENCE]], %subreg.sub0_sub1
; GCN-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
%0:vgpr_32 = COPY $agpr0
%1:vgpr_32 = COPY $agpr1
%2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1
S_NOP 0, implicit-def %3:vreg_64_align2
%4:vreg_64_align2 = INSERT_SUBREG %3, %2, %subreg.sub0_sub1
S_ENDPGM 0, implicit %4
...