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[mips] Fix the predicates for arithmetic operations

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Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47635

llvm-svn: 334031
This commit is contained in:
Simon Dardis 2018-06-05 17:53:22 +00:00
parent a642f8f343
commit 0d95ff03f2
4 changed files with 90 additions and 51 deletions
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8
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -746,8 +746,9 @@ let DecoderNamespace = "MicroMips" in {
ADD_FM_MM<0, 0x150>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
ADD_FM_MM<0, 0x1d0>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL>,
ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6;
let Defs = [HI0, LO0] in
def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6;
def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
ADD_FM_MM<0, 0x110>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
@ -773,7 +774,8 @@ let DecoderNamespace = "MicroMips" in {
MULT_FM_MM<0x2ec>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Arithmetic Instructions with PC and Immediate
def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM,
ISA_MICROMIPS32_NOT_MIPS32R6;
/// Shift Instructions
def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,

98
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -1973,49 +1973,54 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
let AdditionalPredicates = [NotInMicroMips] in {
def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
II_ADDIU, immSExt16, add>,
ADDI_FM<0x9>, IsAsCheapAsAMove;
ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1;
def ANDi : MMRel, StdMMR6Rel,
ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
ADDI_FM<0xc>;
ADDI_FM<0xc>, ISA_MIPS1;
def ORi : MMRel, StdMMR6Rel,
ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
ADDI_FM<0xd>;
ADDI_FM<0xd>, ISA_MIPS1;
def XORi : MMRel, StdMMR6Rel,
ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
ADDI_FM<0xe>;
}
def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>,
ISA_MIPS1_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
ADDI_FM<0xe>, ISA_MIPS1;
def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>,
ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6;
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xa>;
SLTI_FM<0xa>, ISA_MIPS1;
def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xb>;
}
def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
let AdditionalPredicates = [NotInMicroMips] in {
SLTI_FM<0xb>, ISA_MIPS1;
def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM,
ISA_MIPS1;
/// Arithmetic Instructions (3-Operand, R-Type)
def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
ADD_FM<0, 0x21>;
ADD_FM<0, 0x21>, ISA_MIPS1;
def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
ADD_FM<0, 0x23>;
}
let Defs = [HI0, LO0] in
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>;
def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>;
let AdditionalPredicates = [NotInMicroMips] in {
def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
ADD_FM<0, 0x23>, ISA_MIPS1;
let Defs = [HI0, LO0] in
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
ADD_FM<0, 0x20>, ISA_MIPS1;
def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
ADD_FM<0, 0x22>, ISA_MIPS1;
def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>,
ISA_MIPS1;
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>,
ISA_MIPS1;
def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
ADD_FM<0, 0x24>;
ADD_FM<0, 0x24>, ISA_MIPS1;
def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
ADD_FM<0, 0x25>;
ADD_FM<0, 0x25>, ISA_MIPS1;
def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
ADD_FM<0, 0x26>;
def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
ADD_FM<0, 0x26>, ISA_MIPS1;
def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>,
ISA_MIPS1;
}
let AdditionalPredicates = [NotInMicroMips] in {
@ -2273,21 +2278,19 @@ let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1, isCTI = 1 in
}
/// Multiply and Divide Instructions.
def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
}
def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
ISA_MIPS1_NOT_32R6_64R6;
def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
ISA_MIPS1_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
ISA_MIPS1_NOT_32R6_64R6;
def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
ISA_MIPS1_NOT_32R6_64R6;
def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
ISA_MIPS1_NOT_32R6_64R6;
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
@ -2320,18 +2323,17 @@ let AdditionalPredicates = [NotInMicroMips] in {
let AdditionalPredicates = [NotInMicroMips] in
def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1;
// MADD*/MSUB*
def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
ISA_MIPS32_NOT_32R6_64R6;
def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
ISA_MIPS32_NOT_32R6_64R6;
def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
ISA_MIPS32_NOT_32R6_64R6;
def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
ISA_MIPS32_NOT_32R6_64R6;
}
// MADD*/MSUB*
def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
ISA_MIPS32_NOT_32R6_64R6;
def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
ISA_MIPS32_NOT_32R6_64R6;
def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
ISA_MIPS32_NOT_32R6_64R6;
def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
ISA_MIPS32_NOT_32R6_64R6;
let AdditionalPredicates = [NotDSP] in {
def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
ISA_MIPS1_NOT_32R6_64R6;

16
llvm/test/CodeGen/Mips/llvm-ir/isel.ll Normal file
View File

@ -0,0 +1,16 @@
; RUN: llc --mtriple=mips-mti-linux-gnu < %s -debug 2>&1 | FileCheck %s --check-prefixes=CHECK,MIPS
; RUN: llc --mtriple=mips-mti-linux-gnu < %s -mattr=+micromips -debug 2>&1 | FileCheck %s --check-prefixes=CHECK,MM
; REQUIRES: asserts
; Test that the correct mul instruction is selected upfront.
; CHECK-LABEL: Instruction selection ends:
; MIPS: t{{[0-9]+}}: i32,i32 = MUL t{{[0-9]+}}, t{{[0-9]+}}
; MM: t{{[0-9]+}}: i32,i32 = MUL_MM t{{[0-9]+}}, t{{[0-9]+}}
define i32 @mul(i32 %a, i32 %b) {
entry:
%0 = mul i32 %a, %b
ret i32 %0
}

19
llvm/test/MC/Mips/micromips/valid.s
View File

@ -104,14 +104,17 @@ sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32_MM
add $9, $6, $7 # CHECK: add $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x10]
# CHECK: # <MCInst #{{.*}} ADD_MM
add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x30]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D32_MM
addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67]
# CHECK: # <MCInst #{{.*}} ADDi_MM
addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67]
addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67]
addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67]
addu $9, $6, $7 # CHECK: addu $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x50]
sub $9, $6, $7 # CHECK: sub $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x90]
# CHECK: # <MCInst #{{.*}} SUB_MM
subu $4, $3, $5 # CHECK: subu $4, $3, $5 # encoding: [0x00,0xa3,0x21,0xd0]
sub $6, $zero, $7 # CHECK: neg $6, $7 # encoding: [0x00,0xe0,0x31,0x90]
sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x70]
@ -124,6 +127,7 @@ slti $3, $3, 103 # CHECK: slti $3, $3, 103 # encoding: [0x90,0x
sltiu $3, $3, 103 # CHECK: sltiu $3, $3, 103 # encoding: [0xb0,0x63,0x00,0x67]
sltu $3, $3, $5 # CHECK: sltu $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x90]
lui $9, 17767 # CHECK: lui $9, 17767 # encoding: [0x41,0xa9,0x45,0x67]
# CHECK: # <MCInst #{{.*}} LUi_MM
and $9, $6, $7 # CHECK: and $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x50]
andi $9, $6, 17767 # CHECK: andi $9, $6, 17767 # encoding: [0xd1,0x26,0x45,0x67]
or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
@ -134,10 +138,13 @@ nor $9, $6, $7 # CHECK: nor $9, $6, $7 # encoding: [0x00,0x
not $7, $8 # CHECK: not $7, $8 # encoding: [0x00,0x08,0x3a,0xd0]
not $7 # CHECK: not $7, $7 # encoding: [0x00,0x07,0x3a,0xd0]
mul $9, $6, $7 # CHECK: mul $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x10]
# CHECK: # <MCInst #{{.*}} MUL_MM
mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xb0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D32_MM
mult $9, $7 # CHECK: mult $9, $7 # encoding: [0x00,0xe9,0x8b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MULT_MM
multu $9, $7 # CHECK: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MULTu_MM
div $zero, $9, $7 # CHECK: div $zero, $9, $7 # encoding: [0x00,0xe9,0xab,0x3c]
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D32_MM
@ -179,18 +186,24 @@ movt $9, $6, $fcc0 # CHECK: movt $9, $6, $fcc0 # encoding: [0x55,0x
movf $9, $6, $fcc0 # CHECK: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
# FIXME: MTHI should also have its 16 bit implementation selected in micromips
mthi $6 # CHECK: mthi $6 # encoding: [0x00,0x06,0x2d,0x7c]
# CHECK: # <MCInst {{.*}} MTHI_MM
mfhi $6 # CHECK: mfhi $6 # encoding: [0x00,0x06,0x0d,0x7c]
# FIXME: MTLO should also have its 16 bit implementation selected in micromips
mtlo $6 # CHECK: mtlo $6 # encoding: [0x00,0x06,0x3d,0x7c]
# CHECK: # <MCInst {{.*}} MTLO_MM
mflo $6 # CHECK: mflo $6 # encoding: [0x00,0x06,0x1d,0x7c]
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM
mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM
madd $4, $5 # CHECK: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c]
# CHECK: # <MCInst {{.*}} MADD_MM
maddu $4, $5 # CHECK: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c]
# CHECK: # <MCInst {{.*}} MADDU_MM
msub $4, $5 # CHECK: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
# CHECK: # <MCInst {{.*}} MSUB_MM
msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c]
# CHECK: # <MCInst {{.*}} MSUBU_MM
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32_MM
clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c]
@ -255,8 +268,14 @@ swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x
lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
addiupc $2, 20 # CHECK: addiupc $2, 20 # encoding: [0x79,0x00,0x00,0x05]
# CHECK: # <MCInst #{{.*}} ADDIUPC_MM
# CHECK-NOT: # <MCInst #{{.*}} ADDIUPC_MMR6
addiupc $7, 16777212 # CHECK: addiupc $7, 16777212 # encoding: [0x7b,0xbf,0xff,0xff]
# CHECK: # <MCInst #{{.*}} ADDIUPC_MM
# CHECK-NOT: # <MCInst #{{.*}} ADDIUPC_MMR6
addiupc $7, -16777216 # CHECK: addiupc $7, -16777216 # encoding: [0x7b,0xc0,0x00,0x00]
# CHECK: # <MCInst #{{.*}} ADDIUPC_MM
# CHECK-NOT: # <MCInst #{{.*}} ADDIUPC_MMR6
ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c]
ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c]
cachee 1, 8($5) # CHECK: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]