From 0d95ff03f278e8639b34ed62b48df0ed164659e2 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Tue, 5 Jun 2018 17:53:22 +0000 Subject: [PATCH] [mips] Fix the predicates for arithmetic operations Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47635 llvm-svn: 334031 --- llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 8 +- llvm/lib/Target/Mips/MipsInstrInfo.td | 98 +++++++++++----------- llvm/test/CodeGen/Mips/llvm-ir/isel.ll | 16 ++++ llvm/test/MC/Mips/micromips/valid.s | 19 +++++ 4 files changed, 90 insertions(+), 51 deletions(-) create mode 100644 llvm/test/CodeGen/Mips/llvm-ir/isel.ll diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 3c70db6a0922..f4dbd175530e 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -746,8 +746,9 @@ let DecoderNamespace = "MicroMips" in { ADD_FM_MM<0, 0x150>, ISA_MICROMIPS32_NOT_MIPS32R6; def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, ADD_FM_MM<0, 0x1d0>, ISA_MICROMIPS32_NOT_MIPS32R6; - def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL>, - ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6; + let Defs = [HI0, LO0] in + def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, + ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6; def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM_MM<0, 0x110>, ISA_MICROMIPS32_NOT_MIPS32R6; def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, @@ -773,7 +774,8 @@ let DecoderNamespace = "MicroMips" in { MULT_FM_MM<0x2ec>, ISA_MICROMIPS32_NOT_MIPS32R6; /// Arithmetic Instructions with PC and Immediate - def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM; + def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM, + ISA_MICROMIPS32_NOT_MIPS32R6; /// Shift Instructions def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>, diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 08777e284c2a..3271cd130552 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1973,49 +1973,54 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), let AdditionalPredicates = [NotInMicroMips] in { def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd, II_ADDIU, immSExt16, add>, - ADDI_FM<0x9>, IsAsCheapAsAMove; + ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1; def ANDi : MMRel, StdMMR6Rel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, - ADDI_FM<0xc>; + ADDI_FM<0xc>, ISA_MIPS1; def ORi : MMRel, StdMMR6Rel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, - ADDI_FM<0xd>; + ADDI_FM<0xd>, ISA_MIPS1; def XORi : MMRel, StdMMR6Rel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, - ADDI_FM<0xe>; -} -def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>, - ISA_MIPS1_NOT_32R6_64R6; -let AdditionalPredicates = [NotInMicroMips] in { + ADDI_FM<0xe>, ISA_MIPS1; + def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, + ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xa>; + SLTI_FM<0xa>, ISA_MIPS1; def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xb>; -} -def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; -let AdditionalPredicates = [NotInMicroMips] in { + SLTI_FM<0xb>, ISA_MIPS1; + + def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM, + ISA_MIPS1; + /// Arithmetic Instructions (3-Operand, R-Type) def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, - ADD_FM<0, 0x21>; + ADD_FM<0, 0x21>, ISA_MIPS1; def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, - ADD_FM<0, 0x23>; -} -let Defs = [HI0, LO0] in -def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, - ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; -def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>; -def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>; -let AdditionalPredicates = [NotInMicroMips] in { - def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; - def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; + ADD_FM<0, 0x23>, ISA_MIPS1; + + let Defs = [HI0, LO0] in + def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, + ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; + + def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, + ADD_FM<0, 0x20>, ISA_MIPS1; + def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, + ADD_FM<0, 0x22>, ISA_MIPS1; + + def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>, + ISA_MIPS1; + def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>, + ISA_MIPS1; def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, - ADD_FM<0, 0x24>; + ADD_FM<0, 0x24>, ISA_MIPS1; def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, - ADD_FM<0, 0x25>; + ADD_FM<0, 0x25>, ISA_MIPS1; def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, - ADD_FM<0, 0x26>; - def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; + ADD_FM<0, 0x26>, ISA_MIPS1; + def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>, + ISA_MIPS1; } let AdditionalPredicates = [NotInMicroMips] in { @@ -2273,21 +2278,19 @@ let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1, isCTI = 1 in } /// Multiply and Divide Instructions. -def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, - MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6; -def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, - MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6; let AdditionalPredicates = [NotInMicroMips] in { + def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, + MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6; + def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, + MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6; def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6; def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6; -} -def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, - ISA_MIPS1_NOT_32R6_64R6; -def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, - ISA_MIPS1_NOT_32R6_64R6; -let AdditionalPredicates = [NotInMicroMips] in { + def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, + ISA_MIPS1_NOT_32R6_64R6; + def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, + ISA_MIPS1_NOT_32R6_64R6; def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, ISA_MIPS1_NOT_32R6_64R6; def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, @@ -2320,18 +2323,17 @@ let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1; + // MADD*/MSUB* + def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, + ISA_MIPS32_NOT_32R6_64R6; + def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, + ISA_MIPS32_NOT_32R6_64R6; + def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, + ISA_MIPS32_NOT_32R6_64R6; + def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, + ISA_MIPS32_NOT_32R6_64R6; } -// MADD*/MSUB* -def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, - ISA_MIPS32_NOT_32R6_64R6; -def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, - ISA_MIPS32_NOT_32R6_64R6; -def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, - ISA_MIPS32_NOT_32R6_64R6; -def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, - ISA_MIPS32_NOT_32R6_64R6; - let AdditionalPredicates = [NotDSP] in { def PseudoMULT : MultDivPseudo, ISA_MIPS1_NOT_32R6_64R6; diff --git a/llvm/test/CodeGen/Mips/llvm-ir/isel.ll b/llvm/test/CodeGen/Mips/llvm-ir/isel.ll new file mode 100644 index 000000000000..cdcd3fd6876d --- /dev/null +++ b/llvm/test/CodeGen/Mips/llvm-ir/isel.ll @@ -0,0 +1,16 @@ +; RUN: llc --mtriple=mips-mti-linux-gnu < %s -debug 2>&1 | FileCheck %s --check-prefixes=CHECK,MIPS +; RUN: llc --mtriple=mips-mti-linux-gnu < %s -mattr=+micromips -debug 2>&1 | FileCheck %s --check-prefixes=CHECK,MM + +; REQUIRES: asserts + +; Test that the correct mul instruction is selected upfront. + +; CHECK-LABEL: Instruction selection ends: +; MIPS: t{{[0-9]+}}: i32,i32 = MUL t{{[0-9]+}}, t{{[0-9]+}} +; MM: t{{[0-9]+}}: i32,i32 = MUL_MM t{{[0-9]+}}, t{{[0-9]+}} + +define i32 @mul(i32 %a, i32 %b) { +entry: + %0 = mul i32 %a, %b + ret i32 %0 +} diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index da33c6151e01..9e876802390f 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -104,14 +104,17 @@ sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0 sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b] # CHECK-NEXT: #