Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-11-24 14:20:17 +00:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Revert "[LoongArch] Fix codegen of atomicrmw nand"

Browse Source 
This reverts commit 9572406bbc.

The author name is wrong.
This commit is contained in:
Weining Lu 2022-10-18 20:59:59 +08:00
parent d239f3c627
commit 0f374ca5cd
2 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
View File

@ -162,9 +162,9 @@ static void doAtomicBinOpExpansion(const LoongArchInstrInfo *TII,
BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg)
.addReg(DestReg)
.addReg(IncrReg);
BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg)
BuildMI(LoopMBB, DL, TII->get(LoongArch::XORI), ScratchReg)
.addReg(ScratchReg)
.addReg(LoongArch::R0);
.addImm(-1);
break;
case AtomicRMWInst::Add:
BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg)
@ -268,9 +268,9 @@ static void doMaskedAtomicBinOpExpansion(
BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg)
.addReg(DestReg)
.addReg(IncrReg);
BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg)
BuildMI(LoopMBB, DL, TII->get(LoongArch::XORI), ScratchReg)
.addReg(ScratchReg)
.addReg(LoongArch::R0);
.addImm(-1);
// TODO: support other AtomicRMWInst.
}

14
llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
View File

@ -450,7 +450,7 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
; LA32-NEXT: dbar 0
; LA32-NEXT: ll.w $a4, $a2, 0
; LA32-NEXT: and $a5, $a4, $a1
; LA32-NEXT: nor $a5, $a5, $zero
; LA32-NEXT: xori $a5, $a5, -1
; LA32-NEXT: xor $a5, $a4, $a5
; LA32-NEXT: and $a5, $a5, $a3
; LA32-NEXT: xor $a5, $a4, $a5
@ -475,7 +475,7 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-NEXT: dbar 0
; LA64-NEXT: ll.w $a4, $a2, 0
; LA64-NEXT: and $a5, $a4, $a1
; LA64-NEXT: nor $a5, $a5, $zero
; LA64-NEXT: xori $a5, $a5, -1
; LA64-NEXT: xor $a5, $a4, $a5
; LA64-NEXT: and $a5, $a5, $a3
; LA64-NEXT: xor $a5, $a4, $a5
@ -503,7 +503,7 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
; LA32-NEXT: dbar 0
; LA32-NEXT: ll.w $a4, $a2, 0
; LA32-NEXT: and $a5, $a4, $a1
; LA32-NEXT: nor $a5, $a5, $zero
; LA32-NEXT: xori $a5, $a5, -1
; LA32-NEXT: xor $a5, $a4, $a5
; LA32-NEXT: and $a5, $a5, $a3
; LA32-NEXT: xor $a5, $a4, $a5
@ -529,7 +529,7 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-NEXT: dbar 0
; LA64-NEXT: ll.w $a4, $a2, 0
; LA64-NEXT: and $a5, $a4, $a1
; LA64-NEXT: nor $a5, $a5, $zero
; LA64-NEXT: xori $a5, $a5, -1
; LA64-NEXT: xor $a5, $a4, $a5
; LA64-NEXT: and $a5, $a5, $a3
; LA64-NEXT: xor $a5, $a4, $a5
@ -549,7 +549,7 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
; LA32-NEXT: dbar 0
; LA32-NEXT: ll.w $a2, $a1, 0
; LA32-NEXT: and $a3, $a2, $a0
; LA32-NEXT: nor $a3, $a3, $zero
; LA32-NEXT: xori $a3, $a3, -1
; LA32-NEXT: sc.w $a3, $a1, 0
; LA32-NEXT: beqz $a3, .LBB14_1
; LA32-NEXT: # %bb.2:
@ -562,7 +562,7 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
; LA64-NEXT: dbar 0
; LA64-NEXT: ll.w $a2, $a1, 0
; LA64-NEXT: and $a3, $a2, $a0
; LA64-NEXT: nor $a3, $a3, $zero
; LA64-NEXT: xori $a3, $a3, -1
; LA64-NEXT: sc.w $a3, $a1, 0
; LA64-NEXT: beqz $a3, .LBB14_1
; LA64-NEXT: # %bb.2:
@ -589,7 +589,7 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind {
; LA64-NEXT: dbar 0
; LA64-NEXT: ll.d $a2, $a1, 0
; LA64-NEXT: and $a3, $a2, $a0
; LA64-NEXT: nor $a3, $a3, $zero
; LA64-NEXT: xori $a3, $a3, -1
; LA64-NEXT: sc.d $a3, $a1, 0
; LA64-NEXT: beqz $a3, .LBB15_1
; LA64-NEXT: # %bb.2: