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[DAG] Set nneg flag when forming zext in demanded bits (#72281)

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We do the same for the analogous transform in DAGCombine, but this case
was missed in the recent patch which added support for zext nneg.

Sorry for the lack of test coverage. Not sure how to exercise this piece
of logic. It appears to have only minimal impact on LIT tests (only
test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll),
and even then, the changes without it appear uninteresting. Maybe we
should remove this transform instead?
This commit is contained in:
Philip Reames 2024-01-18 07:34:08 -08:00 committed by GitHub
parent 2747193058
commit 0fc5f4b524
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1 changed files with 6 additions and 2 deletions
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8
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -2483,8 +2483,12 @@ bool TargetLowering::SimplifyDemandedBits(
if (Known.isNonNegative()) {
unsigned Opc =
IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND;
if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) {
SDNodeFlags Flags;
if (!IsVecInReg)
Flags.setNonNeg(true);
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src, Flags));
}
}
// Attempt to avoid multi-use ops if we don't need anything from them.