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AMDGPU: Fix handling of -0 in round lowering (#65761)
This commit is contained in:
Matt Arsenault
GitHub
parent
b9a6b28a58
commit
1328a8534b
@ -6586,23 +6586,25 @@ LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
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// round(x) =>
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// t = trunc(x);
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// d = fabs(x - t);
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// o = copysign(1.0f, x);
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// return t + (d >= 0.5 ? o : 0.0);
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// o = copysign(d >= 0.5 ? 1.0 : 0.0, x);
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// return t + o;
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auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags);
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auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags);
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auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags);
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auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
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auto One = MIRBuilder.buildFConstant(Ty, 1.0);
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auto Half = MIRBuilder.buildFConstant(Ty, 0.5);
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auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X);
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auto Cmp =
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MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, Flags);
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auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half,
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Flags);
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auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags);
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// Could emit G_UITOFP instead
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auto One = MIRBuilder.buildFConstant(Ty, 1.0);
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auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
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auto BoolFP = MIRBuilder.buildSelect(Ty, Cmp, One, Zero);
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auto SignedOffset = MIRBuilder.buildFCopysign(Ty, BoolFP, X);
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MIRBuilder.buildFAdd(DstReg, T, Sel, Flags);
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MIRBuilder.buildFAdd(DstReg, T, SignedOffset, Flags);
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MI.eraseFromParent();
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return Legalized;
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@ -2429,18 +2429,16 @@ SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
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const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
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const SDValue One = DAG.getConstantFP(1.0, SL, VT);
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const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
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SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
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EVT SetCCVT =
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
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const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
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SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
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SDValue OneOrZeroFP = DAG.getNode(ISD::SELECT, SL, VT, Cmp, One, Zero);
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SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
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return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
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SDValue SignedOffset = DAG.getNode(ISD::FCOPYSIGN, SL, VT, OneOrZeroFP, X);
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return DAG.getNode(ISD::FADD, SL, VT, T, SignedOffset);
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}
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SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
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File diff suppressed because it is too large
Load Diff
@ -3794,14 +3794,14 @@ define half @v_fneg_round_f16(half %a) #0 {
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; SI-SAFE: ; %bb.0:
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; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
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; SI-SAFE-NEXT: s_brev_b32 s4, -2
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; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-SAFE-NEXT: v_trunc_f32_e32 v2, v0
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; SI-SAFE-NEXT: v_bfi_b32 v1, s4, 1.0, v0
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; SI-SAFE-NEXT: v_sub_f32_e32 v0, v0, v2
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; SI-SAFE-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
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; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; SI-SAFE-NEXT: v_add_f32_e32 v0, v2, v0
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; SI-SAFE-NEXT: v_trunc_f32_e32 v1, v0
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; SI-SAFE-NEXT: v_sub_f32_e32 v2, v0, v1
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; SI-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
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; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
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; SI-SAFE-NEXT: s_brev_b32 s4, -2
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; SI-SAFE-NEXT: v_bfi_b32 v0, s4, v2, v0
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; SI-SAFE-NEXT: v_add_f32_e32 v0, v1, v0
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; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
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;
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@ -3809,56 +3809,55 @@ define half @v_fneg_round_f16(half %a) #0 {
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; SI-NSZ: ; %bb.0:
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; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
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; SI-NSZ-NEXT: s_brev_b32 s4, -2
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; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-NSZ-NEXT: v_trunc_f32_e32 v2, v0
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; SI-NSZ-NEXT: v_bfi_b32 v1, s4, 1.0, v0
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; SI-NSZ-NEXT: v_sub_f32_e32 v0, v0, v2
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; SI-NSZ-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
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; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; SI-NSZ-NEXT: v_sub_f32_e64 v0, -v2, v0
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; SI-NSZ-NEXT: v_trunc_f32_e32 v1, v0
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; SI-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1
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; SI-NSZ-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
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; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
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; SI-NSZ-NEXT: s_brev_b32 s4, -2
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; SI-NSZ-NEXT: v_bfi_b32 v0, s4, v2, v0
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; SI-NSZ-NEXT: v_sub_f32_e64 v0, -v1, v0
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; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-SAFE-LABEL: v_fneg_round_f16:
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; VI-SAFE: ; %bb.0:
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; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-SAFE-NEXT: v_trunc_f16_e32 v1, v0
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; VI-SAFE-NEXT: v_sub_f16_e32 v2, v0, v1
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; VI-SAFE-NEXT: v_mov_b32_e32 v3, 0x3c00
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; VI-SAFE-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
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; VI-SAFE-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
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; VI-SAFE-NEXT: s_movk_i32 s4, 0x7fff
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; VI-SAFE-NEXT: v_mov_b32_e32 v1, 0x3c00
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; VI-SAFE-NEXT: v_trunc_f16_e32 v2, v0
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; VI-SAFE-NEXT: v_bfi_b32 v1, s4, v1, v0
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; VI-SAFE-NEXT: v_sub_f16_e32 v0, v0, v2
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; VI-SAFE-NEXT: v_cmp_ge_f16_e64 vcc, |v0|, 0.5
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; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; VI-SAFE-NEXT: v_add_f16_e32 v0, v2, v0
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; VI-SAFE-NEXT: v_bfi_b32 v0, s4, v2, v0
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; VI-SAFE-NEXT: v_add_f16_e32 v0, v1, v0
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; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
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; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-NSZ-LABEL: v_fneg_round_f16:
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; VI-NSZ: ; %bb.0:
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; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NSZ-NEXT: v_trunc_f16_e32 v1, v0
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; VI-NSZ-NEXT: v_sub_f16_e32 v2, v0, v1
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; VI-NSZ-NEXT: v_mov_b32_e32 v3, 0x3c00
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; VI-NSZ-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
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; VI-NSZ-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
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; VI-NSZ-NEXT: s_movk_i32 s4, 0x7fff
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; VI-NSZ-NEXT: v_mov_b32_e32 v1, 0x3c00
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; VI-NSZ-NEXT: v_trunc_f16_e32 v2, v0
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; VI-NSZ-NEXT: v_bfi_b32 v1, s4, v1, v0
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; VI-NSZ-NEXT: v_sub_f16_e32 v0, v0, v2
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; VI-NSZ-NEXT: v_cmp_ge_f16_e64 vcc, |v0|, 0.5
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; VI-NSZ-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; VI-NSZ-NEXT: v_sub_f16_e64 v0, -v2, v0
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; VI-NSZ-NEXT: v_bfi_b32 v0, s4, v2, v0
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; VI-NSZ-NEXT: v_sub_f16_e64 v0, -v1, v0
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; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-SAFE-LABEL: v_fneg_round_f16:
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; GFX11-SAFE: ; %bb.0:
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; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-SAFE-NEXT: v_trunc_f16_e32 v1, v0
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; GFX11-SAFE-NEXT: s_movk_i32 s0, 0x3c00
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; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
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; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-SAFE-NEXT: v_sub_f16_e32 v2, v0, v1
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; GFX11-SAFE-NEXT: v_bfi_b32 v0, 0x7fff, s0, v0
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; GFX11-SAFE-NEXT: v_cmp_ge_f16_e64 vcc_lo, |v2|, 0.5
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; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-SAFE-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
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; GFX11-SAFE-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
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; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
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; GFX11-SAFE-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
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; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-SAFE-NEXT: v_add_f16_e32 v0, v1, v0
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; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
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; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
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;
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@ -3866,13 +3865,13 @@ define half @v_fneg_round_f16(half %a) #0 {
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; GFX11-NSZ: ; %bb.0:
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; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NSZ-NEXT: v_trunc_f16_e32 v1, v0
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; GFX11-NSZ-NEXT: s_movk_i32 s0, 0x3c00
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; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
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; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NSZ-NEXT: v_sub_f16_e32 v2, v0, v1
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; GFX11-NSZ-NEXT: v_bfi_b32 v0, 0x7fff, s0, v0
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; GFX11-NSZ-NEXT: v_cmp_ge_f16_e64 vcc_lo, |v2|, 0.5
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; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NSZ-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
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; GFX11-NSZ-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
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; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
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; GFX11-NSZ-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
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; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NSZ-NEXT: v_sub_f16_e64 v0, -v1, v0
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; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
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%round = call half @llvm.round.f16(half %a)
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@ -2207,26 +2207,26 @@ define float @v_fneg_round_f32(float %a) #0 {
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; GCN-SAFE-LABEL: v_fneg_round_f32:
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; GCN-SAFE: ; %bb.0:
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; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-SAFE-NEXT: v_trunc_f32_e32 v1, v0
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; GCN-SAFE-NEXT: v_sub_f32_e32 v2, v0, v1
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; GCN-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
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; GCN-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
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; GCN-SAFE-NEXT: s_brev_b32 s4, -2
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; GCN-SAFE-NEXT: v_trunc_f32_e32 v2, v0
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; GCN-SAFE-NEXT: v_bfi_b32 v1, s4, 1.0, v0
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; GCN-SAFE-NEXT: v_sub_f32_e32 v0, v0, v2
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; GCN-SAFE-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
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; GCN-SAFE-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; GCN-SAFE-NEXT: v_add_f32_e32 v0, v2, v0
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; GCN-SAFE-NEXT: v_bfi_b32 v0, s4, v2, v0
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; GCN-SAFE-NEXT: v_add_f32_e32 v0, v1, v0
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; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
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;
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; GCN-NSZ-LABEL: v_fneg_round_f32:
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; GCN-NSZ: ; %bb.0:
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; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NSZ-NEXT: v_trunc_f32_e32 v1, v0
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; GCN-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1
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; GCN-NSZ-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
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; GCN-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
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; GCN-NSZ-NEXT: s_brev_b32 s4, -2
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; GCN-NSZ-NEXT: v_trunc_f32_e32 v2, v0
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; GCN-NSZ-NEXT: v_bfi_b32 v1, s4, 1.0, v0
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; GCN-NSZ-NEXT: v_sub_f32_e32 v0, v0, v2
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; GCN-NSZ-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
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; GCN-NSZ-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; GCN-NSZ-NEXT: v_sub_f32_e64 v0, -v2, v0
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; GCN-NSZ-NEXT: v_bfi_b32 v0, s4, v2, v0
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; GCN-NSZ-NEXT: v_sub_f32_e64 v0, -v1, v0
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; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
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%round = call float @llvm.round.f32(float %a)
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%fneg = fneg float %round
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@ -455,13 +455,13 @@ define float @v_test_known_not_snan_round_input_fmed3_r_i_i_f32(float %a) #0 {
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; GCN-LABEL: v_test_known_not_snan_round_input_fmed3_r_i_i_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_trunc_f32_e32 v1, v0
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; GCN-NEXT: v_sub_f32_e32 v2, v0, v1
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; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
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; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
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; GCN-NEXT: s_brev_b32 s4, -2
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; GCN-NEXT: v_trunc_f32_e32 v2, v0
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; GCN-NEXT: v_bfi_b32 v1, s4, 1.0, v0
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; GCN-NEXT: v_sub_f32_e32 v0, v0, v2
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; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
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; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; GCN-NEXT: v_add_f32_e32 v0, v2, v0
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; GCN-NEXT: v_bfi_b32 v0, s4, v2, v0
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; GCN-NEXT: v_add_f32_e32 v0, v1, v0
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; GCN-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%known.not.snan = call float @llvm.round.f32(float %a)
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@ -9,30 +9,32 @@ define amdgpu_kernel void @round_f64(ptr addrspace(1) %out, double %x) #0 {
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s5, 0xfffff
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; SI-NEXT: s_mov_b32 s4, s6
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_bfe_u32 s8, s3, 0xb0014
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; SI-NEXT: s_addk_i32 s8, 0xfc01
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; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
|
||||
; SI-NEXT: s_bfe_u32 s7, s3, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s7, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s7
|
||||
; SI-NEXT: s_and_b32 s8, s3, 0x80000000
|
||||
; SI-NEXT: s_andn2_b64 s[4:5], s[2:3], s[4:5]
|
||||
; SI-NEXT: s_and_b32 s10, s3, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s8, 0
|
||||
; SI-NEXT: s_cmp_lt_i32 s7, 0
|
||||
; SI-NEXT: s_cselect_b32 s4, 0, s4
|
||||
; SI-NEXT: s_cselect_b32 s5, s10, s5
|
||||
; SI-NEXT: s_cmp_gt_i32 s8, 51
|
||||
; SI-NEXT: s_cselect_b32 s5, s8, s5
|
||||
; SI-NEXT: s_cmp_gt_i32 s7, 51
|
||||
; SI-NEXT: s_cselect_b32 s8, s2, s4
|
||||
; SI-NEXT: s_cselect_b32 s9, s3, s5
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s8
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s9
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[2:3], -v[0:1]
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[2:3], |v[0:1]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s0, s10, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
|
||||
; SI-NEXT: s_cselect_b32 s0, s0, 0
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[10:11], |v[0:1]|, 0.5
|
||||
; SI-NEXT: s_brev_b32 s2, -2
|
||||
; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec
|
||||
; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s0
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; SI-NEXT: v_bfi_b32 v1, s2, v0, v1
|
||||
; SI-NEXT: v_mov_b32_e32 v0, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s0
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[8:9], v[0:1]
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
@ -40,19 +42,21 @@ define amdgpu_kernel void @round_f64(ptr addrspace(1) %out, double %x) #0 {
|
||||
; CI-LABEL: round_f64:
|
||||
; CI: ; %bb.0:
|
||||
; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; CI-NEXT: s_mov_b32 s8, 0
|
||||
; CI-NEXT: s_brev_b32 s5, -2
|
||||
; CI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; CI-NEXT: s_mov_b32 s6, -1
|
||||
; CI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[2:3]
|
||||
; CI-NEXT: s_mov_b32 s4, s0
|
||||
; CI-NEXT: v_add_f64 v[2:3], s[2:3], -v[0:1]
|
||||
; CI-NEXT: s_and_b32 s0, s3, 0x80000000
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[2:3], |v[2:3]|, 0.5
|
||||
; CI-NEXT: s_or_b32 s0, s0, 0x3ff00000
|
||||
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
|
||||
; CI-NEXT: s_cselect_b32 s9, s0, 0
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[0:1], s[8:9]
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[8:9], |v[2:3]|, 0.5
|
||||
; CI-NEXT: v_mov_b32_e32 v2, s3
|
||||
; CI-NEXT: s_and_b64 s[2:3], s[8:9], exec
|
||||
; CI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
|
||||
; CI-NEXT: v_mov_b32_e32 v3, s0
|
||||
; CI-NEXT: v_bfi_b32 v3, s5, v3, v2
|
||||
; CI-NEXT: v_mov_b32_e32 v2, 0
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
|
||||
; CI-NEXT: s_mov_b32 s5, s1
|
||||
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; CI-NEXT: s_endpgm
|
||||
@ -75,6 +79,7 @@ define amdgpu_kernel void @v_round_f64(ptr addrspace(1) %out, ptr addrspace(1) %
|
||||
; SI-NEXT: s_movk_i32 s4, 0xfc01
|
||||
; SI-NEXT: s_mov_b32 s2, -1
|
||||
; SI-NEXT: s_mov_b32 s3, 0xfffff
|
||||
; SI-NEXT: v_mov_b32_e32 v8, 0x3ff00000
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_bfe_u32 v4, v3, 20, 11
|
||||
; SI-NEXT: v_add_i32_e32 v6, vcc, s4, v4
|
||||
@ -90,11 +95,12 @@ define amdgpu_kernel void @v_round_f64(ptr addrspace(1) %out, ptr addrspace(1) %
|
||||
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v6
|
||||
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
|
||||
; SI-NEXT: v_add_f64 v[2:3], v[2:3], -v[4:5]
|
||||
; SI-NEXT: v_or_b32_e32 v6, 0x3ff00000, v7
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
|
||||
; SI-NEXT: v_add_f64 v[6:7], v[2:3], -v[4:5]
|
||||
; SI-NEXT: s_brev_b32 s2, -2
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
|
||||
; SI-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
|
||||
; SI-NEXT: v_bfi_b32 v3, s2, v2, v3
|
||||
; SI-NEXT: v_mov_b32_e32 v2, v1
|
||||
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
|
||||
; SI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
|
||||
; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
|
||||
; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
|
||||
@ -110,16 +116,17 @@ define amdgpu_kernel void @v_round_f64(ptr addrspace(1) %out, ptr addrspace(1) %
|
||||
; CI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
|
||||
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
|
||||
; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
|
||||
; CI-NEXT: v_mov_b32_e32 v8, 0x3ff00000
|
||||
; CI-NEXT: s_brev_b32 s2, -2
|
||||
; CI-NEXT: s_waitcnt vmcnt(0)
|
||||
; CI-NEXT: v_trunc_f64_e32 v[4:5], v[2:3]
|
||||
; CI-NEXT: v_and_b32_e32 v6, 0x80000000, v3
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[2:3], -v[4:5]
|
||||
; CI-NEXT: v_or_b32_e32 v6, 0x3ff00000, v6
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
|
||||
; CI-NEXT: v_add_f64 v[6:7], v[2:3], -v[4:5]
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
|
||||
; CI-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
|
||||
; CI-NEXT: v_bfi_b32 v3, s2, v2, v3
|
||||
; CI-NEXT: v_mov_b32_e32 v2, v1
|
||||
; CI-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
|
||||
; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
|
||||
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
|
||||
; CI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
@ -154,12 +161,12 @@ define amdgpu_kernel void @round_v2f64(ptr addrspace(1) %out, <2 x double> %in)
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s10
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s11
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[6:7], -v[0:1]
|
||||
; SI-NEXT: s_or_b32 s3, s12, 0x3ff00000
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_mov_b32_e32 v0, 0
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; SI-NEXT: v_mov_b32_e32 v4, s5
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[12:13], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s5, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], s3
|
||||
@ -173,13 +180,16 @@ define amdgpu_kernel void @round_v2f64(ptr addrspace(1) %out, <2 x double> %in)
|
||||
; SI-NEXT: s_cselect_b32 s7, s5, s7
|
||||
; SI-NEXT: v_mov_b32_e32 v2, s6
|
||||
; SI-NEXT: v_mov_b32_e32 v3, s7
|
||||
; SI-NEXT: v_add_f64 v[4:5], s[4:5], -v[2:3]
|
||||
; SI-NEXT: s_or_b32 s3, s8, 0x3ff00000
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[4:5]|, 0.5
|
||||
; SI-NEXT: v_add_f64 v[2:3], s[4:5], -v[2:3]
|
||||
; SI-NEXT: s_brev_b32 s12, -2
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[8:9], |v[2:3]|, 0.5
|
||||
; SI-NEXT: v_bfi_b32 v1, s12, v0, v1
|
||||
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
|
||||
; SI-NEXT: v_mov_b32_e32 v0, 0
|
||||
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
|
||||
; SI-NEXT: v_add_f64 v[2:3], s[10:11], v[0:1]
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; SI-NEXT: v_bfi_b32 v1, s12, v1, v4
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[6:7], v[0:1]
|
||||
; SI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
||||
@ -189,25 +199,28 @@ define amdgpu_kernel void @round_v2f64(ptr addrspace(1) %out, <2 x double> %in)
|
||||
; CI: ; %bb.0:
|
||||
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
|
||||
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; CI-NEXT: s_mov_b32 s8, 0
|
||||
; CI-NEXT: s_brev_b32 s2, -2
|
||||
; CI-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; CI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[6:7]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[4:5]
|
||||
; CI-NEXT: v_add_f64 v[2:3], s[6:7], -v[0:1]
|
||||
; CI-NEXT: s_and_b32 s2, s7, 0x80000000
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[2:3]|, 0.5
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_add_f64 v[6:7], s[4:5], -v[4:5]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[2:3], s[6:7]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[6:7], s[4:5]
|
||||
; CI-NEXT: v_add_f64 v[4:5], s[6:7], -v[2:3]
|
||||
; CI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[4:5]|, 0.5
|
||||
; CI-NEXT: v_add_f64 v[4:5], s[4:5], -v[6:7]
|
||||
; CI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; CI-NEXT: s_cselect_b32 s9, s2, 0
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[6:7]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s5, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[6:7], exec
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[0:1], s[8:9]
|
||||
; CI-NEXT: s_cselect_b32 s9, s2, 0
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[4:5], s[8:9]
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[4:5]|, 0.5
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_mov_b32_e32 v8, s4
|
||||
; CI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; CI-NEXT: v_bfi_b32 v1, s2, v8, v1
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[2:3], v[0:1]
|
||||
; CI-NEXT: v_mov_b32_e32 v1, s4
|
||||
; CI-NEXT: v_mov_b32_e32 v4, s5
|
||||
; CI-NEXT: v_bfi_b32 v1, s2, v1, v4
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[6:7], v[0:1]
|
||||
; CI-NEXT: s_mov_b32 s2, -1
|
||||
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
||||
; CI-NEXT: s_endpgm
|
||||
@ -223,7 +236,7 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
|
||||
; SI-NEXT: s_mov_b32 s2, -1
|
||||
; SI-NEXT: s_mov_b32 s13, 0xfffff
|
||||
; SI-NEXT: s_mov_b32 s12, s2
|
||||
; SI-NEXT: v_mov_b32_e32 v4, 0
|
||||
; SI-NEXT: s_brev_b32 s18, -2
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_bfe_u32 s3, s7, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
@ -239,12 +252,12 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s14
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s15
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[6:7], -v[0:1]
|
||||
; SI-NEXT: s_or_b32 s3, s16, 0x3ff00000
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[0:1]|, 0.5
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s3
|
||||
; SI-NEXT: v_mov_b32_e32 v4, 0
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[16:17], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; SI-NEXT: s_and_b64 s[16:17], s[16:17], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s5, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[12:13], s3
|
||||
@ -255,15 +268,16 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
|
||||
; SI-NEXT: s_cselect_b32 s7, s16, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s6, s4, s6
|
||||
; SI-NEXT: v_bfi_b32 v5, s18, v0, v1
|
||||
; SI-NEXT: s_cselect_b32 s7, s5, s7
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s6
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[4:5], -v[0:1]
|
||||
; SI-NEXT: s_or_b32 s3, s16, 0x3ff00000
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_add_f64 v[2:3], s[14:15], v[4:5]
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[16:17], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_mov_b32_e32 v6, s5
|
||||
; SI-NEXT: s_and_b64 s[14:15], s[16:17], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s11, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
@ -278,13 +292,13 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
|
||||
; SI-NEXT: s_cselect_b32 s5, s11, s5
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s4
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s5
|
||||
; SI-NEXT: v_add_f64 v[6:7], s[10:11], -v[0:1]
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[10:11], -v[0:1]
|
||||
; SI-NEXT: v_bfi_b32 v5, s18, v5, v6
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[14:15], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[6:7], v[4:5]
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[6:7]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s3, s14, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s3
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[14:15], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v8, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s9, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[12:13], s3
|
||||
@ -296,15 +310,19 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s6, s8, s6
|
||||
; SI-NEXT: s_cselect_b32 s7, s9, s7
|
||||
; SI-NEXT: v_mov_b32_e32 v6, s6
|
||||
; SI-NEXT: v_mov_b32_e32 v7, s7
|
||||
; SI-NEXT: v_add_f64 v[8:9], s[8:9], -v[6:7]
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s6
|
||||
; SI-NEXT: v_mov_b32_e32 v6, s7
|
||||
; SI-NEXT: v_add_f64 v[6:7], s[8:9], -v[5:6]
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s11
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[10:11], |v[6:7]|, 0.5
|
||||
; SI-NEXT: v_bfi_b32 v5, s18, v8, v9
|
||||
; SI-NEXT: v_add_f64 v[6:7], s[4:5], v[4:5]
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[8:9]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s3, s10, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[10:11], exec
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s3
|
||||
; SI-NEXT: v_mov_b32_e32 v8, s9
|
||||
; SI-NEXT: v_bfi_b32 v5, s18, v5, v8
|
||||
; SI-NEXT: v_add_f64 v[4:5], s[6:7], v[4:5]
|
||||
; SI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@ -315,42 +333,47 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
|
||||
; CI-LABEL: round_v4f64:
|
||||
; CI: ; %bb.0:
|
||||
; CI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x11
|
||||
; CI-NEXT: s_mov_b32 s12, 0
|
||||
; CI-NEXT: s_brev_b32 s2, -2
|
||||
; CI-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; CI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; CI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[6:7]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[4:5]
|
||||
; CI-NEXT: v_mov_b32_e32 v5, s7
|
||||
; CI-NEXT: v_add_f64 v[2:3], s[6:7], -v[0:1]
|
||||
; CI-NEXT: s_and_b32 s2, s7, 0x80000000
|
||||
; CI-NEXT: v_trunc_f64_e32 v[6:7], s[4:5]
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[2:3]|, 0.5
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_add_f64 v[6:7], s[4:5], -v[4:5]
|
||||
; CI-NEXT: v_add_f64 v[2:3], s[4:5], -v[6:7]
|
||||
; CI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; CI-NEXT: s_cselect_b32 s13, s2, 0
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[6:7]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s5, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_trunc_f64_e32 v[6:7], s[10:11]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[6:7], exec
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[0:1], s[12:13]
|
||||
; CI-NEXT: s_cselect_b32 s13, s2, 0
|
||||
; CI-NEXT: v_add_f64 v[8:9], s[10:11], -v[6:7]
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[4:5], s[12:13]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[8:9]
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[8:9]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s11, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_add_f64 v[8:9], s[8:9], -v[4:5]
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_mov_b32_e32 v8, s4
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[2:3]|, 0.5
|
||||
; CI-NEXT: v_bfi_b32 v5, s2, v8, v5
|
||||
; CI-NEXT: v_trunc_f64_e32 v[8:9], s[10:11]
|
||||
; CI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[4:5]
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_add_f64 v[0:1], s[10:11], -v[8:9]
|
||||
; CI-NEXT: v_mov_b32_e32 v5, s4
|
||||
; CI-NEXT: v_mov_b32_e32 v10, s5
|
||||
; CI-NEXT: v_bfi_b32 v5, s2, v5, v10
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[0:1]|, 0.5
|
||||
; CI-NEXT: v_trunc_f64_e32 v[10:11], s[8:9]
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[6:7], v[4:5]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: s_cselect_b32 s13, s2, 0
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[8:9]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s9, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_add_f64 v[6:7], s[8:9], -v[10:11]
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_mov_b32_e32 v5, s4
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[6:7]|, 0.5
|
||||
; CI-NEXT: v_mov_b32_e32 v12, s11
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_add_f64 v[6:7], v[6:7], s[12:13]
|
||||
; CI-NEXT: s_cselect_b32 s13, s2, 0
|
||||
; CI-NEXT: v_add_f64 v[4:5], v[4:5], s[12:13]
|
||||
; CI-NEXT: v_bfi_b32 v5, s2, v5, v12
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
|
||||
; CI-NEXT: v_mov_b32_e32 v5, s4
|
||||
; CI-NEXT: v_mov_b32_e32 v8, s9
|
||||
; CI-NEXT: v_bfi_b32 v5, s2, v5, v8
|
||||
; CI-NEXT: v_add_f64 v[4:5], v[10:11], v[4:5]
|
||||
; CI-NEXT: s_mov_b32 s2, -1
|
||||
; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
||||
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
||||
@ -383,152 +406,161 @@ define amdgpu_kernel void @round_v8f64(ptr addrspace(1) %out, <8 x double> %in)
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s22
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s23
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[6:7], -v[0:1]
|
||||
; SI-NEXT: s_or_b32 s3, s24, 0x3ff00000
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[0:1]|, 0.5
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s5, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], s3
|
||||
; SI-NEXT: s_brev_b32 s3, -2
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[24:25], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; SI-NEXT: s_and_b64 s[24:25], s[24:25], exec
|
||||
; SI-NEXT: s_cselect_b32 s6, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s6
|
||||
; SI-NEXT: s_bfe_u32 s6, s5, 0xb0014
|
||||
; SI-NEXT: s_add_i32 s24, s6, 0xfffffc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], s24
|
||||
; SI-NEXT: s_andn2_b64 s[6:7], s[4:5], s[6:7]
|
||||
; SI-NEXT: s_and_b32 s24, s5, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s3, 0
|
||||
; SI-NEXT: s_and_b32 s25, s5, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s24, 0
|
||||
; SI-NEXT: s_cselect_b32 s6, 0, s6
|
||||
; SI-NEXT: s_cselect_b32 s7, s24, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s7, s25, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s24, 51
|
||||
; SI-NEXT: s_cselect_b32 s6, s4, s6
|
||||
; SI-NEXT: v_bfi_b32 v9, s3, v0, v1
|
||||
; SI-NEXT: s_cselect_b32 s7, s5, s7
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s6
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[4:5], -v[0:1]
|
||||
; SI-NEXT: s_or_b32 s3, s24, 0x3ff00000
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_add_f64 v[2:3], s[22:23], v[8:9]
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s11, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], s3
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[24:25], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s5
|
||||
; SI-NEXT: s_and_b64 s[22:23], s[24:25], exec
|
||||
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v4, s4
|
||||
; SI-NEXT: s_bfe_u32 s4, s11, 0xb0014
|
||||
; SI-NEXT: s_add_i32 s22, s4, 0xfffffc01
|
||||
; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], s22
|
||||
; SI-NEXT: s_andn2_b64 s[4:5], s[10:11], s[4:5]
|
||||
; SI-NEXT: s_and_b32 s22, s11, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s3, 0
|
||||
; SI-NEXT: s_and_b32 s23, s11, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s22, 0
|
||||
; SI-NEXT: s_cselect_b32 s4, 0, s4
|
||||
; SI-NEXT: s_cselect_b32 s5, s22, s5
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s5, s23, s5
|
||||
; SI-NEXT: s_cmp_gt_i32 s22, 51
|
||||
; SI-NEXT: s_cselect_b32 s4, s10, s4
|
||||
; SI-NEXT: s_cselect_b32 s5, s11, s5
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s4
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s5
|
||||
; SI-NEXT: v_add_f64 v[4:5], s[10:11], -v[0:1]
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[10:11], -v[0:1]
|
||||
; SI-NEXT: v_bfi_b32 v9, s3, v4, v5
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[22:23], |v[0:1]|, 0.5
|
||||
; SI-NEXT: v_add_f64 v[0:1], s[6:7], v[8:9]
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[4:5]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s3, s22, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s9, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], s3
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[22:23], exec
|
||||
; SI-NEXT: s_cselect_b32 s6, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v6, s6
|
||||
; SI-NEXT: s_bfe_u32 s6, s9, 0xb0014
|
||||
; SI-NEXT: s_add_i32 s10, s6, 0xfffffc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], s10
|
||||
; SI-NEXT: v_mov_b32_e32 v7, s11
|
||||
; SI-NEXT: s_andn2_b64 s[6:7], s[8:9], s[6:7]
|
||||
; SI-NEXT: s_and_b32 s10, s9, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s3, 0
|
||||
; SI-NEXT: s_and_b32 s11, s9, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s10, 0
|
||||
; SI-NEXT: s_cselect_b32 s6, 0, s6
|
||||
; SI-NEXT: s_cselect_b32 s7, s10, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s7, s11, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s10, 51
|
||||
; SI-NEXT: s_cselect_b32 s6, s8, s6
|
||||
; SI-NEXT: s_cselect_b32 s7, s9, s7
|
||||
; SI-NEXT: v_mov_b32_e32 v4, s6
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s7
|
||||
; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[4:5]
|
||||
; SI-NEXT: v_bfi_b32 v9, s3, v6, v7
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[10:11], |v[4:5]|, 0.5
|
||||
; SI-NEXT: v_add_f64 v[6:7], s[4:5], v[8:9]
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[4:5]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s3, s10, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s15, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], s3
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[10:11], exec
|
||||
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s4
|
||||
; SI-NEXT: s_bfe_u32 s4, s15, 0xb0014
|
||||
; SI-NEXT: s_add_i32 s8, s4, 0xfffffc01
|
||||
; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], s8
|
||||
; SI-NEXT: v_mov_b32_e32 v10, s9
|
||||
; SI-NEXT: s_andn2_b64 s[4:5], s[14:15], s[4:5]
|
||||
; SI-NEXT: s_and_b32 s8, s15, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s3, 0
|
||||
; SI-NEXT: s_and_b32 s9, s15, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s8, 0
|
||||
; SI-NEXT: s_cselect_b32 s4, 0, s4
|
||||
; SI-NEXT: s_cselect_b32 s5, s8, s5
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s5, s9, s5
|
||||
; SI-NEXT: s_cmp_gt_i32 s8, 51
|
||||
; SI-NEXT: s_cselect_b32 s4, s14, s4
|
||||
; SI-NEXT: s_cselect_b32 s5, s15, s5
|
||||
; SI-NEXT: v_mov_b32_e32 v4, s4
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s5
|
||||
; SI-NEXT: v_add_f64 v[10:11], s[14:15], -v[4:5]
|
||||
; SI-NEXT: v_add_f64 v[4:5], s[14:15], -v[4:5]
|
||||
; SI-NEXT: v_bfi_b32 v9, s3, v9, v10
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[8:9], |v[4:5]|, 0.5
|
||||
; SI-NEXT: v_add_f64 v[4:5], s[6:7], v[8:9]
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[10:11]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s3, s8, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s13, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], s3
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[8:9], exec
|
||||
; SI-NEXT: s_cselect_b32 s6, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v12, s6
|
||||
; SI-NEXT: s_bfe_u32 s6, s13, 0xb0014
|
||||
; SI-NEXT: s_add_i32 s8, s6, 0xfffffc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], s8
|
||||
; SI-NEXT: s_andn2_b64 s[6:7], s[12:13], s[6:7]
|
||||
; SI-NEXT: s_and_b32 s8, s13, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s3, 0
|
||||
; SI-NEXT: s_and_b32 s9, s13, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s8, 0
|
||||
; SI-NEXT: s_cselect_b32 s6, 0, s6
|
||||
; SI-NEXT: s_cselect_b32 s7, s8, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s7, s9, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s8, 51
|
||||
; SI-NEXT: s_cselect_b32 s7, s13, s7
|
||||
; SI-NEXT: s_cselect_b32 s6, s12, s6
|
||||
; SI-NEXT: v_mov_b32_e32 v11, s7
|
||||
; SI-NEXT: v_mov_b32_e32 v10, s6
|
||||
; SI-NEXT: v_add_f64 v[10:11], s[12:13], -v[10:11]
|
||||
; SI-NEXT: v_mov_b32_e32 v10, s7
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s6
|
||||
; SI-NEXT: v_add_f64 v[10:11], s[12:13], -v[9:10]
|
||||
; SI-NEXT: v_mov_b32_e32 v13, s15
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[8:9], |v[10:11]|, 0.5
|
||||
; SI-NEXT: v_bfi_b32 v9, s3, v12, v13
|
||||
; SI-NEXT: v_add_f64 v[12:13], s[4:5], v[8:9]
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[10:11]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s3, s8, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s19, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], s3
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[8:9], exec
|
||||
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v14, s4
|
||||
; SI-NEXT: s_bfe_u32 s4, s19, 0xb0014
|
||||
; SI-NEXT: s_add_i32 s8, s4, 0xfffffc01
|
||||
; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], s8
|
||||
; SI-NEXT: s_andn2_b64 s[4:5], s[18:19], s[4:5]
|
||||
; SI-NEXT: s_and_b32 s8, s19, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s3, 0
|
||||
; SI-NEXT: s_and_b32 s9, s19, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s8, 0
|
||||
; SI-NEXT: s_cselect_b32 s4, 0, s4
|
||||
; SI-NEXT: s_cselect_b32 s5, s8, s5
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s5, s9, s5
|
||||
; SI-NEXT: s_cmp_gt_i32 s8, 51
|
||||
; SI-NEXT: s_cselect_b32 s5, s19, s5
|
||||
; SI-NEXT: s_cselect_b32 s4, s18, s4
|
||||
; SI-NEXT: v_mov_b32_e32 v11, s5
|
||||
; SI-NEXT: v_mov_b32_e32 v10, s4
|
||||
; SI-NEXT: v_add_f64 v[14:15], s[18:19], -v[10:11]
|
||||
; SI-NEXT: v_mov_b32_e32 v10, s5
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s4
|
||||
; SI-NEXT: v_add_f64 v[10:11], s[18:19], -v[9:10]
|
||||
; SI-NEXT: v_mov_b32_e32 v15, s13
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[8:9], |v[10:11]|, 0.5
|
||||
; SI-NEXT: v_bfi_b32 v9, s3, v14, v15
|
||||
; SI-NEXT: v_add_f64 v[10:11], s[6:7], v[8:9]
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[14:15]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s3, s8, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s3
|
||||
; SI-NEXT: s_bfe_u32 s3, s17, 0xb0014
|
||||
; SI-NEXT: s_addk_i32 s3, 0xfc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], s3
|
||||
; SI-NEXT: s_and_b64 s[6:7], s[8:9], exec
|
||||
; SI-NEXT: s_cselect_b32 s6, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s6
|
||||
; SI-NEXT: s_bfe_u32 s6, s17, 0xb0014
|
||||
; SI-NEXT: s_add_i32 s8, s6, 0xfffffc01
|
||||
; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], s8
|
||||
; SI-NEXT: s_andn2_b64 s[6:7], s[16:17], s[6:7]
|
||||
; SI-NEXT: s_and_b32 s8, s17, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s3, 0
|
||||
; SI-NEXT: s_and_b32 s9, s17, 0x80000000
|
||||
; SI-NEXT: s_cmp_lt_i32 s8, 0
|
||||
; SI-NEXT: s_cselect_b32 s6, 0, s6
|
||||
; SI-NEXT: s_cselect_b32 s7, s8, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s3, 51
|
||||
; SI-NEXT: s_cselect_b32 s7, s9, s7
|
||||
; SI-NEXT: s_cmp_gt_i32 s8, 51
|
||||
; SI-NEXT: s_cselect_b32 s7, s17, s7
|
||||
; SI-NEXT: s_cselect_b32 s6, s16, s6
|
||||
; SI-NEXT: v_mov_b32_e32 v15, s7
|
||||
; SI-NEXT: v_mov_b32_e32 v14, s6
|
||||
; SI-NEXT: v_add_f64 v[14:15], s[16:17], -v[14:15]
|
||||
; SI-NEXT: v_mov_b32_e32 v16, s19
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[8:9], |v[14:15]|, 0.5
|
||||
; SI-NEXT: v_bfi_b32 v9, s3, v9, v16
|
||||
; SI-NEXT: v_add_f64 v[16:17], s[4:5], v[8:9]
|
||||
; SI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[14:15]|, 0.5
|
||||
; SI-NEXT: s_or_b32 s3, s8, 0x3ff00000
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; SI-NEXT: s_cselect_b32 s3, s3, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s3
|
||||
; SI-NEXT: s_and_b64 s[4:5], s[8:9], exec
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s4
|
||||
; SI-NEXT: v_mov_b32_e32 v14, s17
|
||||
; SI-NEXT: v_bfi_b32 v9, s3, v9, v14
|
||||
; SI-NEXT: v_add_f64 v[14:15], s[6:7], v[8:9]
|
||||
; SI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@ -541,74 +573,83 @@ define amdgpu_kernel void @round_v8f64(ptr addrspace(1) %out, <8 x double> %in)
|
||||
; CI-LABEL: round_v8f64:
|
||||
; CI: ; %bb.0:
|
||||
; CI-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x19
|
||||
; CI-NEXT: s_mov_b32 s20, 0
|
||||
; CI-NEXT: s_brev_b32 s2, -2
|
||||
; CI-NEXT: v_mov_b32_e32 v12, 0
|
||||
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; CI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; CI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[6:7]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[4:5]
|
||||
; CI-NEXT: v_add_f64 v[2:3], s[6:7], -v[0:1]
|
||||
; CI-NEXT: s_and_b32 s2, s7, 0x80000000
|
||||
; CI-NEXT: v_mov_b32_e32 v6, s7
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[2:3]|, 0.5
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_add_f64 v[6:7], s[4:5], -v[4:5]
|
||||
; CI-NEXT: v_add_f64 v[2:3], s[4:5], -v[4:5]
|
||||
; CI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[2:3]|, 0.5
|
||||
; CI-NEXT: v_mov_b32_e32 v7, s4
|
||||
; CI-NEXT: v_bfi_b32 v13, s2, v7, v6
|
||||
; CI-NEXT: s_and_b64 s[6:7], s[6:7], exec
|
||||
; CI-NEXT: s_cselect_b32 s21, s2, 0
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[6:7], |v[6:7]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s5, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_trunc_f64_e32 v[6:7], s[10:11]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[6:7], exec
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[0:1], s[20:21]
|
||||
; CI-NEXT: s_cselect_b32 s21, s2, 0
|
||||
; CI-NEXT: v_add_f64 v[8:9], s[10:11], -v[6:7]
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[4:5], s[20:21]
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[12:13]
|
||||
; CI-NEXT: v_mov_b32_e32 v8, s4
|
||||
; CI-NEXT: v_mov_b32_e32 v9, s5
|
||||
; CI-NEXT: v_add_f64 v[0:1], s[10:11], -v[6:7]
|
||||
; CI-NEXT: v_bfi_b32 v13, s2, v8, v9
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[0:1]|, 0.5
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[4:5], v[12:13]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[8:9]
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[8:9]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s11, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_add_f64 v[8:9], s[8:9], -v[4:5]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_add_f64 v[8:9], s[8:9], -v[4:5]
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_mov_b32_e32 v10, s4
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[8:9]|, 0.5
|
||||
; CI-NEXT: v_trunc_f64_e32 v[8:9], s[14:15]
|
||||
; CI-NEXT: s_cselect_b32 s21, s2, 0
|
||||
; CI-NEXT: s_and_b32 s2, s9, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_mov_b32_e32 v11, s11
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_bfi_b32 v13, s2, v10, v11
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_add_f64 v[10:11], s[14:15], -v[8:9]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_trunc_f64_e32 v[12:13], s[12:13]
|
||||
; CI-NEXT: v_add_f64 v[6:7], v[6:7], s[20:21]
|
||||
; CI-NEXT: s_cselect_b32 s21, s2, 0
|
||||
; CI-NEXT: v_add_f64 v[6:7], v[6:7], v[12:13]
|
||||
; CI-NEXT: v_mov_b32_e32 v13, s4
|
||||
; CI-NEXT: v_mov_b32_e32 v14, s9
|
||||
; CI-NEXT: v_bfi_b32 v13, s2, v13, v14
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[10:11]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s15, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_add_f64 v[14:15], s[12:13], -v[12:13]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[14:15], s[12:13]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_add_f64 v[4:5], v[4:5], s[20:21]
|
||||
; CI-NEXT: s_cselect_b32 s21, s2, 0
|
||||
; CI-NEXT: v_add_f64 v[10:11], s[12:13], -v[14:15]
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_add_f64 v[4:5], v[4:5], v[12:13]
|
||||
; CI-NEXT: v_mov_b32_e32 v13, s4
|
||||
; CI-NEXT: v_mov_b32_e32 v16, s15
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[10:11]|, 0.5
|
||||
; CI-NEXT: v_bfi_b32 v13, s2, v13, v16
|
||||
; CI-NEXT: v_trunc_f64_e32 v[16:17], s[18:19]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_add_f64 v[10:11], v[8:9], v[12:13]
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_add_f64 v[8:9], s[18:19], -v[16:17]
|
||||
; CI-NEXT: v_mov_b32_e32 v13, s4
|
||||
; CI-NEXT: v_mov_b32_e32 v18, s13
|
||||
; CI-NEXT: v_bfi_b32 v13, s2, v13, v18
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[8:9]|, 0.5
|
||||
; CI-NEXT: v_trunc_f64_e32 v[18:19], s[16:17]
|
||||
; CI-NEXT: v_add_f64 v[8:9], v[14:15], v[12:13]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_add_f64 v[14:15], s[16:17], -v[18:19]
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_mov_b32_e32 v13, s4
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[14:15]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s13, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_trunc_f64_e32 v[14:15], s[18:19]
|
||||
; CI-NEXT: v_mov_b32_e32 v20, s19
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_add_f64 v[10:11], v[8:9], s[20:21]
|
||||
; CI-NEXT: s_cselect_b32 s21, s2, 0
|
||||
; CI-NEXT: v_add_f64 v[16:17], s[18:19], -v[14:15]
|
||||
; CI-NEXT: v_add_f64 v[8:9], v[12:13], s[20:21]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[12:13], s[16:17]
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[16:17]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s19, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: v_add_f64 v[16:17], s[16:17], -v[12:13]
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: s_cselect_b32 s21, s2, 0
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 s[4:5], |v[16:17]|, 0.5
|
||||
; CI-NEXT: s_and_b32 s2, s17, 0x80000000
|
||||
; CI-NEXT: s_or_b32 s2, s2, 0x3ff00000
|
||||
; CI-NEXT: s_and_b64 s[4:5], s[4:5], exec
|
||||
; CI-NEXT: v_add_f64 v[14:15], v[14:15], s[20:21]
|
||||
; CI-NEXT: s_cselect_b32 s21, s2, 0
|
||||
; CI-NEXT: v_add_f64 v[12:13], v[12:13], s[20:21]
|
||||
; CI-NEXT: v_bfi_b32 v13, s2, v13, v20
|
||||
; CI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
|
||||
; CI-NEXT: v_add_f64 v[14:15], v[16:17], v[12:13]
|
||||
; CI-NEXT: v_mov_b32_e32 v13, s4
|
||||
; CI-NEXT: v_mov_b32_e32 v16, s17
|
||||
; CI-NEXT: v_bfi_b32 v13, s2, v13, v16
|
||||
; CI-NEXT: v_add_f64 v[12:13], v[18:19], v[12:13]
|
||||
; CI-NEXT: s_mov_b32 s2, -1
|
||||
; CI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
|
||||
; CI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
|
||||
|
||||
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Reference in New Issue
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