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[RISCV] Further expand coverage for insert_vector_elt patterns
This commit is contained in:
Philip Reames
Philip Reames
parent
066c4524bc
commit
1aa493f064
241
llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
Normal file
241
llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
Normal file
@ -0,0 +1,241 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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define void @v4xi8_concat_vector_insert_idx0(ptr %a, ptr %b, i8 %x) {
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; CHECK-LABEL: v4xi8_concat_vector_insert_idx0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v9, (a1)
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 2
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; CHECK-NEXT: vmv.s.x v9, a2
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; CHECK-NEXT: vsetivli zero, 2, e8, mf4, tu, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 1
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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%v1 = load <2 x i8>, ptr %a
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%v2 = load <2 x i8>, ptr %b
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%concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i8> %concat, i8 %x, i32 1
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store <4 x i8> %ins, ptr %a
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ret void
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}
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define void @v4xi8_concat_vector_insert_idx1(ptr %a, ptr %b, i8 %x) {
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; CHECK-LABEL: v4xi8_concat_vector_insert_idx1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v9, (a1)
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 2
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; CHECK-NEXT: vmv.s.x v9, a2
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; CHECK-NEXT: vsetivli zero, 2, e8, mf4, tu, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 1
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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%v1 = load <2 x i8>, ptr %a
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%v2 = load <2 x i8>, ptr %b
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%concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i8> %concat, i8 %x, i32 1
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store <4 x i8> %ins, ptr %a
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ret void
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}
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define void @v4xi8_concat_vector_insert_idx2(ptr %a, ptr %b, i8 %x) {
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; CHECK-LABEL: v4xi8_concat_vector_insert_idx2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v9, (a1)
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 2
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; CHECK-NEXT: vmv.s.x v9, a2
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; CHECK-NEXT: vsetivli zero, 3, e8, mf4, tu, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 2
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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%v1 = load <2 x i8>, ptr %a
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%v2 = load <2 x i8>, ptr %b
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%concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i8> %concat, i8 %x, i32 2
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store <4 x i8> %ins, ptr %a
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ret void
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}
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define void @v4xi8_concat_vector_insert_idx3(ptr %a, ptr %b, i8 %x) {
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; CHECK-LABEL: v4xi8_concat_vector_insert_idx3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v9, (a1)
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 2
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; CHECK-NEXT: vmv.s.x v9, a2
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; CHECK-NEXT: vslideup.vi v8, v9, 3
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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%v1 = load <2 x i8>, ptr %a
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%v2 = load <2 x i8>, ptr %b
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%concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i8> %concat, i8 %x, i32 3
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store <4 x i8> %ins, ptr %a
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ret void
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}
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define void @v4xi64_concat_vector_insert_idx0(ptr %a, ptr %b, i64 %x) {
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; RV32-LABEL: v4xi64_concat_vector_insert_idx0:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a0)
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; RV32-NEXT: vle64.v v10, (a1)
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v8, a2
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; RV32-NEXT: vslide1down.vx v10, v10, a3
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; RV32-NEXT: vsetivli zero, 2, e64, m1, tu, ma
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; RV32-NEXT: vslideup.vi v8, v10, 1
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vse64.v v8, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4xi64_concat_vector_insert_idx0:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a0)
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; RV64-NEXT: vle64.v v10, (a1)
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vmv.s.x v10, a2
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; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
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; RV64-NEXT: vslideup.vi v8, v10, 1
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vse64.v v8, (a0)
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; RV64-NEXT: ret
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%v1 = load <2 x i64>, ptr %a
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%v2 = load <2 x i64>, ptr %b
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%concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i64> %concat, i64 %x, i32 1
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store <4 x i64> %ins, ptr %a
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ret void
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}
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define void @v4xi64_concat_vector_insert_idx1(ptr %a, ptr %b, i64 %x) {
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; RV32-LABEL: v4xi64_concat_vector_insert_idx1:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a0)
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; RV32-NEXT: vle64.v v10, (a1)
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v8, a2
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; RV32-NEXT: vslide1down.vx v10, v10, a3
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; RV32-NEXT: vsetivli zero, 2, e64, m1, tu, ma
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; RV32-NEXT: vslideup.vi v8, v10, 1
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vse64.v v8, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4xi64_concat_vector_insert_idx1:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a0)
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; RV64-NEXT: vle64.v v10, (a1)
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vmv.s.x v10, a2
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; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
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; RV64-NEXT: vslideup.vi v8, v10, 1
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vse64.v v8, (a0)
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; RV64-NEXT: ret
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%v1 = load <2 x i64>, ptr %a
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%v2 = load <2 x i64>, ptr %b
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%concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i64> %concat, i64 %x, i32 1
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store <4 x i64> %ins, ptr %a
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ret void
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}
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define void @v4xi64_concat_vector_insert_idx2(ptr %a, ptr %b, i64 %x) {
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; RV32-LABEL: v4xi64_concat_vector_insert_idx2:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a0)
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; RV32-NEXT: vle64.v v10, (a1)
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v8, a2
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; RV32-NEXT: vslide1down.vx v10, v10, a3
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; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, ma
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vse64.v v8, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4xi64_concat_vector_insert_idx2:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a0)
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; RV64-NEXT: vle64.v v10, (a1)
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vmv.s.x v10, a2
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; RV64-NEXT: vsetivli zero, 3, e64, m2, tu, ma
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vse64.v v8, (a0)
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; RV64-NEXT: ret
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%v1 = load <2 x i64>, ptr %a
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%v2 = load <2 x i64>, ptr %b
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%concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i64> %concat, i64 %x, i32 2
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store <4 x i64> %ins, ptr %a
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ret void
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}
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define void @v4xi64_concat_vector_insert_idx3(ptr %a, ptr %b, i64 %x) {
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; RV32-LABEL: v4xi64_concat_vector_insert_idx3:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a0)
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; RV32-NEXT: vle64.v v10, (a1)
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v8, a2
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; RV32-NEXT: vslide1down.vx v10, v10, a3
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v8, v10, 3
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; RV32-NEXT: vse64.v v8, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4xi64_concat_vector_insert_idx3:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a0)
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; RV64-NEXT: vle64.v v10, (a1)
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vmv.s.x v10, a2
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; RV64-NEXT: vslideup.vi v8, v10, 3
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; RV64-NEXT: vse64.v v8, (a0)
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; RV64-NEXT: ret
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%v1 = load <2 x i64>, ptr %a
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%v2 = load <2 x i64>, ptr %b
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%concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i64> %concat, i64 %x, i32 3
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store <4 x i64> %ins, ptr %a
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ret void
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}
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@ -566,3 +566,41 @@ define <8 x i32> @add_constant_rhs_8xi32_vector_in3(<8 x i32> %vin, i32 %a, i32
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%v3 = insertelement <8 x i32> %v2, i32 %e3, i32 6
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ret <8 x i32> %v3
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}
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define <8 x i32> @add_constant_rhs_8xi32_partial(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK-LABEL: add_constant_rhs_8xi32_partial:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a4, %hi(.LCPI19_0)
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; CHECK-NEXT: addi a4, a4, %lo(.LCPI19_0)
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v10, (a4)
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; CHECK-NEXT: vadd.vv v8, v8, v10
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; CHECK-NEXT: addi a0, a0, 23
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; CHECK-NEXT: addi a1, a1, 25
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; CHECK-NEXT: addi a2, a2, 1
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; CHECK-NEXT: addi a3, a3, 2047
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; CHECK-NEXT: addi a3, a3, 308
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma
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; CHECK-NEXT: vslideup.vi v8, v10, 4
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; CHECK-NEXT: vmv.s.x v10, a1
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; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma
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; CHECK-NEXT: vslideup.vi v8, v10, 5
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; CHECK-NEXT: vmv.s.x v10, a2
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; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma
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; CHECK-NEXT: vslideup.vi v8, v10, 6
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; CHECK-NEXT: vmv.s.x v10, a3
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v10, 7
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; CHECK-NEXT: ret
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%vadd = add <8 x i32> %vin, <i32 1, i32 2, i32 3, i32 5, i32 undef, i32 undef, i32 undef, i32 undef>
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%e0 = add i32 %a, 23
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%e1 = add i32 %b, 25
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%e2 = add i32 %c, 1
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%e3 = add i32 %d, 2355
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%v0 = insertelement <8 x i32> %vadd, i32 %e0, i32 4
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%v1 = insertelement <8 x i32> %v0, i32 %e1, i32 5
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%v2 = insertelement <8 x i32> %v1, i32 %e2, i32 6
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%v3 = insertelement <8 x i32> %v2, i32 %e3, i32 7
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ret <8 x i32> %v3
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}
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