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[AArch64] Fix a fencepost error in lowering for llvm.aarch64.neon.uqshl.

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Patch by Jiangning Liu!

llvm-svn: 211014
This commit is contained in:
James Molloy 2014-06-16 10:39:21 +00:00
parent ddb7aa6aaa
commit 1e3b5a49e1
2 changed files with 10 additions and 1 deletions
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2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -7007,7 +7007,7 @@ static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
DAG.getConstant(-ShiftAmount, MVT::i32));
else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount <= ElemBits)
else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
DAG.getConstant(ShiftAmount, MVT::i32));

9
llvm/test/CodeGen/AArch64/arm64-vshift.ll
View File

@ -1313,6 +1313,15 @@ define <8 x i8> @uqshli8b(<8 x i8>* %A) nounwind {
ret <8 x i8> %tmp3
}
define <8 x i8> @uqshli8b_1(<8 x i8>* %A) nounwind {
;CHECK-LABEL: uqshli8b_1:
;CHECK: movi.8b [[REG:v[0-9]+]], #0x8
;CHECK: uqshl.8b v0, v0, [[REG]]
%tmp1 = load <8 x i8>* %A
%tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>)
ret <8 x i8> %tmp3
}
define <4 x i16> @uqshli4h(<4 x i16>* %A) nounwind {
;CHECK-LABEL: uqshli4h:
;CHECK: uqshl.4h v0, {{v[0-9]+}}, #1