From 1f25888712cb757854c45e3070178968cdd50371 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 13 Nov 2022 20:00:34 -0800 Subject: [PATCH] [RISCV] Add PACKW and PACKH to isSignExtendingOpW in RISCVSExtWRemoval. PACKW sign extends like other W instructions. PACKH zeroes bits 63:16 which means bits 63:31 are all zero. --- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp index 8a6c728e1734..ebd64945b651 100644 --- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp +++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp @@ -250,6 +250,7 @@ static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI, case RISCV::CLZW: case RISCV::CTZW: case RISCV::CPOPW: + case RISCV::PACKW: case RISCV::FCVT_W_H: case RISCV::FCVT_WU_H: case RISCV::FCVT_W_S: @@ -276,6 +277,7 @@ static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI, case RISCV::CLZ: case RISCV::CPOP: case RISCV::CTZ: + case RISCV::PACKH: return true; // shifting right sufficiently makes the value 32-bit sign-extended case RISCV::SRAI: