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[clang][llvm] Obsolete Exynos M1 and M2

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This commit is contained in:
Evandro Menezes 2019-10-02 16:26:40 -05:00
parent 88d77fce94
commit 215da6606c
36 changed files with 34 additions and 1541 deletions
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2
clang/test/CodeGen/arm-target-features.c
View File

@ -25,8 +25,6 @@
// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a72 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a73 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m1 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m2 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m3 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
// CHECK-BASIC-V8: "target-features"="+armv8-a,+crc,+crypto,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+fpregs,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp"

50
clang/test/Driver/aarch64-cpus.c
View File

@ -152,24 +152,6 @@
// ARM64-CORTEX-A76: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "cortex-a76"
// ARM64-CORTEX-A76-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target aarch64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1 %s
// RUN: %clang -target aarch64 -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1 %s
// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1 %s
// RUN: %clang -target aarch64 -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-TUNE %s
// RUN: %clang -target aarch64 -mlittle-endian -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-TUNE %s
// RUN: %clang -target aarch64_be -mlittle-endian -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-TUNE %s
// M1: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "exynos-m1"
// M1-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "generic"
// RUN: %clang -target aarch64 -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2 %s
// RUN: %clang -target aarch64 -mlittle-endian -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2 %s
// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2 %s
// RUN: %clang -target aarch64 -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-TUNE %s
// RUN: %clang -target aarch64 -mlittle-endian -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-TUNE %s
// RUN: %clang -target aarch64_be -mlittle-endian -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-TUNE %s
// M2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "exynos-m2"
// M2-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target aarch64_be -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3 %s
// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3 %s
// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3 %s
@ -199,20 +181,6 @@
// M5-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
// M5-TUNE-NOT: "+v8.2a"
// RUN: %clang -target arm64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M1 %s
// RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M1 %s
// RUN: %clang -target arm64 -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M1-TUNE %s
// RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M1-TUNE %s
// ARM64-M1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m1"
// ARM64-M1-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target arm64 -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M2 %s
// RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M2 %s
// RUN: %clang -target arm64 -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M2-TUNE %s
// RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M2-TUNE %s
// ARM64-M2: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m2"
// ARM64-M2-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target arm64 -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M3 %s
// RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M3 %s
// RUN: %clang -target arm64 -mtune=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-M3-TUNE %s
@ -341,24 +309,6 @@
// CORTEX-A73-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "cortex-a73"
// CORTEX-A73-BE-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target aarch64_be -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-BE %s
// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-BE %s
// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-BE %s
// RUN: %clang -target aarch64_be -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-BE-TUNE %s
// RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-BE-TUNE %s
// RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1-BE-TUNE %s
// M1-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m1"
// M1-BE-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target aarch64_be -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-BE %s
// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-BE %s
// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-BE %s
// RUN: %clang -target aarch64_be -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-BE-TUNE %s
// RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-BE-TUNE %s
// RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=M2-BE-TUNE %s
// M2-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m2"
// M2-BE-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target aarch64_be -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3-BE %s
// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3-BE %s
// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3-BE %s

16
clang/test/Driver/arm-cortex-cpus.c
View File

@ -658,11 +658,7 @@
// RUN: %clang -target arm -mcpu=cortex-a72 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
// RUN: %clang -target arm -mcpu=cortex-a73 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
//
// RUN: %clang -target arm -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
// RUN: %clang -target arm -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
// RUN: %clang -target arm -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
// RUN: %clang -target arm -mcpu=exynos-m1 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
// RUN: %clang -target arm -mcpu=exynos-m2 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
// RUN: %clang -target arm -mcpu=exynos-m3 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
// CHECK-CPUV8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}
@ -694,11 +690,7 @@
// RUN: %clang -target arm -mcpu=cortex-a72 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// RUN: %clang -target arm -mcpu=cortex-a73 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
//
// RUN: %clang -target armeb -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// RUN: %clang -target armeb -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// RUN: %clang -target armeb -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// RUN: %clang -target arm -mcpu=exynos-m1 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// RUN: %clang -target arm -mcpu=exynos-m2 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// RUN: %clang -target arm -mcpu=exynos-m3 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// CHECK-BE-CPUV8A: "-cc1"{{.*}} "-triple" "armebv8-{{.*}}
@ -733,11 +725,7 @@
// RUN: %clang -target arm -mcpu=cortex-a72 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=cortex-a73 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
//
// RUN: %clang -target arm -mcpu=exynos-m1 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=exynos-m2 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=exynos-m3 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=exynos-m1 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=exynos-m2 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=exynos-m3 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// CHECK-CPUV8A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8-{{.*}}
@ -769,11 +757,7 @@
// RUN: %clang -target arm -mcpu=cortex-a72 -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=cortex-a73 -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A-THUMB %s
//
// RUN: %clang -target armeb -mcpu=exynos-m1 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A-THUMB %s
// RUN: %clang -target armeb -mcpu=exynos-m2 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A-THUMB %s
// RUN: %clang -target armeb -mcpu=exynos-m3 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=exynos-m1 -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=exynos-m2 -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=exynos-m3 -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A-THUMB %s
// CHECK-BE-CPUV8A-THUMB: "-cc1"{{.*}} "-triple" "thumbebv8-{{.*}}

2
clang/test/Frontend/aarch64-target-cpu.c
View File

@ -6,7 +6,7 @@
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cortex-a72 -verify %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cortex-a73 -verify %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cyclone -verify %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu exynos-m1 -verify %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu exynos-m3 -verify %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu generic -verify %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu kryo -verify %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu thunderx2t99 -verify %s

2
clang/test/Preprocessor/aarch64-target-features.c
View File

@ -148,8 +148,6 @@
// RUN: %clang -target aarch64 -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A57 %s
// RUN: %clang -target aarch64 -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A72 %s
// RUN: %clang -target aarch64 -mcpu=cortex-a73 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CORTEX-A73 %s
// RUN: %clang -target aarch64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M1 %s
// RUN: %clang -target aarch64 -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M1 %s
// RUN: %clang -target aarch64 -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M1 %s
// RUN: %clang -target aarch64 -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M4 %s
// RUN: %clang -target aarch64 -mcpu=exynos-m5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M4 %s

8
clang/test/Preprocessor/arm-target-features.c
View File

@ -528,10 +528,6 @@
// RUN: %clang -target armv8 -mcpu=cortex-a73 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a73 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
//
// RUN: %clang -target armv8 -mcpu=exynos-m1 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
// RUN: %clang -target armv8 -mthumb -mcpu=exynos-m1 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
// RUN: %clang -target armv8 -mcpu=exynos-m2 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
// RUN: %clang -target armv8 -mthumb -mcpu=exynos-m2 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
// RUN: %clang -target armv8 -mcpu=exynos-m3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
// RUN: %clang -target armv8 -mthumb -mcpu=exynos-m3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
// RUN: %clang -target armv8 -mcpu=exynos-m4 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8 %s
@ -556,10 +552,6 @@
// RUN: %clang -target armv8-eabi -mcpu=cortex-a73 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s
// RUN: %clang -target armv8-eabi -mthumb -mcpu=cortex-a73 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s
//
// RUN: %clang -target armv8-eabi -mcpu=exynos-m1 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s
// RUN: %clang -target armv8-eabi -mthumb -mcpu=exynos-m1 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s
// RUN: %clang -target armv8-eabi -mcpu=exynos-m2 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s
// RUN: %clang -target armv8-eabi -mthumb -mcpu=exynos-m2 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s
// RUN: %clang -target armv8-eabi -mcpu=exynos-m3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s
// RUN: %clang -target armv8-eabi -mthumb -mcpu=exynos-m3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s
// RUN: %clang -target armv8-eabi -mcpu=exynos-m4 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=ARMV8-ALLOW-FP-INSTR %s

6
llvm/docs/WritingAnLLVMBackend.rst
View File

@ -1023,9 +1023,9 @@ output file:
.. code-block:: shell
$ <src>/utils/schedcover.py <build>/lib/Target/AArch64/tblGenSubtarget.with
instruction, default, CortexA53Model, CortexA57Model, CycloneModel, ExynosM1Model, FalkorModel, KryoModel, ThunderX2T99Model, ThunderXT8XModel
ABSv16i8, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_2VXVY_2cyc, KryoWrite_2cyc_XY_XY_150ln, ,
ABSv1i64, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_1VXVY_2cyc, KryoWrite_2cyc_XY_noRSV_67ln, ,
instruction, default, CortexA53Model, CortexA57Model, CycloneModel, ExynosM3Model, FalkorModel, KryoModel, ThunderX2T99Model, ThunderXT8XModel
ABSv16i8, WriteV, , , CyWriteV3, M3WriteNMISC1, FalkorWr_2VXVY_2cyc, KryoWrite_2cyc_XY_XY_150ln, ,
ABSv1i64, WriteV, , , CyWriteV3, M3WriteNMISC1, FalkorWr_1VXVY_2cyc, KryoWrite_2cyc_XY_noRSV_67ln, ,
...
To capture the debug output from generating a schedule model, change to the

4
llvm/include/llvm/Support/AArch64TargetParser.def
View File

@ -120,10 +120,6 @@ AARCH64_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
AArch64::AEK_SSBS))
AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_NONE))
AARCH64_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))
AARCH64_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))
AARCH64_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))
AARCH64_CPU_NAME("exynos-m4", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,

2
llvm/include/llvm/Support/ARMTargetParser.def
View File

@ -277,8 +277,6 @@ ARM_CPU_NAME("cortex-a76ae", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m4", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))

12
llvm/lib/Support/Host.cpp
View File

@ -265,14 +265,12 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
unsigned Exynos = (Variant << 12) | Part;
switch (Exynos) {
default:
// Default by falling through to Exynos M1.
// Default by falling through to Exynos M3.
LLVM_FALLTHROUGH;
case 0x1001:
return "exynos-m1";
case 0x4001:
return "exynos-m2";
case 0x1002:
return "exynos-m3";
case 0x1003:
return "exynos-m4";
}
}

30
llvm/lib/Target/AArch64/AArch64.td
View File

@ -448,7 +448,6 @@ include "AArch64SchedA57.td"
include "AArch64SchedCyclone.td"
include "AArch64SchedFalkor.td"
include "AArch64SchedKryo.td"
include "AArch64SchedExynosM1.td"
include "AArch64SchedExynosM3.td"
include "AArch64SchedExynosM4.td"
include "AArch64SchedThunderX.td"
@ -582,33 +581,6 @@ def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
FeatureZCZeroingFPWorkaround
]>;
def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
"Samsung Exynos-M1 processors",
[FeatureSlowPaired128,
FeatureCRC,
FeatureCrypto,
FeatureExynosCheapAsMoveHandling,
FeatureForce32BitJumpTables,
FeatureFuseAES,
FeaturePerfMon,
FeaturePostRAScheduler,
FeatureSlowMisaligned128Store,
FeatureUseRSqrt,
FeatureZCZeroingFP]>;
def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
"Samsung Exynos-M2 processors",
[FeatureSlowPaired128,
FeatureCRC,
FeatureCrypto,
FeatureExynosCheapAsMoveHandling,
FeatureForce32BitJumpTables,
FeatureFuseAES,
FeaturePerfMon,
FeaturePostRAScheduler,
FeatureSlowMisaligned128Store,
FeatureZCZeroingFP]>;
def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
"Samsung Exynos-M3 processors",
[FeatureCRC,
@ -816,8 +788,6 @@ def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
def : ProcessorModel<"exynos-m5", ExynosM4Model, [ProcExynosM4]>;

850
llvm/lib/Target/AArch64/AArch64SchedExynosM1.td
View File

@ -1,850 +0,0 @@
//=- AArch64SchedExynosM1.td - Samsung Exynos M1 Sched Defs --*- tablegen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines the machine model for the Samsung Exynos M1 to support
// instruction scheduling and other instruction cost heuristics.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// The Exynos-M1 is a traditional superscalar microprocessor with a
// 4-wide in-order stage for decode and dispatch and a wider issue stage.
// The execution units and loads and stores are out-of-order.
def ExynosM1Model : SchedMachineModel {
let IssueWidth = 4; // Up to 4 uops per cycle.
let MicroOpBufferSize = 96; // ROB size.
let LoopMicroOpBufferSize = 24; // Based on the instruction queue size.
let LoadLatency = 4; // Optimistic load cases.
let MispredictPenalty = 14; // Minimum branch misprediction penalty.
let CompleteModel = 1; // Use the default model otherwise.
list<Predicate> UnsupportedFeatures = SVEUnsupported.F;
}
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on the Exynos-M1,
// which has 9 pipelines, each with its own queue with out-of-order dispatch.
let SchedModel = ExynosM1Model in {
def M1UnitA : ProcResource<2>; // Simple integer
def M1UnitC : ProcResource<1>; // Simple and complex integer
def M1UnitD : ProcResource<1>; // Integer division (inside C, serialized)
def M1UnitB : ProcResource<2>; // Branch
def M1UnitL : ProcResource<1>; // Load
def M1UnitS : ProcResource<1>; // Store
def M1PipeF0 : ProcResource<1>; // FP #0
let Super = M1PipeF0 in {
def M1UnitFMAC : ProcResource<1>; // FP multiplication
def M1UnitNAL0 : ProcResource<1>; // Simple vector
def M1UnitNMISC : ProcResource<1>; // Miscellanea
def M1UnitFCVT : ProcResource<1>; // FP conversion
def M1UnitNCRYPT : ProcResource<1>; // Cryptographic
}
def M1PipeF1 : ProcResource<1>; // FP #1
let Super = M1PipeF1 in {
def M1UnitFADD : ProcResource<1>; // Simple FP
def M1UnitNAL1 : ProcResource<1>; // Simple vector
def M1UnitFVAR : ProcResource<1>; // FP division & square root (serialized)
def M1UnitFST : ProcResource<1>; // FP store
}
def M1UnitALU : ProcResGroup<[M1UnitA,
M1UnitC]>; // All integer
def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
M1UnitNAL1]>; // All simple vector
//===----------------------------------------------------------------------===//
// Coarse scheduling model.
def M1WriteA1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
def M1WriteA2 : SchedWriteRes<[M1UnitALU]> { let Latency = 2; }
def M1WriteAA : SchedWriteRes<[M1UnitALU]> { let Latency = 2;
let ResourceCycles = [2]; }
def M1WriteAB : SchedWriteRes<[M1UnitALU,
M1UnitC]> { let Latency = 1;
let NumMicroOps = 2; }
def M1WriteAC : SchedWriteRes<[M1UnitALU,
M1UnitALU,
M1UnitC]> { let Latency = 2;
let NumMicroOps = 3; }
def M1WriteAD : SchedWriteRes<[M1UnitALU,
M1UnitC]> { let Latency = 2;
let NumMicroOps = 2; }
def M1WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M1WriteA1]>,
SchedVar<ExynosLogicPred, [M1WriteA1]>,
SchedVar<NoSchedPred, [M1WriteAA]>]>;
def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; }
def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; }
def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
def M1WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M1WriteAC]>,
SchedVar<NoSchedPred, [M1WriteAB]>]>;
def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
def M1WriteL6 : SchedWriteRes<[M1UnitL]> { let Latency = 6; }
def M1WriteLA : SchedWriteRes<[M1UnitL]> { let Latency = 6;
let ResourceCycles = [2]; }
def M1WriteLB : SchedWriteRes<[M1UnitL,
M1UnitA]> { let Latency = 4;
let NumMicroOps = 2; }
def M1WriteLC : SchedWriteRes<[M1UnitL,
M1UnitA]> { let Latency = 5;
let NumMicroOps = 2; }
def M1WriteLD : SchedWriteRes<[M1UnitL,
M1UnitA]> { let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [2, 1]; }
def M1WriteLH : SchedWriteRes<[]> { let Latency = 5;
let NumMicroOps = 0; }
def M1WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteLC]>,
SchedVar<NoSchedPred, [M1WriteL5]>]>;
def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
def M1WriteS3 : SchedWriteRes<[M1UnitS]> { let Latency = 3; }
def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
def M1WriteSA : SchedWriteRes<[M1UnitS,
M1UnitFST,
M1UnitA]> { let Latency = 3;
let NumMicroOps = 2; }
def M1WriteSB : SchedWriteRes<[M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitA]> { let Latency = 3;
let NumMicroOps = 3; }
def M1WriteSC : SchedWriteRes<[M1UnitS,
M1UnitA]> { let Latency = 2;
let NumMicroOps = 2; }
def M1WriteSX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteSC]>,
SchedVar<NoSchedPred, [M1WriteS1]>]>;
def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
// Branch instructions.
def : WriteRes<WriteBr, []> { let Latency = 0; }
def : WriteRes<WriteBrReg, [M1UnitC]> { let Latency = 1; }
// Arithmetic and logical integer instructions.
def : WriteRes<WriteI, [M1UnitALU]> { let Latency = 1; }
def : WriteRes<WriteISReg, [M1UnitALU]> { let Latency = 1; }
def : WriteRes<WriteIEReg, [M1UnitALU]> { let Latency = 1; }
def : WriteRes<WriteIS, [M1UnitALU]> { let Latency = 1; }
// Move instructions.
def : WriteRes<WriteImm, [M1UnitALU]> { let Latency = 1; }
// Divide and multiply instructions.
def : WriteRes<WriteID32, [M1UnitC,
M1UnitD]> { let Latency = 13;
let ResourceCycles = [1, 13]; }
def : WriteRes<WriteID64, [M1UnitC,
M1UnitD]> { let Latency = 21;
let ResourceCycles = [1, 21]; }
// TODO: Long multiplication take 5 cycles and also the ALU.
def : WriteRes<WriteIM32, [M1UnitC]> { let Latency = 3; }
def : WriteRes<WriteIM64, [M1UnitC]> { let Latency = 4;
let ResourceCycles = [2]; }
// Miscellaneous instructions.
def : WriteRes<WriteExtr, [M1UnitALU,
M1UnitALU]> { let Latency = 2;
let NumMicroOps = 2; }
// Addressing modes.
def : WriteRes<WriteAdr, []> { let Latency = 1;
let NumMicroOps = 0; }
def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
// Load instructions.
def : WriteRes<WriteLD, [M1UnitL]> { let Latency = 4; }
def : WriteRes<WriteLDHi, []> { let Latency = 4;
let NumMicroOps = 0; }
def : SchedAlias<WriteLDIdx, M1WriteLX>;
// Store instructions.
def : WriteRes<WriteST, [M1UnitS]> { let Latency = 1; }
def : WriteRes<WriteSTP, [M1UnitS]> { let Latency = 1; }
def : WriteRes<WriteSTX, [M1UnitS]> { let Latency = 1; }
def : SchedAlias<WriteSTIdx, M1WriteSX>;
// FP data instructions.
def : WriteRes<WriteF, [M1UnitFADD]> { let Latency = 3; }
def : WriteRes<WriteFCmp, [M1UnitNMISC]> { let Latency = 4; }
def : WriteRes<WriteFDiv, [M1UnitFVAR]> { let Latency = 15;
let ResourceCycles = [15]; }
def : WriteRes<WriteFMul, [M1UnitFMAC]> { let Latency = 4; }
// FP miscellaneous instructions.
def : WriteRes<WriteFCvt, [M1UnitFCVT]> { let Latency = 3; }
def : WriteRes<WriteFImm, [M1UnitNALU]> { let Latency = 1; }
def : WriteRes<WriteFCopy, [M1UnitS]> { let Latency = 4; }
// FP load instructions.
def : WriteRes<WriteVLD, [M1UnitL]> { let Latency = 5; }
// FP store instructions.
def : WriteRes<WriteVST, [M1UnitS,
M1UnitFST]> { let Latency = 1;
let NumMicroOps = 1; }
// ASIMD FP instructions.
def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
// Other miscellaneous instructions.
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
def : WriteRes<WriteBarrier, []> { let Latency = 1; }
def : WriteRes<WriteHint, []> { let Latency = 1; }
def : WriteRes<WriteSys, []> { let Latency = 1; }
//===----------------------------------------------------------------------===//
// Fast forwarding.
// TODO: Add FP register forwarding rules.
def : ReadAdvance<ReadI, 0>;
def : ReadAdvance<ReadISReg, 0>;
def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>;
// TODO: The forwarding for WriteIM32 saves actually 2 cycles.
def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>;
//===----------------------------------------------------------------------===//
// Finer scheduling model.
def M1WriteNEONA : SchedWriteRes<[M1UnitNALU,
M1UnitNALU,
M1UnitFADD]> { let Latency = 9;
let NumMicroOps = 3; }
def M1WriteNEONB : SchedWriteRes<[M1UnitNALU,
M1UnitFST]> { let Latency = 5;
let NumMicroOps = 2;}
def M1WriteNEONC : SchedWriteRes<[M1UnitNALU,
M1UnitFST]> { let Latency = 6;
let NumMicroOps = 2; }
def M1WriteNEOND : SchedWriteRes<[M1UnitNALU,
M1UnitFST,
M1UnitL]> { let Latency = 10;
let NumMicroOps = 3; }
def M1WriteNEONE : SchedWriteRes<[M1UnitFCVT,
M1UnitFST]> { let Latency = 8;
let NumMicroOps = 2; }
def M1WriteNEONF : SchedWriteRes<[M1UnitFCVT,
M1UnitFST,
M1UnitL]> { let Latency = 13;
let NumMicroOps = 3; }
def M1WriteNEONG : SchedWriteRes<[M1UnitNMISC,
M1UnitFST]> { let Latency = 6;
let NumMicroOps = 2; }
def M1WriteNEONH : SchedWriteRes<[M1UnitNALU,
M1UnitFST]> { let Latency = 3;
let NumMicroOps = 2; }
def M1WriteNEONI : SchedWriteRes<[M1UnitFST,
M1UnitL]> { let Latency = 9;
let NumMicroOps = 2; }
def M1WriteNEONJ : SchedWriteRes<[M1UnitNMISC,
M1UnitFMAC]> { let Latency = 6;
let NumMicroOps = 2; }
def M1WriteNEONK : SchedWriteRes<[M1UnitNMISC,
M1UnitFMAC]> { let Latency = 7;
let NumMicroOps = 2; }
def M1WriteNEONL : SchedWriteRes<[M1UnitNALU]> { let Latency = 2;
let ResourceCycles = [2]; }
def M1WriteFADD3 : SchedWriteRes<[M1UnitFADD]> { let Latency = 3; }
def M1WriteFCVT3 : SchedWriteRes<[M1UnitFCVT]> { let Latency = 3; }
def M1WriteFCVT4 : SchedWriteRes<[M1UnitFCVT]> { let Latency = 4; }
def M1WriteFMAC4 : SchedWriteRes<[M1UnitFMAC]> { let Latency = 4; }
def M1WriteFMAC5 : SchedWriteRes<[M1UnitFMAC]> { let Latency = 5; }
// TODO
def M1WriteFVAR15 : SchedWriteRes<[M1UnitFVAR]> { let Latency = 15;
let ResourceCycles = [15]; }
def M1WriteFVAR23 : SchedWriteRes<[M1UnitFVAR]> { let Latency = 23;
let ResourceCycles = [23]; }
def M1WriteNALU1 : SchedWriteRes<[M1UnitNALU]> { let Latency = 1; }
def M1WriteNALU2 : SchedWriteRes<[M1UnitNALU]> { let Latency = 2; }
def M1WriteNAL11 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 1; }
def M1WriteNAL12 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 2; }
def M1WriteNAL13 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 3; }
def M1WriteNCRYPT1 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
def M1WriteNCRYPT5 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 5; }
def M1WriteNMISC1 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 1; }
def M1WriteNMISC2 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 2; }
def M1WriteNMISC3 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 3; }
def M1WriteNMISC4 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 4; }
def M1WriteTB : SchedWriteRes<[M1UnitC,
M1UnitALU]> { let Latency = 2;
let NumMicroOps = 2; }
def M1WriteVLDA : SchedWriteRes<[M1UnitL,
M1UnitL]> { let Latency = 6;
let NumMicroOps = 2; }
def M1WriteVLDB : SchedWriteRes<[M1UnitL,
M1UnitL,
M1UnitL]> { let Latency = 7;
let NumMicroOps = 3; }
def M1WriteVLDC : SchedWriteRes<[M1UnitL,
M1UnitL,
M1UnitL,
M1UnitL]> { let Latency = 8;
let NumMicroOps = 4; }
def M1WriteVLDD : SchedWriteRes<[M1UnitL,
M1UnitNALU]> { let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [2, 1]; }
def M1WriteVLDE : SchedWriteRes<[M1UnitL,
M1UnitNALU]> { let Latency = 6;
let NumMicroOps = 2; }
def M1WriteVLDF : SchedWriteRes<[M1UnitL,
M1UnitL]> { let Latency = 10;
let NumMicroOps = 2;
let ResourceCycles = [1, 1]; }
def M1WriteVLDG : SchedWriteRes<[M1UnitL,
M1UnitNALU,
M1UnitNALU]> { let Latency = 7;
let NumMicroOps = 3;
let ResourceCycles = [2, 1, 1]; }
def M1WriteVLDH : SchedWriteRes<[M1UnitL,
M1UnitNALU,
M1UnitNALU]> { let Latency = 6;
let NumMicroOps = 3; }
def M1WriteVLDI : SchedWriteRes<[M1UnitL,
M1UnitL,
M1UnitL]> { let Latency = 12;
let NumMicroOps = 3;
let ResourceCycles = [2, 2, 2]; }
def M1WriteVLDJ : SchedWriteRes<[M1UnitL,
M1UnitNALU,
M1UnitNALU,
M1UnitNALU]> { let Latency = 9;
let NumMicroOps = 4;
let ResourceCycles = [2, 1, 1, 1]; }
def M1WriteVLDK : SchedWriteRes<[M1UnitL,
M1UnitNALU,
M1UnitNALU,
M1UnitNALU,
M1UnitNALU]> { let Latency = 9;
let NumMicroOps = 5;
let ResourceCycles = [2, 1, 1, 1, 1]; }
def M1WriteVLDL : SchedWriteRes<[M1UnitL,
M1UnitNALU,
M1UnitNALU,
M1UnitL,
M1UnitNALU]> { let Latency = 7;
let NumMicroOps = 5;
let ResourceCycles = [1, 1, 1, 1, 1]; }
def M1WriteVLDM : SchedWriteRes<[M1UnitL,
M1UnitNALU,
M1UnitNALU,
M1UnitL,
M1UnitNALU,
M1UnitNALU]> { let Latency = 7;
let NumMicroOps = 6;
let ResourceCycles = [1, 1, 1, 1, 1, 1]; }
def M1WriteVLDN : SchedWriteRes<[M1UnitL,
M1UnitL,
M1UnitL,
M1UnitL]> { let Latency = 14;
let NumMicroOps = 4;
let ResourceCycles = [2, 1, 2, 1]; }
def M1WriteVSTA : WriteSequence<[WriteVST], 2>;
def M1WriteVSTB : WriteSequence<[WriteVST], 3>;
def M1WriteVSTC : WriteSequence<[WriteVST], 4>;
def M1WriteVSTD : SchedWriteRes<[M1UnitS,
M1UnitFST,
M1UnitFST]> { let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [7, 1, 1]; }
def M1WriteVSTE : SchedWriteRes<[M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitFST]> { let Latency = 8;
let NumMicroOps = 3;
let ResourceCycles = [7, 1, 1, 1, 1]; }
def M1WriteVSTF : SchedWriteRes<[M1UnitNALU,
M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitFST,
M1UnitFST]> { let Latency = 15;
let NumMicroOps = 5;
let ResourceCycles = [1, 7, 1, 7, 1, 1, 1]; }
def M1WriteVSTG : SchedWriteRes<[M1UnitNALU,
M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitFST,
M1UnitFST]> { let Latency = 16;
let NumMicroOps = 6;
let ResourceCycles = [1, 7, 1, 7, 1, 1, 1, 1, 1]; }
def M1WriteVSTH : SchedWriteRes<[M1UnitNALU,
M1UnitS,
M1UnitFST,
M1UnitFST,
M1UnitFST]> { let Latency = 14;
let NumMicroOps = 4;
let ResourceCycles = [1, 7, 1, 7, 1]; }
def M1WriteVSTI : SchedWriteRes<[M1UnitNALU,
M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitFST,
M1UnitFST]> { let Latency = 17;
let NumMicroOps = 7;
let ResourceCycles = [1, 7, 1, 7, 1, 1, 1, 1, 1, 1, 1]; }
// Special cases.
def M1WriteAES : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
def M1WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M1WriteNALU1]>,
SchedVar<NoSchedPred, [M1WriteA1]>]>;
// Fast forwarding.
def M1ReadAES : SchedReadAdvance<1, [M1WriteAES]>;
// Branch instructions
def : InstRW<[M1WriteB1], (instrs Bcc)>;
def : InstRW<[M1WriteA1], (instrs BL)>;
def : InstRW<[M1WriteBX], (instrs BLR)>;
def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>;
def : InstRW<[M1WriteAD], (instregex "^TBN?Z[WX]")>;
// Arithmetic and logical integer instructions.
def : InstRW<[M1WriteAX], (instregex ".+rx(64)?$")>;
def : InstRW<[M1WriteAX], (instregex ".+rs$")>;
// Move instructions.
def : InstRW<[M1WriteCOPY], (instrs COPY)>;
// Divide and multiply instructions.
// Miscellaneous instructions.
// Load instructions.
def : InstRW<[M1WriteLB,
WriteLDHi,
WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
def : InstRW<[M1WriteLC,
ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
def : InstRW<[M1WriteL5,
ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
def : InstRW<[M1WriteLC,
ReadAdrBase], (instrs PRFMroW)>;
def : InstRW<[M1WriteL5,
ReadAdrBase], (instrs PRFMroX)>;
// Store instructions.
def : InstRW<[M1WriteSC,
ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
def : InstRW<[WriteST,
ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
// FP data instructions.
def : InstRW<[M1WriteNALU1], (instregex "^F(ABS|NEG)[DS]r")>;
def : InstRW<[M1WriteFADD3], (instregex "^F(ADD|SUB)[DS]rr")>;
def : InstRW<[M1WriteNEONG], (instregex "^FCCMPE?[DS]rr")>;
def : InstRW<[M1WriteNMISC4], (instregex "^FCMPE?[DS]r")>;
def : InstRW<[M1WriteFVAR15], (instrs FDIVSrr)>;
def : InstRW<[M1WriteFVAR23], (instrs FDIVDrr)>;
def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN).+rr")>;
def : InstRW<[M1WriteFMAC4], (instregex "^FN?MUL[DS]rr")>;
def : InstRW<[M1WriteFMAC5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
def : InstRW<[M1WriteFCVT3], (instregex "^FRINT.+r")>;
def : InstRW<[M1WriteNEONH], (instregex "^FCSEL[DS]rrr")>;
def : InstRW<[M1WriteFVAR15], (instrs FSQRTSr)>;
def : InstRW<[M1WriteFVAR23], (instrs FSQRTDr)>;
// FP miscellaneous instructions.
def : InstRW<[M1WriteFCVT3], (instregex "^FCVT[DS][DS]r")>;
def : InstRW<[M1WriteNEONF], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
def : InstRW<[M1WriteNEONE], (instregex "^[SU]CVTF[SU]")>;
def : InstRW<[M1WriteNALU1], (instregex "^FMOV[DS][ir]")>;
def : InstRW<[M1WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>;
def : InstRW<[M1WriteNMISC1], (instregex "^FRECPXv1")>;
def : InstRW<[M1WriteFMAC5], (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
def : InstRW<[M1WriteS4], (instregex "^FMOV[WX][DS](High)?r")>;
def : InstRW<[M1WriteNEONI], (instregex "^FMOV[DS][WX](High)?r")>;
// FP load instructions.
def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>;
def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>;
def : InstRW<[WriteVLD,
WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>;
def : InstRW<[M1WriteLD,
ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
def : InstRW<[WriteVLD,
ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
def : InstRW<[M1WriteLD,
ReadAdrBase], (instregex "^LDRQro[WX]")>;
def : InstRW<[WriteVLD,
M1WriteLH], (instregex "^LDN?P[DS]i")>;
def : InstRW<[M1WriteLA,
M1WriteLH], (instregex "^LDN?PQi")>;
def : InstRW<[M1WriteLC,
M1WriteLH,
WriteAdr], (instregex "^LDP[DS](post|pre)")>;
def : InstRW<[M1WriteLD,
M1WriteLH,
WriteAdr], (instregex "^LDPQ(post|pre)")>;
// FP store instructions.
def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>;
def : InstRW<[WriteVST,
WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>;
def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>;
def : InstRW<[M1WriteSA,
ReadAdrBase], (instregex "^STR[BDHS]roW")>;
def : InstRW<[WriteVST,
ReadAdrBase], (instregex "^STR[BDHS]roX")>;
def : InstRW<[M1WriteSA,
ReadAdrBase], (instregex "^STRQro[WX]")>;
def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>;
def : InstRW<[WriteVST,
WriteAdr], (instregex "^STP[DS](post|pre)")>;
def : InstRW<[M1WriteSB,
WriteAdr], (instregex "^STPQ(post|pre)")>;
// ASIMD instructions.
def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
def : InstRW<[M1WriteNMISC1], (instregex "^[SU]ABDL?v")>;
def : InstRW<[M1WriteNMISC1], (instregex "^(SQ)?ABSv")>;
def : InstRW<[M1WriteNMISC1], (instregex "^SQNEGv")>;
def : InstRW<[M1WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>;
def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?H(ADD|SUB)v")>;
def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?AD[AD](L|LP|P|W)V?2?v")>;
def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?SUB[LW]2?v")>;
def : InstRW<[M1WriteNMISC3], (instregex "^R?(ADD|SUB)HN?2?v")>;
def : InstRW<[M1WriteNMISC3], (instregex "^[SU]+Q(ADD|SUB)v")>;
def : InstRW<[M1WriteNMISC3], (instregex "^[SU]RHADDv")>;
def : InstRW<[M1WriteNMISC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
def : InstRW<[M1WriteNALU1], (instregex "^CMTSTv")>;
def : InstRW<[M1WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
def : InstRW<[M1WriteNMISC1], (instregex "^[SU](MIN|MAX)v")>;
def : InstRW<[M1WriteNMISC2], (instregex "^[SU](MIN|MAX)Pv")>;
def : InstRW<[M1WriteNMISC3], (instregex "^[SU](MIN|MAX)Vv")>;
def : InstRW<[M1WriteNMISC4], (instregex "^(MUL|SQR?DMULH)v")>;
def : InstRW<[M1WriteNMISC4], (instregex "^ML[AS]v")>;
def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD|SQRD)ML[AS][HL]v")>;
def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD)MULLv")>;
def : InstRW<[M1WriteNAL13], (instregex "^(S|SR|U|UR)SRAv")>;
def : InstRW<[M1WriteNALU1], (instregex "^SHL[dv]")>;
def : InstRW<[M1WriteNALU1], (instregex "^[SU]SH[LR][dv]")>;
def : InstRW<[M1WriteNALU1], (instregex "^S[RS]I[dv]")>;
def : InstRW<[M1WriteNAL13], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
def : InstRW<[M1WriteNAL13], (instregex "^[SU]RSH[LR][dv]")>;
def : InstRW<[M1WriteNAL13], (instregex "^[SU]QR?SHLU?[bdhsv]")>;
// ASIMD FP instructions.
def : InstRW<[M1WriteNALU1], (instregex "^F(ABS|NEG)v")>;
def : InstRW<[M1WriteNMISC3], (instregex "^F(ABD|ADD|SUB)v")>;
def : InstRW<[M1WriteNEONA], (instregex "^FADDP")>;
def : InstRW<[M1WriteNMISC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
def : InstRW<[M1WriteFCVT3], (instregex "^[FVSU]CVTX?[AFLMNPZ][SU]?(_Int)?v")>;
def : InstRW<[M1WriteFVAR15], (instregex "FDIVv.f32")>;
def : InstRW<[M1WriteFVAR23], (instregex "FDIVv2f64")>;
def : InstRW<[M1WriteFVAR15], (instregex "FSQRTv.f32")>;
def : InstRW<[M1WriteFVAR23], (instregex "FSQRTv2f64")>;
def : InstRW<[M1WriteNMISC1], (instregex "^F(MAX|MIN)(NM)?V?v")>;
def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN)(NM)?Pv")>;
def : InstRW<[M1WriteNEONJ], (instregex "^FMULX?v.i")>;
def : InstRW<[M1WriteFMAC4], (instregex "^FMULX?v.f")>;
def : InstRW<[M1WriteNEONK], (instregex "^FML[AS]v.i")>;
def : InstRW<[M1WriteFMAC5], (instregex "^FML[AS]v.f")>;
def : InstRW<[M1WriteFCVT3], (instregex "^FRINT[AIMNPXZ]v")>;
// ASIMD miscellaneous instructions.
def : InstRW<[M1WriteNALU1], (instregex "^RBITv")>;
def : InstRW<[M1WriteNAL11], (instregex "^(BIF|BIT|BSL)v")>;
def : InstRW<[M1WriteNEONB], (instregex "^DUPv.+gpr")>;
def : InstRW<[M1WriteNALU1], (instregex "^DUPv.+lane")>;
def : InstRW<[M1WriteNALU1], (instregex "^EXTv8")>;
def : InstRW<[M1WriteNEONL], (instregex "^EXTv16")>;
def : InstRW<[M1WriteNAL13], (instregex "^[SU]?Q?XTU?Nv")>;
def : InstRW<[M1WriteNALU1], (instregex "^CPY")>;
def : InstRW<[M1WriteNALU1], (instregex "^INSv.+lane")>;
def : InstRW<[M1WriteNALU1], (instregex "^MOVI[Dv]")>;
def : InstRW<[M1WriteNALU1], (instregex "^FMOVv")>;
def : InstRW<[M1WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
def : InstRW<[M1WriteFMAC5], (instregex "^F(RECP|RSQRT)Sv")>;
def : InstRW<[M1WriteNALU1], (instregex "^REV(16|32|64)v")>;
def : InstRW<[M1WriteNAL11], (instregex "^TB[LX]v8i8One")>;
def : InstRW<[WriteSequence<[M1WriteNAL11], 2>],
(instregex "^TB[LX]v8i8Two")>;
def : InstRW<[WriteSequence<[M1WriteNAL11], 3>],
(instregex "^TB[LX]v8i8Three")>;
def : InstRW<[WriteSequence<[M1WriteNAL11], 4>],
(instregex "^TB[LX]v8i8Four")>;
def : InstRW<[M1WriteNAL12], (instregex "^TB[LX]v16i8One")>;
def : InstRW<[WriteSequence<[M1WriteNAL12], 2>],
(instregex "^TB[LX]v16i8Two")>;
def : InstRW<[WriteSequence<[M1WriteNAL12], 3>],
(instregex "^TB[LX]v16i8Three")>;
def : InstRW<[WriteSequence<[M1WriteNAL12], 4>],
(instregex "^TB[LX]v16i8Four")>;
def : InstRW<[M1WriteNEOND], (instregex "^[SU]MOVv")>;
def : InstRW<[M1WriteNEONC], (instregex "^INSv.+gpr")>;
def : InstRW<[M1WriteNALU1], (instregex "^(TRN|UZP)[12](v8i8|v4i16|v2i32)")>;
def : InstRW<[M1WriteNALU2], (instregex "^(TRN|UZP)[12](v16i8|v8i16|v4i32|v2i64)")>;
def : InstRW<[M1WriteNALU1], (instregex "^ZIP[12]v")>;
// ASIMD load instructions.
def : InstRW<[M1WriteVLDD], (instregex "LD1i(8|16|32)$")>;
def : InstRW<[M1WriteVLDD,
WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
def : InstRW<[M1WriteVLDE], (instregex "LD1i(64)$")>;
def : InstRW<[M1WriteVLDE,
WriteAdr], (instregex "LD1i(64)_POST$")>;
def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s)$")>;
def : InstRW<[WriteVLD,
WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
def : InstRW<[WriteVLD], (instregex "LD1Rv(1d)$")>;
def : InstRW<[WriteVLD,
WriteAdr], (instregex "LD1Rv(1d)_POST$")>;
def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
def : InstRW<[WriteVLD,
WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
def : InstRW<[WriteVLD,
WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
def : InstRW<[WriteVLD,
WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
def : InstRW<[M1WriteVLDA,
WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
def : InstRW<[M1WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
def : InstRW<[M1WriteVLDA,
WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
def : InstRW<[M1WriteVLDB,
WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
def : InstRW<[M1WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
def : InstRW<[M1WriteVLDB,
WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
def : InstRW<[M1WriteVLDC,
WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
def : InstRW<[M1WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
def : InstRW<[M1WriteVLDC,
WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVLDG], (instregex "LD2i(8|16)$")>;
def : InstRW<[M1WriteVLDG,
WriteAdr], (instregex "LD2i(8|16)_POST$")>;
def : InstRW<[M1WriteVLDG], (instregex "LD2i(32)$")>;
def : InstRW<[M1WriteVLDG,
WriteAdr], (instregex "LD2i(32)_POST$")>;
def : InstRW<[M1WriteVLDH], (instregex "LD2i(64)$")>;
def : InstRW<[M1WriteVLDH,
WriteAdr], (instregex "LD2i(64)_POST$")>;
def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(8b|4h|2s)$")>;
def : InstRW<[M1WriteVLDA,
WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(1d)$")>;
def : InstRW<[M1WriteVLDA,
WriteAdr], (instregex "LD2Rv(1d)_POST$")>;
def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
def : InstRW<[M1WriteVLDA,
WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
def : InstRW<[M1WriteVLDF,
WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(16b|8h|4s)$")>;
def : InstRW<[M1WriteVLDF,
WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(2d)$")>;
def : InstRW<[M1WriteVLDF,
WriteAdr], (instregex "LD2Twov(2d)_POST$")>;
def : InstRW<[M1WriteVLDJ], (instregex "LD3i(8|16)$")>;
def : InstRW<[M1WriteVLDJ,
WriteAdr], (instregex "LD3i(8|16)_POST$")>;
def : InstRW<[M1WriteVLDJ], (instregex "LD3i(32)$")>;
def : InstRW<[M1WriteVLDJ,
WriteAdr], (instregex "LD3i(32)_POST$")>;
def : InstRW<[M1WriteVLDL], (instregex "LD3i(64)$")>;
def : InstRW<[M1WriteVLDL,
WriteAdr], (instregex "LD3i(64)_POST$")>;
def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(8b|4h|2s)$")>;
def : InstRW<[M1WriteVLDB,
WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(1d)$")>;
def : InstRW<[M1WriteVLDB,
WriteAdr], (instregex "LD3Rv(1d)_POST$")>;
def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(16b|8h|4s)$")>;
def : InstRW<[M1WriteVLDB,
WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>;
def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(2d)$")>;
def : InstRW<[M1WriteVLDB,
WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
def : InstRW<[M1WriteVLDI,
WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(16b|8h|4s)$")>;
def : InstRW<[M1WriteVLDI,
WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(2d)$")>;
def : InstRW<[M1WriteVLDI,
WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
def : InstRW<[M1WriteVLDK], (instregex "LD4i(8|16)$")>;
def : InstRW<[M1WriteVLDK,
WriteAdr], (instregex "LD4i(8|16)_POST$")>;
def : InstRW<[M1WriteVLDK], (instregex "LD4i(32)$")>;
def : InstRW<[M1WriteVLDK,
WriteAdr], (instregex "LD4i(32)_POST$")>;
def : InstRW<[M1WriteVLDM], (instregex "LD4i(64)$")>;
def : InstRW<[M1WriteVLDM,
WriteAdr], (instregex "LD4i(64)_POST$")>;
def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(8b|4h|2s)$")>;
def : InstRW<[M1WriteVLDC,
WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(1d)$")>;
def : InstRW<[M1WriteVLDC,
WriteAdr], (instregex "LD4Rv(1d)_POST$")>;
def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(16b|8h|4s)$")>;
def : InstRW<[M1WriteVLDC,
WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>;
def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(2d)$")>;
def : InstRW<[M1WriteVLDC,
WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
def : InstRW<[M1WriteVLDN,
WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(16b|8h|4s)$")>;
def : InstRW<[M1WriteVLDN,
WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(2d)$")>;
def : InstRW<[M1WriteVLDN,
WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
// ASIMD store instructions.
def : InstRW<[M1WriteVSTD], (instregex "ST1i(8|16|32)$")>;
def : InstRW<[M1WriteVSTD,
WriteAdr], (instregex "ST1i(8|16|32)_POST$")>;
def : InstRW<[M1WriteVSTD], (instregex "ST1i(64)$")>;
def : InstRW<[M1WriteVSTD,
WriteAdr], (instregex "ST1i(64)_POST$")>;
def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
def : InstRW<[WriteVST,
WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
def : InstRW<[WriteVST,
WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
def : InstRW<[M1WriteVSTA,
WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
def : InstRW<[M1WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
def : InstRW<[M1WriteVSTA,
WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
def : InstRW<[M1WriteVSTB,
WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
def : InstRW<[M1WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
def : InstRW<[M1WriteVSTB,
WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
def : InstRW<[M1WriteVSTC,
WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
def : InstRW<[M1WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
def : InstRW<[M1WriteVSTC,
WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
def : InstRW<[M1WriteVSTD], (instregex "ST2i(8|16|32)$")>;
def : InstRW<[M1WriteVSTD,
WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
def : InstRW<[M1WriteVSTD], (instregex "ST2i(64)$")>;
def : InstRW<[M1WriteVSTD,
WriteAdr], (instregex "ST2i(64)_POST$")>;
def : InstRW<[M1WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
def : InstRW<[M1WriteVSTD,
WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVSTE], (instregex "ST2Twov(16b|8h|4s)$")>;
def : InstRW<[M1WriteVSTE,
WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
def : InstRW<[M1WriteVSTE], (instregex "ST2Twov(2d)$")>;
def : InstRW<[M1WriteVSTE,
WriteAdr], (instregex "ST2Twov(2d)_POST$")>;
def : InstRW<[M1WriteVSTH], (instregex "ST3i(8|16)$")>;
def : InstRW<[M1WriteVSTH,
WriteAdr], (instregex "ST3i(8|16)_POST$")>;
def : InstRW<[M1WriteVSTH], (instregex "ST3i(32)$")>;
def : InstRW<[M1WriteVSTH,
WriteAdr], (instregex "ST3i(32)_POST$")>;
def : InstRW<[M1WriteVSTF], (instregex "ST3i(64)$")>;
def : InstRW<[M1WriteVSTF,
WriteAdr], (instregex "ST3i(64)_POST$")>;
def : InstRW<[M1WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
def : InstRW<[M1WriteVSTF,
WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVSTG], (instregex "ST3Threev(16b|8h|4s)$")>;
def : InstRW<[M1WriteVSTG,
WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
def : InstRW<[M1WriteVSTG], (instregex "ST3Threev(2d)$")>;
def : InstRW<[M1WriteVSTG,
WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
def : InstRW<[M1WriteVSTH], (instregex "ST4i(8|16)$")>;
def : InstRW<[M1WriteVSTH,
WriteAdr], (instregex "ST4i(8|16)_POST$")>;
def : InstRW<[M1WriteVSTH], (instregex "ST4i(32)$")>;
def : InstRW<[M1WriteVSTH,
WriteAdr], (instregex "ST4i(32)_POST$")>;
def : InstRW<[M1WriteVSTF], (instregex "ST4i(64)$")>;
def : InstRW<[M1WriteVSTF,
WriteAdr], (instregex "ST4i(64)_POST$")>;
def : InstRW<[M1WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>;
def : InstRW<[M1WriteVSTF,
WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
def : InstRW<[M1WriteVSTI], (instregex "ST4Fourv(16b|8h|4s)$")>;
def : InstRW<[M1WriteVSTI,
WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
def : InstRW<[M1WriteVSTI], (instregex "ST4Fourv(2d)$")>;
def : InstRW<[M1WriteVSTI,
WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
// Cryptography instructions.
def : InstRW<[M1WriteAES], (instregex "^AES[DE]")>;
def : InstRW<[M1WriteAES, M1ReadAES], (instregex "^AESI?MC")>;
def : InstRW<[M1WriteNCRYPT1], (instregex "^PMUL")>;
def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA1(H|SU)")>;
def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA1[CMP]")>;
def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA256SU0")>;
def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA256(H|SU1)")>;
// CRC instructions.
def : InstRW<[M1WriteC2], (instregex "^CRC32")>;
} // SchedModel = ExynosM1Model

6
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
View File

@ -94,12 +94,6 @@ void AArch64Subtarget::initializeProperties() {
MinPrefetchStride = 2048;
MaxPrefetchIterationsAhead = 3;
break;
case ExynosM1:
MaxInterleaveFactor = 4;
MaxJumpTableSize = 8;
PrefFunctionLogAlignment = 4;
PrefLoopLogAlignment = 3;
break;
case ExynosM3:
MaxInterleaveFactor = 4;
MaxJumpTableSize = 20;

1
llvm/lib/Target/AArch64/AArch64Subtarget.h
View File

@ -48,7 +48,6 @@ public:
CortexA75,
CortexA76,
Cyclone,
ExynosM1,
ExynosM3,
Falkor,
Kryo,

2
llvm/lib/Target/ARM/ARM.td
View File

@ -1197,8 +1197,6 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
FeatureZCZeroing,
FeatureNoPostRASched]>;
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>;
def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>;
def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>;
def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos,
FeatureFullFP16,

2
llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
View File

@ -1,6 +1,6 @@
# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=UNPROFITABLE,ALL %s
# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=falkor -enable-unsafe-fp-math %s -machine-combiner-verify-pattern-order=true | FileCheck --check-prefixes=PROFITABLE,ALL %s
# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=exynos-m1 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
#
name: f1_2s

34
llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
View File

@ -1,6 +1,5 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOSM1 %s
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m3 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; Test ldr clustering.
@ -9,11 +8,6 @@
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
; EXYNOSM1: ********** MI Scheduling **********
; EXYNOSM1-LABEL: ldr_int:%bb.0
; EXYNOSM1: Cluster ld/st SU(1) - SU(2)
; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
define i32 @ldr_int(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 1
%tmp1 = load i32, i32* %p1, align 2
@ -29,11 +23,6 @@ define i32 @ldr_int(i32* %a) nounwind {
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
; CHECK: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
; EXYNOSM1: ********** MI Scheduling **********
; EXYNOSM1-LABEL: ldp_sext_int:%bb.0
; EXYNOSM1: Cluster ld/st SU(1) - SU(2)
; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
define i64 @ldp_sext_int(i32* %p) nounwind {
%tmp = load i32, i32* %p, align 4
%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
@ -50,11 +39,6 @@ define i64 @ldp_sext_int(i32* %p) nounwind {
; CHECK: Cluster ld/st SU(2) - SU(1)
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
; EXYNOSM1: ********** MI Scheduling **********
; EXYNOSM1-LABEL: ldur_int:%bb.0
; EXYNOSM1: Cluster ld/st SU(2) - SU(1)
; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
define i32 @ldur_int(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 -1
%tmp1 = load i32, i32* %p1, align 2
@ -70,11 +54,6 @@ define i32 @ldur_int(i32* %a) nounwind {
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
; CHECK: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
; EXYNOSM1: ********** MI Scheduling **********
; EXYNOSM1-LABEL: ldp_half_sext_zext_int:%bb.0
; EXYNOSM1: Cluster ld/st SU(3) - SU(4)
; EXYNOSM1: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
; EXYNOSM1: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
%tmp0 = load i64, i64* %q, align 4
%tmp = load i32, i32* %p, align 4
@ -93,11 +72,6 @@ define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
; CHECK: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
; EXYNOSM1: ********** MI Scheduling **********
; EXYNOSM1-LABEL: ldp_half_zext_sext_int:%bb.0
; EXYNOSM1: Cluster ld/st SU(3) - SU(4)
; EXYNOSM1: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
; EXYNOSM1: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
%tmp0 = load i64, i64* %q, align 4
%tmp = load i32, i32* %p, align 4
@ -116,11 +90,6 @@ define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
; CHECK-NOT: Cluster ld/st
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
; EXYNOSM1: ********** MI Scheduling **********
; EXYNOSM1-LABEL: ldr_int_volatile:%bb.0
; EXYNOSM1-NOT: Cluster ld/st
; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
define i32 @ldr_int_volatile(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 1
%tmp1 = load volatile i32, i32* %p1, align 2
@ -136,9 +105,6 @@ define i32 @ldr_int_volatile(i32* %a) nounwind {
; CHECK: Cluster ld/st SU(1) - SU(3)
; CHECK: SU(1): %{{[0-9]+}}:fpr128 = LDRQui
; CHECK: SU(3): %{{[0-9]+}}:fpr128 = LDRQui
; EXYNOSM1: ********** MI Scheduling **********
; EXYNOSM1-LABEL: ldq_cluster:%bb.0
; EXYNOSM1-NOT: Cluster ld/st
define <2 x i64> @ldq_cluster(i64* %p) {
%a1 = bitcast i64* %p to <2 x i64>*
%tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8

348
llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
View File

@ -1,7 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s --check-prefixes=CHECK,GENERIC
; The instruction latencies of Exynos-M1 trigger the transform we see under the Exynos check.
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m1 | FileCheck %s --check-prefixes=CHECK,EXYNOSM1
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m3 | FileCheck %s --check-prefixes=CHECK,EXYNOSM3
declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>)
@ -437,13 +435,6 @@ define <2 x float> @test_vfma_lane_f32(<2 x float> %a, <2 x float> %b, <2 x floa
; GENERIC-NEXT: fmla v0.2s, v1.2s, v2.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfma_lane_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2s, v2.s[1]
; EXYNOSM1-NEXT: fmla v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfma_lane_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -464,13 +455,6 @@ define <4 x float> @test_vfmaq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x flo
; GENERIC-NEXT: fmla v0.4s, v1.4s, v2.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmaq_lane_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.4s, v2.s[1]
; EXYNOSM1-NEXT: fmla v0.4s, v1.4s, v2.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmaq_lane_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -490,12 +474,6 @@ define <2 x float> @test_vfma_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x flo
; GENERIC-NEXT: fmla v0.2s, v1.2s, v2.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfma_laneq_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.2s, v2.s[3]
; EXYNOSM1-NEXT: fmla v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfma_laneq_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmla v0.2s, v1.2s, v2.s[3]
@ -512,12 +490,6 @@ define <4 x float> @test_vfmaq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x fl
; GENERIC-NEXT: fmla v0.4s, v1.4s, v2.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmaq_laneq_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.4s, v2.s[3]
; EXYNOSM1-NEXT: fmla v0.4s, v1.4s, v2.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmaq_laneq_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmla v0.4s, v1.4s, v2.s[3]
@ -535,13 +507,6 @@ define <2 x float> @test_vfms_lane_f32(<2 x float> %a, <2 x float> %b, <2 x floa
; GENERIC-NEXT: fmls v0.2s, v1.2s, v2.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfms_lane_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2s, v2.s[1]
; EXYNOSM1-NEXT: fmls v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfms_lane_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -561,13 +526,6 @@ define <4 x float> @test_vfmsq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x flo
; GENERIC-NEXT: fmls v0.4s, v1.4s, v2.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmsq_lane_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.4s, v2.s[1]
; EXYNOSM1-NEXT: fmls v0.4s, v1.4s, v2.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmsq_lane_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -586,12 +544,6 @@ define <2 x float> @test_vfms_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x flo
; GENERIC-NEXT: fmls v0.2s, v1.2s, v2.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfms_laneq_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.2s, v2.s[3]
; EXYNOSM1-NEXT: fmls v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfms_laneq_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmls v0.2s, v1.2s, v2.s[3]
@ -609,12 +561,6 @@ define <4 x float> @test_vfmsq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x fl
; GENERIC-NEXT: fmls v0.4s, v1.4s, v2.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmsq_laneq_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.4s, v2.s[3]
; EXYNOSM1-NEXT: fmls v0.4s, v1.4s, v2.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmsq_laneq_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmls v0.4s, v1.4s, v2.s[3]
@ -633,13 +579,6 @@ define <2 x double> @test_vfmaq_lane_f64(<2 x double> %a, <2 x double> %b, <1 x
; GENERIC-NEXT: fmla v0.2d, v1.2d, v2.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmaq_lane_f64:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2d, v2.d[0]
; EXYNOSM1-NEXT: fmla v0.2d, v1.2d, v2.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmaq_lane_f64:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -659,12 +598,6 @@ define <2 x double> @test_vfmaq_laneq_f64(<2 x double> %a, <2 x double> %b, <2 x
; GENERIC-NEXT: fmla v0.2d, v1.2d, v2.d[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmaq_laneq_f64:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.2d, v2.d[1]
; EXYNOSM1-NEXT: fmla v0.2d, v1.2d, v2.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmaq_laneq_f64:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmla v0.2d, v1.2d, v2.d[1]
@ -682,13 +615,6 @@ define <2 x double> @test_vfmsq_lane_f64(<2 x double> %a, <2 x double> %b, <1 x
; GENERIC-NEXT: fmls v0.2d, v1.2d, v2.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmsq_lane_f64:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2d, v2.d[0]
; EXYNOSM1-NEXT: fmls v0.2d, v1.2d, v2.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmsq_lane_f64:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -707,12 +633,6 @@ define <2 x double> @test_vfmsq_laneq_f64(<2 x double> %a, <2 x double> %b, <2 x
; GENERIC-NEXT: fmls v0.2d, v1.2d, v2.d[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmsq_laneq_f64:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.2d, v2.d[1]
; EXYNOSM1-NEXT: fmls v0.2d, v1.2d, v2.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmsq_laneq_f64:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmls v0.2d, v1.2d, v2.d[1]
@ -1752,13 +1672,6 @@ define <2 x float> @test_vmul_lane_f32(<2 x float> %a, <2 x float> %v) {
; GENERIC-NEXT: fmul v0.2s, v0.2s, v1.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmul_lane_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.2s, v1.s[1]
; EXYNOSM1-NEXT: fmul v0.2s, v0.2s, v1.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmul_lane_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -1791,13 +1704,6 @@ define <4 x float> @test_vmulq_lane_f32(<4 x float> %a, <2 x float> %v) {
; GENERIC-NEXT: fmul v0.4s, v0.4s, v1.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulq_lane_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.4s, v1.s[1]
; EXYNOSM1-NEXT: fmul v0.4s, v0.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulq_lane_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -1816,13 +1722,6 @@ define <2 x double> @test_vmulq_lane_f64(<2 x double> %a, <1 x double> %v) {
; GENERIC-NEXT: fmul v0.2d, v0.2d, v1.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulq_lane_f64:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.2d, v1.d[0]
; EXYNOSM1-NEXT: fmul v0.2d, v0.2d, v1.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulq_lane_f64:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -1840,12 +1739,6 @@ define <2 x float> @test_vmul_laneq_f32(<2 x float> %a, <4 x float> %v) {
; GENERIC-NEXT: fmul v0.2s, v0.2s, v1.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmul_laneq_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.2s, v1.s[3]
; EXYNOSM1-NEXT: fmul v0.2s, v0.2s, v1.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmul_laneq_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmul v0.2s, v0.2s, v1.s[3]
@ -1876,12 +1769,6 @@ define <4 x float> @test_vmulq_laneq_f32(<4 x float> %a, <4 x float> %v) {
; GENERIC-NEXT: fmul v0.4s, v0.4s, v1.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulq_laneq_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.4s, v1.s[3]
; EXYNOSM1-NEXT: fmul v0.4s, v0.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulq_laneq_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmul v0.4s, v0.4s, v1.s[3]
@ -1898,12 +1785,6 @@ define <2 x double> @test_vmulq_laneq_f64(<2 x double> %a, <2 x double> %v) {
; GENERIC-NEXT: fmul v0.2d, v0.2d, v1.d[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulq_laneq_f64:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.2d, v1.d[1]
; EXYNOSM1-NEXT: fmul v0.2d, v0.2d, v1.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulq_laneq_f64:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmul v0.2d, v0.2d, v1.d[1]
@ -1921,13 +1802,6 @@ define <2 x float> @test_vmulx_lane_f32(<2 x float> %a, <2 x float> %v) {
; GENERIC-NEXT: fmulx v0.2s, v0.2s, v1.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulx_lane_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.2s, v1.s[1]
; EXYNOSM1-NEXT: fmulx v0.2s, v0.2s, v1.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulx_lane_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -1946,13 +1820,6 @@ define <4 x float> @test_vmulxq_lane_f32(<4 x float> %a, <2 x float> %v) {
; GENERIC-NEXT: fmulx v0.4s, v0.4s, v1.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulxq_lane_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.4s, v1.s[1]
; EXYNOSM1-NEXT: fmulx v0.4s, v0.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulxq_lane_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -1971,13 +1838,6 @@ define <2 x double> @test_vmulxq_lane_f64(<2 x double> %a, <1 x double> %v) {
; GENERIC-NEXT: fmulx v0.2d, v0.2d, v1.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulxq_lane_f64:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.2d, v1.d[0]
; EXYNOSM1-NEXT: fmulx v0.2d, v0.2d, v1.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulxq_lane_f64:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -1995,12 +1855,6 @@ define <2 x float> @test_vmulx_laneq_f32(<2 x float> %a, <4 x float> %v) {
; GENERIC-NEXT: fmulx v0.2s, v0.2s, v1.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulx_laneq_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.2s, v1.s[3]
; EXYNOSM1-NEXT: fmulx v0.2s, v0.2s, v1.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulx_laneq_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmulx v0.2s, v0.2s, v1.s[3]
@ -2017,12 +1871,6 @@ define <4 x float> @test_vmulxq_laneq_f32(<4 x float> %a, <4 x float> %v) {
; GENERIC-NEXT: fmulx v0.4s, v0.4s, v1.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulxq_laneq_f32:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.4s, v1.s[3]
; EXYNOSM1-NEXT: fmulx v0.4s, v0.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulxq_laneq_f32:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmulx v0.4s, v0.4s, v1.s[3]
@ -2039,12 +1887,6 @@ define <2 x double> @test_vmulxq_laneq_f64(<2 x double> %a, <2 x double> %v) {
; GENERIC-NEXT: fmulx v0.2d, v0.2d, v1.d[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulxq_laneq_f64:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.2d, v1.d[1]
; EXYNOSM1-NEXT: fmulx v0.2d, v0.2d, v1.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulxq_laneq_f64:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmulx v0.2d, v0.2d, v1.d[1]
@ -2446,13 +2288,6 @@ define <2 x float> @test_vfma_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x fl
; GENERIC-NEXT: fmla v0.2s, v1.2s, v2.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfma_lane_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2s, v2.s[0]
; EXYNOSM1-NEXT: fmla v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfma_lane_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -2471,13 +2306,6 @@ define <4 x float> @test_vfmaq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x f
; GENERIC-NEXT: fmla v0.4s, v1.4s, v2.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmaq_lane_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.4s, v2.s[0]
; EXYNOSM1-NEXT: fmla v0.4s, v1.4s, v2.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmaq_lane_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -2495,12 +2323,6 @@ define <2 x float> @test_vfma_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x f
; GENERIC-NEXT: fmla v0.2s, v1.2s, v2.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfma_laneq_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.2s, v2.s[0]
; EXYNOSM1-NEXT: fmla v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfma_laneq_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmla v0.2s, v1.2s, v2.s[0]
@ -2517,12 +2339,6 @@ define <4 x float> @test_vfmaq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x
; GENERIC-NEXT: fmla v0.4s, v1.4s, v2.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmaq_laneq_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.4s, v2.s[0]
; EXYNOSM1-NEXT: fmla v0.4s, v1.4s, v2.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmaq_laneq_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmla v0.4s, v1.4s, v2.s[0]
@ -2540,13 +2356,6 @@ define <2 x float> @test_vfms_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x fl
; GENERIC-NEXT: fmls v0.2s, v1.2s, v2.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfms_lane_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2s, v2.s[0]
; EXYNOSM1-NEXT: fmls v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfms_lane_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -2566,13 +2375,6 @@ define <4 x float> @test_vfmsq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x f
; GENERIC-NEXT: fmls v0.4s, v1.4s, v2.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmsq_lane_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.4s, v2.s[0]
; EXYNOSM1-NEXT: fmls v0.4s, v1.4s, v2.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmsq_lane_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -2591,12 +2393,6 @@ define <2 x float> @test_vfms_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x f
; GENERIC-NEXT: fmls v0.2s, v1.2s, v2.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfms_laneq_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.2s, v2.s[0]
; EXYNOSM1-NEXT: fmls v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfms_laneq_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmls v0.2s, v1.2s, v2.s[0]
@ -2614,12 +2410,6 @@ define <4 x float> @test_vfmsq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x
; GENERIC-NEXT: fmls v0.4s, v1.4s, v2.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmsq_laneq_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.4s, v2.s[0]
; EXYNOSM1-NEXT: fmls v0.4s, v1.4s, v2.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmsq_laneq_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmls v0.4s, v1.4s, v2.s[0]
@ -2637,12 +2427,6 @@ define <2 x double> @test_vfmaq_laneq_f64_0(<2 x double> %a, <2 x double> %b, <2
; GENERIC-NEXT: fmla v0.2d, v1.2d, v2.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmaq_laneq_f64_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.2d, v2.d[0]
; EXYNOSM1-NEXT: fmla v0.2d, v1.2d, v2.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmaq_laneq_f64_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmla v0.2d, v1.2d, v2.d[0]
@ -2659,12 +2443,6 @@ define <2 x double> @test_vfmsq_laneq_f64_0(<2 x double> %a, <2 x double> %b, <2
; GENERIC-NEXT: fmls v0.2d, v1.2d, v2.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfmsq_laneq_f64_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v2.2d, v2.d[0]
; EXYNOSM1-NEXT: fmls v0.2d, v1.2d, v2.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfmsq_laneq_f64_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmls v0.2d, v1.2d, v2.d[0]
@ -3591,13 +3369,6 @@ define <2 x float> @test_vmul_lane_f32_0(<2 x float> %a, <2 x float> %v) {
; GENERIC-NEXT: fmul v0.2s, v0.2s, v1.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmul_lane_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.2s, v1.s[0]
; EXYNOSM1-NEXT: fmul v0.2s, v0.2s, v1.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmul_lane_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -3616,13 +3387,6 @@ define <4 x float> @test_vmulq_lane_f32_0(<4 x float> %a, <2 x float> %v) {
; GENERIC-NEXT: fmul v0.4s, v0.4s, v1.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulq_lane_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.4s, v1.s[0]
; EXYNOSM1-NEXT: fmul v0.4s, v0.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulq_lane_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -3640,12 +3404,6 @@ define <2 x float> @test_vmul_laneq_f32_0(<2 x float> %a, <4 x float> %v) {
; GENERIC-NEXT: fmul v0.2s, v0.2s, v1.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmul_laneq_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.2s, v1.s[0]
; EXYNOSM1-NEXT: fmul v0.2s, v0.2s, v1.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmul_laneq_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmul v0.2s, v0.2s, v1.s[0]
@ -3676,12 +3434,6 @@ define <4 x float> @test_vmulq_laneq_f32_0(<4 x float> %a, <4 x float> %v) {
; GENERIC-NEXT: fmul v0.4s, v0.4s, v1.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulq_laneq_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.4s, v1.s[0]
; EXYNOSM1-NEXT: fmul v0.4s, v0.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulq_laneq_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmul v0.4s, v0.4s, v1.s[0]
@ -3698,12 +3450,6 @@ define <2 x double> @test_vmulq_laneq_f64_0(<2 x double> %a, <2 x double> %v) {
; GENERIC-NEXT: fmul v0.2d, v0.2d, v1.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulq_laneq_f64_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.2d, v1.d[0]
; EXYNOSM1-NEXT: fmul v0.2d, v0.2d, v1.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulq_laneq_f64_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmul v0.2d, v0.2d, v1.d[0]
@ -3721,13 +3467,6 @@ define <2 x float> @test_vmulx_lane_f32_0(<2 x float> %a, <2 x float> %v) {
; GENERIC-NEXT: fmulx v0.2s, v0.2s, v1.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulx_lane_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.2s, v1.s[0]
; EXYNOSM1-NEXT: fmulx v0.2s, v0.2s, v1.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulx_lane_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -3746,13 +3485,6 @@ define <4 x float> @test_vmulxq_lane_f32_0(<4 x float> %a, <2 x float> %v) {
; GENERIC-NEXT: fmulx v0.4s, v0.4s, v1.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulxq_lane_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.4s, v1.s[0]
; EXYNOSM1-NEXT: fmulx v0.4s, v0.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulxq_lane_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -3771,13 +3503,6 @@ define <2 x double> @test_vmulxq_lane_f64_0(<2 x double> %a, <1 x double> %v) {
; GENERIC-NEXT: fmulx v0.2d, v0.2d, v1.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulxq_lane_f64_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d1 killed $d1 def $q1
; EXYNOSM1-NEXT: dup v1.2d, v1.d[0]
; EXYNOSM1-NEXT: fmulx v0.2d, v0.2d, v1.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulxq_lane_f64_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d1 killed $d1 def $q1
@ -3795,12 +3520,6 @@ define <2 x float> @test_vmulx_laneq_f32_0(<2 x float> %a, <4 x float> %v) {
; GENERIC-NEXT: fmulx v0.2s, v0.2s, v1.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulx_laneq_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.2s, v1.s[0]
; EXYNOSM1-NEXT: fmulx v0.2s, v0.2s, v1.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulx_laneq_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmulx v0.2s, v0.2s, v1.s[0]
@ -3817,12 +3536,6 @@ define <4 x float> @test_vmulxq_laneq_f32_0(<4 x float> %a, <4 x float> %v) {
; GENERIC-NEXT: fmulx v0.4s, v0.4s, v1.s[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulxq_laneq_f32_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.4s, v1.s[0]
; EXYNOSM1-NEXT: fmulx v0.4s, v0.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulxq_laneq_f32_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmulx v0.4s, v0.4s, v1.s[0]
@ -3839,12 +3552,6 @@ define <2 x double> @test_vmulxq_laneq_f64_0(<2 x double> %a, <2 x double> %v) {
; GENERIC-NEXT: fmulx v0.2d, v0.2d, v1.d[0]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vmulxq_laneq_f64_0:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v1.2d, v1.d[0]
; EXYNOSM1-NEXT: fmulx v0.2d, v0.2d, v1.2d
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vmulxq_laneq_f64_0:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmulx v0.2d, v0.2d, v1.d[0]
@ -3862,13 +3569,6 @@ define <4 x float> @optimize_dup(<4 x float> %a, <4 x float> %b, <4 x float> %c,
; GENERIC-NEXT: fmls v0.4s, v2.4s, v3.s[3]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: optimize_dup:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v3.4s, v3.s[3]
; EXYNOSM1-NEXT: fmla v0.4s, v1.4s, v3.4s
; EXYNOSM1-NEXT: fmls v0.4s, v2.4s, v3.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: optimize_dup:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmla v0.4s, v1.4s, v3.s[3]
@ -3890,14 +3590,6 @@ define <4 x float> @no_optimize_dup(<4 x float> %a, <4 x float> %b, <4 x float>
; GENERIC-NEXT: fmls v0.4s, v2.4s, v3.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: no_optimize_dup:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: dup v4.4s, v3.s[3]
; EXYNOSM1-NEXT: fmla v0.4s, v1.4s, v4.4s
; EXYNOSM1-NEXT: dup v1.4s, v3.s[1]
; EXYNOSM1-NEXT: fmls v0.4s, v2.4s, v1.4s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: no_optimize_dup:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: fmla v0.4s, v1.4s, v3.s[3]
@ -3919,13 +3611,6 @@ define <2 x float> @test_vfma_lane_simdinstr_opt_pass_caching_a57(<2 x float> %a
; GENERIC-NEXT: fmla v0.2s, v1.2s, v2.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_a57:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2s, v2.s[1]
; EXYNOSM1-NEXT: fmla v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_a57:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
@ -3937,32 +3622,6 @@ entry:
ret <2 x float> %0
}
define <2 x float> @test_vfma_lane_simdinstr_opt_pass_caching_m1(<2 x float> %a, <2 x float> %b, <2 x float> %v) "target-cpu"="exynos-m1" {
; GENERIC-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_m1:
; GENERIC: // %bb.0: // %entry
; GENERIC-NEXT: // kill: def $d2 killed $d2 def $q2
; GENERIC-NEXT: dup v2.2s, v2.s[1]
; GENERIC-NEXT: fmla v0.2s, v1.2s, v2.2s
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_m1:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2s, v2.s[1]
; EXYNOSM1-NEXT: fmla v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_m1:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM3-NEXT: fmla v0.2s, v1.2s, v2.s[1]
; EXYNOSM3-NEXT: ret
entry:
%lane = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 1, i32 1>
%0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
ret <2 x float> %0
}
define <2 x float> @test_vfma_lane_simdinstr_opt_pass_caching_m3(<2 x float> %a, <2 x float> %b, <2 x float> %v) "target-cpu"="exynos-m3" {
; GENERIC-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_m3:
; GENERIC: // %bb.0: // %entry
@ -3970,13 +3629,6 @@ define <2 x float> @test_vfma_lane_simdinstr_opt_pass_caching_m3(<2 x float> %a,
; GENERIC-NEXT: fmla v0.2s, v1.2s, v2.s[1]
; GENERIC-NEXT: ret
;
; EXYNOSM1-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_m3:
; EXYNOSM1: // %bb.0: // %entry
; EXYNOSM1-NEXT: // kill: def $d2 killed $d2 def $q2
; EXYNOSM1-NEXT: dup v2.2s, v2.s[1]
; EXYNOSM1-NEXT: fmla v0.2s, v1.2s, v2.2s
; EXYNOSM1-NEXT: ret
;
; EXYNOSM3-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_m3:
; EXYNOSM3: // %bb.0: // %entry
; EXYNOSM3-NEXT: // kill: def $d2 killed $d2 def $q2

4
llvm/test/CodeGen/AArch64/arm64-st1.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m1 | FileCheck --check-prefix=EXYNOS %s
; The instruction latencies of Exynos-M1 trigger the transform we see under the Exynos check.
; The instruction latencies of Exynos-M3 trigger the transform we see under the Exynos check.
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m3 | FileCheck --check-prefix=EXYNOS %s
define void @st1lane_16b(<16 x i8> %A, i8* %D) {
; CHECK-LABEL: st1lane_16b

1
llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
View File

@ -5,7 +5,6 @@
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-fp | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,ZEROGP,NONEFP
; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone -mattr=+fullfp16 | FileCheck %s -check-prefixes=ALL,ZEROGP,NONE16
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP

2
llvm/test/CodeGen/AArch64/cpus.ll
View File

@ -15,8 +15,6 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a76 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m2 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m4 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m5 2>&1 | FileCheck %s

2
llvm/test/CodeGen/AArch64/jump-table-exynos.ll
View File

@ -1,6 +1,4 @@
; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mattr=+force-32bit-jump-tables -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m1 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m2 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
; Exynos doesn't want jump tables to be compressed for now.

2
llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
View File

@ -3,8 +3,6 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a72 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a73 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cyclone < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s

12
llvm/test/CodeGen/AArch64/max-jump-table.ll
View File

@ -2,7 +2,6 @@
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m1 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM1 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m3 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t
declare void @ext(i32, i32)
@ -42,9 +41,6 @@ entry:
; CHECK8-NOT: %jump-table.2:
; CHECK16-NEXT: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17
; CHECK16-NOT: %jump-table.1:
; CHECKM1-NEXT: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9
; CHECKM1-NEXT: %jump-table.1: %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17
; CHECKM1-NOT: %jump-table.2:
; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17
; CHECKM3-NOT: %jump-table.1:
@ -90,8 +86,6 @@ entry:
; CHECK8-NOT: %jump-table.1:
; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}}
; CHECK16-NOT: %jump-table.1:
; CHECKM1-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4{{$}}
; CHECKM1-NOT: %jump-table.1:
; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}}
; CHECKM3-NOT: %jump-table.1:
; CHECK-DAG: End machine code for function jt2.
@ -137,9 +131,6 @@ entry:
; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7
; CHECK16-NEXT: %jump-table.1: %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12
; CHECK16-NOT: %jump-table.2:
; CHECKM1-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4
; CHECKM1-NEXT: %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10
; CHECKM1-NOT: %jump-table.2:
; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10
; CHECKM3-NOT: %jump-table.1:
; CHECK-DAG: End machine code for function jt3.
@ -192,9 +183,6 @@ entry:
; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7
; CHECK16-NEXT: %jump-table.1: %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12
; CHECK16-NOT: %jump-table.2:
; CHECKM1-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4
; CHECKM1-NEXT: %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10
; CHECKM1-NOT: %jump-table.2:
; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10
; CHECKM3-NOT: %jump-table.1:
; CHECK-DAG: End machine code for function jt4.

2
llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
View File

@ -4,8 +4,6 @@
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m2 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s

1
llvm/test/CodeGen/AArch64/no-quad-ldp-stp.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+slow-paired-128 -verify-machineinstrs -asm-verbose=false | FileCheck %s --check-prefixes=CHECK,SLOW
; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s --check-prefixes=CHECK,SLOW
; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m3 -verify-machineinstrs -asm-verbose=false | FileCheck %s --check-prefixes=CHECK,FAST
; CHECK-LABEL: test_nopair_st

2
llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
View File

@ -18,8 +18,6 @@
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m1 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m2 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
define void @test() {

2
llvm/test/CodeGen/AArch64/remat.ll
View File

@ -9,8 +9,6 @@
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a75 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=neoverse-e1 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=neoverse-n1 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m2 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m4 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m5 -o - %s | FileCheck %s

4
llvm/test/CodeGen/AArch64/strqu.ll
View File

@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-linux-gnu | FileCheck --check-prefixes=CHECK,NOSPLIT %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-linux-gnu | FileCheck --check-prefixes=CHECK,NOSPLIT %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 | FileCheck --check-prefixes=CHECK,NOSPLIT %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-linux-gnu -mcpu=exynos-m1 | FileCheck --check-prefixes=CHECK,SPLIT %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck --check-prefixes=CHECK,NOSPLIT %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-linux-gnu -mcpu=exynos-m3 | FileCheck --check-prefixes=CHECK,NOSPLIT %s
define void @test_split_f(<4 x float> %val, <4 x float>* %addr) {
; NOSPLIT-LABEL: test_split_f:

74
llvm/test/CodeGen/ARM/build-attributes.ll
View File

@ -138,20 +138,14 @@
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a73 | FileCheck %s --check-prefix=CORTEX-A73
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 | FileCheck %s --check-prefix=EXYNOS-M1
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-M1-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m2 | FileCheck %s --check-prefix=EXYNOS-M2
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m2 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-M1-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m2 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m3 | FileCheck %s --check-prefix=EXYNOS-M3
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m3 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-M1-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m3 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m3 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m4 | FileCheck %s --check-prefix=EXYNOS-M4
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m4 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-M1-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m4 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m4 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m5 | FileCheck %s --check-prefix=EXYNOS-M5
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m5 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-M1-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m5 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A-FAST
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
@ -186,10 +180,6 @@
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m1 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m1 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m2 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m2 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m3 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m3 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m4 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
@ -1576,58 +1566,12 @@
; CORTEX-A73: .eabi_attribute 38, 1
; CORTEX-A73: .eabi_attribute 14, 0
; EXYNOS-M1: .cpu exynos-m1
; EXYNOS-M1: .eabi_attribute 6, 14
; EXYNOS-M1: .eabi_attribute 7, 65
; EXYNOS-M1: .eabi_attribute 8, 1
; EXYNOS-M1: .eabi_attribute 9, 2
; EXYNOS-M1: .fpu crypto-neon-fp-armv8
; EXYNOS-M1: .eabi_attribute 12, 3
; EXYNOS-M1-NOT: .eabi_attribute 27
; EXYNOS-M1: .eabi_attribute 36, 1
; EXYNOS-M1: .eabi_attribute 42, 1
; EXYNOS-M1-NOT: .eabi_attribute 44
; EXYNOS-M1: .eabi_attribute 68, 3
; EXYNOS-M1-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; EXYNOS-M1: .eabi_attribute 20, 1
; EXYNOS-M1: .eabi_attribute 21, 1
; EXYNOS-M1-NOT: .eabi_attribute 22
; EXYNOS-M1: .eabi_attribute 23, 3
; EXYNOS-M1: .eabi_attribute 24, 1
; EXYNOS-M1: .eabi_attribute 25, 1
; EXYNOS-M1-NOT: .eabi_attribute 28
; EXYNOS-M1: .eabi_attribute 38, 1
; EXYNOS-M1-FAST-NOT: .eabi_attribute 19
;; The exynos-m1 has the ARMv8 FP unit, which always flushes preserving sign.
; EXYNOS-M1-FAST: .eabi_attribute 20, 2
; EXYNOS-M1-FAST-NOT: .eabi_attribute 21
; EXYNOS-M1-FAST-NOT: .eabi_attribute 22
; EXYNOS-M1-FAST: .eabi_attribute 23, 1
; EXYNOS-M2: .cpu exynos-m2
; EXYNOS-M2: .eabi_attribute 6, 14
; EXYNOS-M2: .eabi_attribute 7, 65
; EXYNOS-M2: .eabi_attribute 8, 1
; EXYNOS-M2: .eabi_attribute 9, 2
; EXYNOS-M2: .fpu crypto-neon-fp-armv8
; EXYNOS-M2: .eabi_attribute 12, 3
; EXYNOS-M2-NOT: .eabi_attribute 27
; EXYNOS-M2: .eabi_attribute 36, 1
; EXYNOS-M2: .eabi_attribute 42, 1
; EXYNOS-M2-NOT: .eabi_attribute 44
; EXYNOS-M2: .eabi_attribute 68, 3
; EXYNOS-M2-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; EXYNOS-M2: .eabi_attribute 20, 1
; EXYNOS-M2: .eabi_attribute 21, 1
; EXYNOS-M2-NOT: .eabi_attribute 22
; EXYNOS-M2: .eabi_attribute 23, 3
; EXYNOS-M2: .eabi_attribute 24, 1
; EXYNOS-M2: .eabi_attribute 25, 1
; EXYNOS-M2-NOT: .eabi_attribute 28
; EXYNOS-M2: .eabi_attribute 38, 1
; EXYNOS-FAST-NOT: .eabi_attribute 19
;; The Exynos processors have the ARMv8 FP unit, which always flushes preserving sign.
; EXYNOS-FAST: .eabi_attribute 20, 2
; EXYNOS-FAST-NOT: .eabi_attribute 21
; EXYNOS-FAST-NOT: .eabi_attribute 22
; EXYNOS-FAST: .eabi_attribute 23, 1
; EXYNOS-M3: .cpu exynos-m3
; EXYNOS-M3: .eabi_attribute 6, 14

8
llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s
View File

@ -1,5 +1,4 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M1
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
@ -8,17 +7,11 @@
# ALL: Iterations: 100
# ALL-NEXT: Instructions: 100
# M1-NEXT: Total Cycles: 26
# M3-NEXT: Total Cycles: 18
# M4-NEXT: Total Cycles: 18
# ALL-NEXT: Total uOps: 100
# M1: Dispatch Width: 4
# M1-NEXT: uOps Per Cycle: 3.85
# M1-NEXT: IPC: 3.85
# M1-NEXT: Block RThroughput: 0.3
# M3: Dispatch Width: 6
# M3-NEXT: uOps Per Cycle: 5.56
# M3-NEXT: IPC: 5.56
@ -39,6 +32,5 @@
# ALL: [1] [2] [3] [4] [5] [6] Instructions:
# M1-NEXT: 1 0 0.25 b main
# M3-NEXT: 1 0 0.17 b main
# M4-NEXT: 1 0 0.17 b main

16
llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s
View File

@ -1,5 +1,4 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM1
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM4
@ -15,17 +14,11 @@
# ALL: Iterations: 100
# ALL-NEXT: Instructions: 800
# EM1-NEXT: Total Cycles: 403
# EM3-NEXT: Total Cycles: 304
# EM4-NEXT: Total Cycles: 304
# ALL-NEXT: Total uOps: 800
# EM1: Dispatch Width: 4
# EM1-NEXT: uOps Per Cycle: 1.99
# EM1-NEXT: IPC: 1.99
# EM1-NEXT: Block RThroughput: 4.0
# EM3: Dispatch Width: 6
# EM3-NEXT: uOps Per Cycle: 2.63
# EM3-NEXT: IPC: 2.63
@ -46,15 +39,6 @@
# ALL: [1] [2] [3] [4] [5] [6] Instructions:
# EM1-NEXT: 1 1 0.33 sub w0, w1, w2, sxtb
# EM1-NEXT: 1 2 0.67 add x3, x4, w5, sxth #1
# EM1-NEXT: 1 1 0.33 subs x6, x7, w8, uxtw #2
# EM1-NEXT: 1 1 0.33 adds x9, x10, x11, uxtx #3
# EM1-NEXT: 1 1 0.33 sub w12, w13, w14, uxtb
# EM1-NEXT: 1 2 0.67 add x15, x16, w17, uxth #1
# EM1-NEXT: 1 2 0.67 subs x18, x19, w20, sxtw #2
# EM1-NEXT: 1 2 0.67 adds x21, x22, x23, sxtx #3
# EM3-NEXT: 1 1 0.25 sub w0, w1, w2, sxtb
# EM3-NEXT: 1 2 0.50 add x3, x4, w5, sxth #1
# EM3-NEXT: 1 1 0.25 subs x6, x7, w8, uxtw #2

6
llvm/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s
View File

@ -1,5 +1,4 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M1
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M3
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M4
@ -10,11 +9,6 @@
# ALL-NEXT: Total Cycles: 2
# ALL-NEXT: Total uOps: 1
# M1: Dispatch Width: 4
# M1-NEXT: uOps Per Cycle: 0.50
# M1-NEXT: IPC: 0.50
# M1-NEXT: Block RThroughput: 0.3
# M3: Dispatch Width: 6
# M3-NEXT: uOps Per Cycle: 0.50
# M3-NEXT: IPC: 0.50

16
llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s
View File

@ -1,5 +1,4 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM1
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3
# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM4
@ -15,17 +14,11 @@
# ALL: Iterations: 100
# ALL-NEXT: Instructions: 800
# EM1-NEXT: Total Cycles: 470
# EM3-NEXT: Total Cycles: 354
# EM4-NEXT: Total Cycles: 329
# ALL-NEXT: Total uOps: 800
# EM1: Dispatch Width: 4
# EM1-NEXT: uOps Per Cycle: 1.70
# EM1-NEXT: IPC: 1.70
# EM1-NEXT: Block RThroughput: 4.7
# EM3: Dispatch Width: 6
# EM3-NEXT: uOps Per Cycle: 2.26
# EM3-NEXT: IPC: 2.26
@ -46,15 +39,6 @@
# ALL: [1] [2] [3] [4] [5] [6] Instructions:
# EM1-NEXT: 1 1 0.33 adds w0, w1, w2
# EM1-NEXT: 1 2 0.67 sub x3, x4, x5, lsr #1
# EM1-NEXT: 1 1 0.33 ands x6, x7, x8, lsl #2
# EM1-NEXT: 1 2 0.67 orr w9, w10, w11, asr #3
# EM1-NEXT: 1 2 0.67 adds w12, w13, w14, lsl #4
# EM1-NEXT: 1 2 0.67 sub x15, x16, x17, lsr #6
# EM1-NEXT: 1 2 0.67 ands x18, x19, x20, lsl #8
# EM1-NEXT: 1 2 0.67 orr w21, w22, w23, asr #10
# EM3-NEXT: 1 1 0.25 adds w0, w1, w2
# EM3-NEXT: 1 2 0.50 sub x3, x4, x5, lsr #1
# EM3-NEXT: 1 1 0.25 ands x6, x7, x8, lsl #2

18
llvm/unittests/Support/Host.cpp
View File

@ -147,7 +147,7 @@ Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU part : 0xd05
processor : 1
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
@ -159,17 +159,17 @@ CPU architecture: 8
EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
"CPU variant : 0xc\n"
"CPU part : 0xafe"),
"exynos-m1");
// Verify Exynos M1.
"exynos-m3");
// Verify Exynos M3.
EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
"CPU variant : 0x1\n"
"CPU part : 0x001"),
"exynos-m1");
// Verify Exynos M2.
"CPU part : 0x002"),
"exynos-m3");
// Verify Exynos M4.
EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
"CPU variant : 0x4\n"
"CPU part : 0x001"),
"exynos-m2");
"CPU variant : 0x1\n"
"CPU part : 0x003"),
"exynos-m4");
const std::string ThunderX2T99ProcCpuInfo = R"(
processor : 0

26
llvm/unittests/Support/TargetParserTest.cpp
View File

@ -267,16 +267,6 @@ TEST(TargetParserTest, testARMCPU) {
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A"));
EXPECT_TRUE(testARMCPU("exynos-m1", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A"));
EXPECT_TRUE(testARMCPU("exynos-m2", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A"));
EXPECT_TRUE(testARMCPU("exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@ -309,7 +299,7 @@ TEST(TargetParserTest, testARMCPU) {
"7-S"));
}
static constexpr unsigned NumARMCPUArchs = 87;
static constexpr unsigned NumARMCPUArchs = 85;
TEST(TargetParserTest, testARMCPUArchList) {
SmallVector<StringRef, NumARMCPUArchs> List;
@ -829,14 +819,6 @@ TEST(TargetParserTest, testAArch64CPU) {
EXPECT_TRUE(testAArch64CPU(
"cyclone", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(
"exynos-m1", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(
"exynos-m2", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(
"exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
@ -908,7 +890,7 @@ TEST(TargetParserTest, testAArch64CPU) {
"8.2-A"));
}
static constexpr unsigned NumAArch64CPUArchs = 28;
static constexpr unsigned NumAArch64CPUArchs = 26;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
@ -969,10 +951,6 @@ TEST(TargetParserTest, testAArch64Extension) {
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cyclone",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("exynos-m1",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("exynos-m2",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("exynos-m3",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_TRUE(testAArch64Extension("exynos-m4",