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[ARM] generate armv6m eXecute Only (XO) code
[ARM] generate armv6m eXecute Only (XO) code for immediates, globals Previously eXecute Only (XO) support was implemented for targets that support MOVW/MOVT (~armv7+). See: https://reviews.llvm.org/D27449 XO prevents the compiler from generating data accesses to code sections. This patch implements XO codegen for armv6-M, which does not support MOVW/MOVT, and must resort to the following general pattern to avoid loads: movs r3, :upper8_15:foo lsls r3, #8 adds r3, :upper0_7:foo lsls r3, #8 adds r3, :lower8_15:foo lsls r3, #8 adds r3, :lower0_7:foo ldr r3, [r3] This is equivalent to the code pattern generated by GCC. The above relocations are new to LLVM and have been implemented in a parent patch: https://reviews.llvm.org/D149443. This patch limits itself to implementing codegen for this pattern and enabling XO for armv6-M in the backend. Separate patches will follow for: - switch tables - replacing specific loads from constant islands which are spread out over the ARM backend codebase. Amongst others: FastISel, call lowering, stack frames. Reviewed By: john.brawn Differential Revision: https://reviews.llvm.org/D152795
This commit is contained in:
Ties Stuij
parent
2f7ab29624
commit
2273741ea2
@ -199,6 +199,15 @@ void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
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O << ":lower16:";
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else if (TF & ARMII::MO_HI16)
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O << ":upper16:";
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else if (TF & ARMII::MO_LO_0_7)
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O << ":lower0_7:";
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else if (TF & ARMII::MO_LO_8_15)
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O << ":lower8_15:";
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else if (TF & ARMII::MO_HI_0_7)
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O << ":upper0_7:";
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else if (TF & ARMII::MO_HI_8_15)
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O << ":upper8_15:";
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GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
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printOffset(MO.getOffset(), O);
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}
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@ -228,6 +237,14 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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O << ":lower16:";
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else if (TF == ARMII::MO_HI16)
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O << ":upper16:";
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else if (TF == ARMII::MO_LO_0_7)
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O << ":lower0_7:";
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else if (TF == ARMII::MO_LO_8_15)
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O << ":lower8_15:";
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else if (TF == ARMII::MO_HI_0_7)
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O << ":upper0_7:";
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else if (TF == ARMII::MO_HI_8_15)
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O << ":upper8_15:";
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O << MO.getImm();
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break;
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}
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@ -3327,7 +3327,8 @@ bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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MachineRegisterInfo *MRI) const {
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// Fold large immediates into add, sub, or, xor.
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unsigned DefOpc = DefMI.getOpcode();
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if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
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if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm &&
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DefOpc != ARM::tMOVi32imm)
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return false;
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if (!DefMI.getOperand(1).isImm())
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// Could be t2MOVi32imm @xx
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@ -5538,7 +5539,10 @@ ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
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using namespace ARMII;
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static const std::pair<unsigned, const char *> TargetFlags[] = {
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{MO_LO16, "arm-lo16"}, {MO_HI16, "arm-hi16"}};
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{MO_LO16, "arm-lo16"}, {MO_HI16, "arm-hi16"},
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{MO_LO_0_7, "arm-lo-0-7"}, {MO_HI_0_7, "arm-hi-0-7"},
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{MO_LO_8_15, "arm-lo-8-15"}, {MO_HI_8_15, "arm-hi-8-15"},
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};
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return ArrayRef(TargetFlags);
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}
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@ -71,6 +71,8 @@ namespace {
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void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
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unsigned Opc, bool IsExt);
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void ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI);
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void ExpandTMOV32BitImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI);
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void ExpandMOV32BitImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI);
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void CMSEClearGPRegs(MachineBasicBlock &MBB,
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@ -969,6 +971,106 @@ static MachineOperand makeImplicit(const MachineOperand &MO) {
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return NewMO;
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}
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void ARMExpandPseudo::ExpandTMOV32BitImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI) {
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MachineInstr &MI = *MBBI;
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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const MachineOperand &MO = MI.getOperand(1);
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MachineInstrBuilder Upper8_15, LSL_U8_15, Upper0_7, Lower8_15, Lower0_7;
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unsigned MIFlags = MI.getFlags();
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LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
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Upper8_15 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tMOVi8), DstReg)
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.addReg(ARM::CPSR, RegState::Kill);
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LSL_U8_15 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
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.addReg(ARM::CPSR, RegState::Kill)
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.addReg(DstReg)
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.addImm(8)
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.add(predOps(ARMCC::AL))
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.setMIFlags(MIFlags);
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Upper0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
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.addReg(ARM::CPSR, RegState::Kill)
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.addReg(DstReg);
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MachineInstr *LSL_U0_7 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
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MBB.insert(MBBI, LSL_U0_7);
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Lower8_15 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
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.addReg(ARM::CPSR, RegState::Kill)
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.addReg(DstReg);
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MachineInstr *LSL_L8_15 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
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MBB.insert(MBBI, LSL_L8_15);
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Lower0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(ARM::CPSR, RegState::Kill)
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.addReg(DstReg);
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Upper8_15.setMIFlags(MIFlags);
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Upper0_7.setMIFlags(MIFlags);
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Lower8_15.setMIFlags(MIFlags);
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Lower0_7.setMIFlags(MIFlags);
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switch (MO.getType()) {
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case MachineOperand::MO_Immediate: {
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unsigned Imm = MO.getImm();
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unsigned Hi8_15 = (Imm >> 24) & 0xff;
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unsigned Hi0_7 = (Imm >> 16) & 0xff;
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unsigned Lo8_15 = (Imm >> 8) & 0xff;
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unsigned Lo0_7 = Imm & 0xff;
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Upper8_15 = Upper8_15.addImm(Hi8_15);
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Upper0_7 = Upper0_7.addImm(Hi0_7);
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Lower8_15 = Lower8_15.addImm(Lo8_15);
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Lower0_7 = Lower0_7.addImm(Lo0_7);
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break;
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}
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case MachineOperand::MO_ExternalSymbol: {
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const char *ES = MO.getSymbolName();
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unsigned TF = MO.getTargetFlags();
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Upper8_15 = Upper8_15.addExternalSymbol(ES, TF | ARMII::MO_HI_8_15);
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Upper0_7 = Upper0_7.addExternalSymbol(ES, TF | ARMII::MO_HI_0_7);
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Lower8_15 = Lower8_15.addExternalSymbol(ES, TF | ARMII::MO_LO_8_15);
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Lower0_7 = Lower0_7.addExternalSymbol(ES, TF | ARMII::MO_LO_0_7);
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break;
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}
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default: {
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const GlobalValue *GV = MO.getGlobal();
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unsigned TF = MO.getTargetFlags();
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Upper8_15 =
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Upper8_15.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI_8_15);
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Upper0_7 =
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Upper0_7.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI_0_7);
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Lower8_15 =
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Lower8_15.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO_8_15);
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Lower0_7 =
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Lower0_7.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO_0_7);
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break;
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}
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}
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Upper8_15 = Upper8_15.add(predOps(ARMCC::AL));
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Upper0_7 = Upper0_7.add(predOps(ARMCC::AL));
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Lower8_15 = Lower8_15.add(predOps(ARMCC::AL));
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Lower0_7 = Lower0_7.add(predOps(ARMCC::AL));
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MI.eraseFromParent();
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LLVM_DEBUG(dbgs() << "To: "; Upper8_15.getInstr()->dump(););
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LLVM_DEBUG(dbgs() << "And: "; LSL_U8_15.getInstr()->dump(););
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LLVM_DEBUG(dbgs() << "And: "; Upper0_7.getInstr()->dump(););
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LLVM_DEBUG(dbgs() << "And: "; LSL_U0_7->dump(););
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LLVM_DEBUG(dbgs() << "And: "; Lower8_15.getInstr()->dump(););
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LLVM_DEBUG(dbgs() << "And: "; LSL_L8_15->dump(););
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LLVM_DEBUG(dbgs() << "And: "; Lower0_7.getInstr()->dump(););
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}
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void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI) {
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MachineInstr &MI = *MBBI;
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@ -2658,6 +2760,10 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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ExpandMOV32BitImm(MBB, MBBI);
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return true;
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case ARM::tMOVi32imm:
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ExpandTMOV32BitImm(MBB, MBBI);
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return true;
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case ARM::SUBS_PC_LR: {
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
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@ -3701,7 +3701,8 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
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case ISD::Constant: {
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unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
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// If we can't materialize the constant we need to use a literal pool
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if (ConstantMaterializationCost(Val, Subtarget) > 2) {
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if (ConstantMaterializationCost(Val, Subtarget) > 2 &&
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!Subtarget->genExecuteOnly()) {
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SDValue CPIdx = CurDAG->getTargetConstantPool(
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ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val),
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TLI->getPointerTy(CurDAG->getDataLayout()));
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@ -3956,9 +3956,12 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
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}
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// If we have T2 ops, we can materialize the address directly via movt/movw
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// pair. This is always cheaper.
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if (Subtarget->useMovt()) {
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++NumMovwMovt;
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// pair. This is always cheaper. If need to generate Execute Only code, and we
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// only have Thumb1 available, we can't use a constant pool and are forced to
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// use immediate relocations.
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if (Subtarget->useMovt() || Subtarget->genExecuteOnly()) {
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if (Subtarget->useMovt())
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++NumMovwMovt;
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// FIXME: Once remat is capable of dealing with instructions with register
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// operands, expand this into two nodes.
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return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
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@ -1603,7 +1603,22 @@ def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
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IIC_iLoad_i,
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[(set tGPR:$dst,
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(ARMWrapper tglobaladdr:$src))]>,
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Requires<[IsThumb, DontUseMovt]>;
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Requires<[IsThumb, DontUseMovt, DontGenExecuteOnly]>;
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// 32-bit immediate using mov/add with the 4 :lower0_7: to :upper8_15:
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// relocations.
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// This is a single pseudo instruction to make it re-materializable.
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// FIXME: Remove this when we can do generalized remat.
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let isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
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def tMOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), NoItinerary,
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[(set rGPR:$dst, (i32 imm:$src))]>,
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Requires<[IsThumb1Only, GenExecuteOnly, DontUseMovt]>;
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def : ARMPat<(ARMWrapper tglobaladdr :$dst), (tMOVi32imm tglobaladdr :$dst)>,
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Requires<[GenT1ExecuteOnly]>;
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def : ARMPat<(ARMWrapper texternalsym :$dst), (tMOVi32imm texternalsym :$dst)>,
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Requires<[GenT1ExecuteOnly]>;
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// TLS globals
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def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
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@ -58,6 +58,22 @@ MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
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MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
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Expr = ARMMCExpr::createUpper16(Expr, OutContext);
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break;
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case ARMII::MO_LO_0_7:
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Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
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Expr = ARMMCExpr::createLower0_7(Expr, OutContext);
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break;
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case ARMII::MO_LO_8_15:
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Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
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Expr = ARMMCExpr::createLower8_15(Expr, OutContext);
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break;
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case ARMII::MO_HI_0_7:
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Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
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Expr = ARMMCExpr::createUpper0_7(Expr, OutContext);
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break;
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case ARMII::MO_HI_8_15:
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Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
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Expr = ARMMCExpr::createUpper8_15(Expr, OutContext);
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break;
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}
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if (!MO.isJTI() && MO.getOffset())
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@ -224,6 +224,10 @@ let RecomputePerFunction = 1 in {
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}
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def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
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def DontGenExecuteOnly : Predicate<"!Subtarget->genExecuteOnly()">;
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def GenT1ExecuteOnly : Predicate<"Subtarget->genExecuteOnly() && "
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"Subtarget->isThumb1Only() && "
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"!Subtarget->hasV8MBaselineOps()">;
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// Armv8.5-A extensions
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def HasSB : Predicate<"Subtarget->hasSB()">,
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@ -187,10 +187,12 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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// Assert this for now to make the change obvious.
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assert(hasV6T2Ops() || !hasThumb2());
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// Execute only support requires movt support
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if (genExecuteOnly()) {
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NoMovt = false;
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assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
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// Execute only support for >= v8-M Baseline requires movt support
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if (hasV8MBaselineOps())
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NoMovt = false;
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if (!hasV6MOps())
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report_fatal_error("Cannot generate execute-only code for this target");
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}
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// Keep a pointer to static instruction cost data for the specified CPU.
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@ -255,7 +255,7 @@ namespace ARMII {
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/// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
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/// just that part of the flag set.
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MO_OPTION_MASK = 0x3,
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MO_OPTION_MASK = 0xf03,
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/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the ".refptr.FOO" symbol. This is used for
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@ -287,11 +287,27 @@ namespace ARMII {
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/// example).
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MO_NONLAZY = 0x80,
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// It's undefined behaviour if an enum overflows the range between its
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// smallest and largest values, but since these are |ed together, it can
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// happen. Put a sentinel in (values of this enum are stored as "unsigned
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// char").
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MO_UNUSED_MAXIMUM = 0xff
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/// MO_LO_0_7 - On a symbol operand, this represents a relocation containing
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/// bits 0 through 7 of the address. Used only with Thumb1 MOV and ADD
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// instructions.
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MO_LO_0_7 = 0x100,
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/// MO_LO_8_15 - On a symbol operand, this represents a relocation
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/// containing
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/// bits 8 through 15 of the address. Used only with Thumb1 MOV and ADD
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// instructions.
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MO_LO_8_15 = 0x200,
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/// MO_HI_0_7 - On a symbol operand, this represents a relocation containing
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/// bits 16 through 23 of the address. Used only with Thumb1 MOV and ADD
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// instructions.
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MO_HI_0_7 = 0x400,
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/// MO_HI_8_15 - On a symbol operand, this represents a relocation
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/// containing
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/// bits 24 through 31 of the address. Used only with Thumb1 MOV and ADD
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// instructions.
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MO_HI_8_15 = 0x800
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};
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enum {
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@ -1,3 +1,4 @@
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; RUN: llc < %s -mtriple=thumbv6m -mattr=+execute-only %s -o - | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7m -mattr=+execute-only %s -o - | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv8m.base -mattr=+execute-only %s -o - | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv8m.base -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck %s
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@ -2,6 +2,7 @@
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; RUN: llc -mtriple=thumbv8m.base-eabi -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
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; RUN: llc -mtriple=thumbv7m-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
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; RUN: llc -mtriple=thumbv8m.main-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
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; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK-T1 %s
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; CHECK-NOT: {{^ *}}.text{{$}}
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; CHECK: .section .text,"axy",%progbits,unique,0
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@ -11,7 +12,15 @@
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define i32 @global() minsize {
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; CHECK-LABEL: global:
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; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var
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; CHECK: movt [[GLOBDEST]], :upper16:var
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; CHECK-NEXT: movt [[GLOBDEST]], :upper16:var
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; CHECK-T1-LABEL: global:
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; CHECK-T1: movs [[GLOBDEST:r[0-9]+]], :upper8_15:var
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; CHECK-T1-NEXT: lsls [[GLOBDEST]], [[GLOBDEST]], #8
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||||
; CHECK-T1-NEXT: adds [[GLOBDEST]], :upper0_7:var
|
||||
; CHECK-T1-NEXT: lsls [[GLOBDEST]], [[GLOBDEST]], #8
|
||||
; CHECK-T1-NEXT: adds [[GLOBDEST]], :lower8_15:var
|
||||
; CHECK-T1-NEXT: lsls [[GLOBDEST]], [[GLOBDEST]], #8
|
||||
; CHECK-T1-NEXT: adds [[GLOBDEST]], :lower0_7:var
|
||||
|
||||
%val = load i32, ptr @var
|
||||
ret i32 %val
|
||||
@ -80,7 +89,35 @@ return: ; preds = %entry, %sw.bb8, %sw
|
||||
define hidden ptr @string_literal() {
|
||||
entry:
|
||||
; CHECK-LABEL: string_literal:
|
||||
; CHECK-NOT: .asciz
|
||||
; CHECK: .fnend
|
||||
; CHECK: movw [[STRLIT:r[0-9]+]], :lower16:.L.str
|
||||
; CHECK-NEXT: movt [[STRLIT]], :upper16:.L.str
|
||||
; CHECK-T1-LABEL: string_literal:
|
||||
; CHECK-T1: movs [[STRLIT:r[0-9]+]], :upper8_15:.L.str
|
||||
; CHECK-T1-NEXT: lsls [[STRLIT]], [[STRLIT]], #8
|
||||
; CHECK-T1-NEXT: adds [[STRLIT]], :upper0_7:.L.str
|
||||
; CHECK-T1-NEXT: lsls [[STRLIT]], [[STRLIT]], #8
|
||||
; CHECK-T1-NEXT: adds [[STRLIT]], :lower8_15:.L.str
|
||||
; CHECK-T1-NEXT: lsls [[STRLIT]], [[STRLIT]], #8
|
||||
; CHECK-T1-NEXT: adds [[STRLIT]], :lower0_7:.L.str
|
||||
|
||||
ret ptr @.str
|
||||
}
|
||||
|
||||
@external_global = external global i32
|
||||
define i32 @test_external_global() {
|
||||
entry:
|
||||
; CHECK-LABEL: external_global:
|
||||
; CHECK: movw [[EXTGLOB:r[0-9]+]], :lower16:external_global
|
||||
; CHECK-NEXT: movt [[EXTGLOB]], :upper16:external_global
|
||||
; CHECK-T1-LABEL: external_global:
|
||||
; CHECK-T1: movs [[EXTGLOB:r[0-9]+]], :upper8_15:external_global
|
||||
; CHECK-T1-NEXT: lsls [[EXTGLOB]], [[EXTGLOB]], #8
|
||||
; CHECK-T1-NEXT: adds [[EXTGLOB]], :upper0_7:external_global
|
||||
; CHECK-T1-NEXT: lsls [[EXTGLOB]], [[EXTGLOB]], #8
|
||||
; CHECK-T1-NEXT: adds [[EXTGLOB]], :lower8_15:external_global
|
||||
; CHECK-T1-NEXT: lsls [[EXTGLOB]], [[EXTGLOB]], #8
|
||||
; CHECK-T1-NEXT: adds [[EXTGLOB]], :lower0_7:external_global
|
||||
|
||||
%v = load i32, ptr @external_global
|
||||
ret i32 %v
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user