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Replace hard asserts with assert macros with different behavior.
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This commit is contained in:
parent
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@ -1326,7 +1326,7 @@ void PrinterCapstone::decoderEmitterEmitPredicateFunction(
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if (!Predicates.empty()) {
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OS.indent(Indentation) << "switch (Idx) {\n";
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OS.indent(Indentation)
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<< "default: /* llvm_unreachable(\"Invalid index!\"); */\n";
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<< "default: CS_ASSERT_RET_VAL(0 && \"Invalid index!\", false);\n";
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unsigned Index = 0;
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for (const auto &Predicate : Predicates) {
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OS.indent(Indentation) << "case " << Index++ << ":\n";
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@ -1335,7 +1335,7 @@ void PrinterCapstone::decoderEmitterEmitPredicateFunction(
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OS.indent(Indentation) << "}\n";
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} else {
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// No case statement to emit
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OS.indent(Indentation) << "/* llvm_unreachable(\"Invalid index!\"); */\n";
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OS.indent(Indentation) << "CS_ASSERT_RET_VAL(0 && \"Invalid index!\", false);\n";
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}
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Indentation -= 2;
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OS.indent(Indentation) << "}\n\n";
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@ -1357,7 +1357,7 @@ void PrinterCapstone::decoderEmitterEmitDecoderFunction(
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OS.indent(Indentation) << "InsnType tmp; \\\n";
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OS.indent(Indentation) << "switch (Idx) { \\\n";
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OS.indent(Indentation)
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<< "default: /* llvm_unreachable(\"Invalid index!\"); */ \\\n";
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<< "default: CS_ASSERT_RET_VAL(0 && \"Invalid index!\", MCDisassembler_Fail); \\\n";
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unsigned Index = 0;
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for (const auto &Decoder : Decoders) {
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OS.indent(Indentation) << "case " << Index++ << ": \\\n";
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@ -1371,6 +1371,7 @@ void PrinterCapstone::decoderEmitterEmitDecoderFunction(
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void PrinterCapstone::decoderEmitterEmitIncludes() const {
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OS << "#include \"../../MCInst.h\"\n"
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<< "#include \"../../cs_priv.h\"\n"
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<< "#include \"../../LEB128.h\"\n\n";
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}
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@ -1385,7 +1386,7 @@ void PrinterCapstone::decoderEmitterEmitSourceFileHeader() const {
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void PrinterCapstone::asmWriterEmitSourceFileHeader(RecordKeeper &Records) const {
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emitDefaultSourceFileHeader(OS);
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OS << "#include <capstone/platform.h>\n"
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<< "#include <assert.h>\n\n";
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<< "#include \"../../cs_priv.h\"\n\n";
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}
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void PrinterCapstone::asmWriterEmitGetMnemonic(
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@ -1481,7 +1482,7 @@ void PrinterCapstone::asmWriterEmitPrintInstruction(
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OS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
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<< "_t Bits = MnemonicInfo.second;\n"
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<< " assert(Bits != 0 && \"Cannot print this instruction.\");\n";
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<< " CS_ASSERT_RET(Bits != 0 && \"Cannot print this instruction.\");\n";
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// Output the table driven operand information.
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BitsLeft = OpcodeInfoBits - AsmStrBits;
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@ -1509,7 +1510,7 @@ void PrinterCapstone::asmWriterEmitPrintInstruction(
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} else {
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OS << " switch ((Bits >> " << (OpcodeInfoBits - BitsLeft) << ") & "
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<< ((1 << NumBits) - 1) << ") {\n"
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<< " default: assert(0 && \"Invalid command number.\");\n";
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<< " default: CS_ASSERT_RET(0 && \"Invalid command number.\");\n";
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// Print out all the cases.
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for (unsigned J = 0, F = Commands.size(); J != F; ++J) {
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@ -1545,7 +1546,7 @@ void PrinterCapstone::asmWriterEmitOpCases(
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void PrinterCapstone::asmWriterEmitInstrSwitch() const {
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OS << " switch (MCInst_getOpcode(MI)) {\n";
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OS << " default: assert(0 && \"Unexpected opcode.\");\n";
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OS << " default: CS_ASSERT_RET(0 && \"Unexpected opcode.\");\n";
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}
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void PrinterCapstone::asmWriterEmitCompoundClosure(unsigned Indent,
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@ -1578,7 +1579,7 @@ void PrinterCapstone::asmWriterEmitInstruction(
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// If this is the operand that varies between all of the instructions,
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// emit a switch for just this operand now.
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OS << " switch (MCInst_getOpcode(MI)) {\n";
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OS << " default: assert(0 && \"Unexpected opcode.\");\n";
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OS << " default: CS_ASSERT_RET(0 && \"Unexpected opcode.\");\n";
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std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
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OpsToPrint.push_back(
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std::make_pair(FirstInst.CGI->Namespace.str() + "_" +
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@ -1615,8 +1616,8 @@ void PrinterCapstone::asmWriterEmitGetRegNameAssert(
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else
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OS << "getRegisterName(unsigned RegNo) {\n";
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OS << "#ifndef CAPSTONE_DIET\n";
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OS << " assert(RegNo && RegNo < " << (RegSize + 1)
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<< " && \"Invalid register number!\");\n"
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OS << " CS_ASSERT_RET_VAL(RegNo && RegNo < " << (RegSize + 1)
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<< " && \"Invalid register number!\", NULL);\n"
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<< "\n";
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}
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@ -1647,8 +1648,8 @@ void PrinterCapstone::asmWriterEmitAltIdxSwitch(
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StringRef const &Namespace) const {
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if (HasAltNames) {
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OS << " switch(AltIdx) {\n"
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<< " default: assert(0 && \"Invalid register alt name "
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"index!\");\n";
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<< " default: CS_ASSERT_RET_VAL(0 && \"Invalid register alt name "
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"index!\", NULL);\n";
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for (const Record *R : AltNameIndices) {
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StringRef const AltName = R->getName();
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OS << " case ";
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@ -1656,9 +1657,9 @@ void PrinterCapstone::asmWriterEmitAltIdxSwitch(
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OS << Namespace << "_";
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OS << AltName << ":\n";
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if (R->isValueUnset("FallbackRegAltNameIndex"))
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OS << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
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OS << " CS_ASSERT_RET_VAL(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
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<< "[RegNo-1]) &&\n"
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<< " \"Invalid alt name index for register!\");\n";
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<< " \"Invalid alt name index for register!\", NULL);\n";
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else {
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OS << " if (!*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
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<< "[RegNo-1]))\n"
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@ -1672,8 +1673,8 @@ void PrinterCapstone::asmWriterEmitAltIdxSwitch(
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}
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OS << " }\n";
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} else {
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OS << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
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<< " \"Invalid alt name index for register!\");\n"
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OS << " CS_ASSERT_RET_VAL(*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
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<< " \"Invalid alt name index for register!\", NULL);\n"
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<< " return AsmStrs+RegAsmOffset[RegNo-1];\n";
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}
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OS << "#else\n"
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@ -1872,11 +1873,11 @@ void PrinterCapstone::asmWriterEmitPrintAliasOp(
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<< " SStream *OS) {\n"
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<< "#ifndef CAPSTONE_DIET\n";
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if (PrintMethods.empty())
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OS << " assert(0 && \"Unknown PrintMethod kind\");\n";
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OS << " CS_ASSERT_RET(0 && \"Unknown PrintMethod kind\");\n";
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else {
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OS << " switch (PrintMethodIdx) {\n"
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<< " default:\n"
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<< " assert(0 && \"Unknown PrintMethod kind\");\n"
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<< " CS_ASSERT_RET(0 && \"Unknown PrintMethod kind\");\n"
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<< " break;\n";
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for (unsigned I = 0; I < PrintMethods.size(); ++I) {
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@ -1903,7 +1904,7 @@ void PrinterCapstone::asmWriterEmitPrintMC(
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<< " unsigned PredicateIndex) {\n"
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<< " switch (PredicateIndex) {\n"
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<< " default:\n"
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<< " assert(0 && \"Unknown MCOperandPredicate kind\");\n"
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<< " CS_ASSERT_RET_VAL(0 && \"Unknown MCOperandPredicate kind\", false);\n"
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<< " return false;\n";
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for (unsigned I = 0; I < MCOpPredicates.size(); ++I) {
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