Give helpers internal linkage. NFC.

clang/lib/StaticAnalyzer/Checkers/cert/PutenvWithAutoChecker.cpp

@@ -24,6 +24,7 @@
 using namespace clang;
 using namespace ento;
 
+namespace {
 class PutenvWithAutoChecker : public Checker<check::PostCall> {
 private:
   BugType BT{this, "'putenv' function should not be called with auto variables",
@@ -33,6 +34,7 @@ private:
 public:
   void checkPostCall(const CallEvent &Call, CheckerContext &C) const;
 };
+} // namespace
 
 void PutenvWithAutoChecker::checkPostCall(const CallEvent &Call,
                                           CheckerContext &C) const {

llvm/lib/CodeGen/ReachingDefAnalysis.cpp

@@ -21,23 +21,23 @@ char ReachingDefAnalysis::ID = 0;
 INITIALIZE_PASS(ReachingDefAnalysis, DEBUG_TYPE, "ReachingDefAnalysis", false,
                 true)
 
-bool isValidReg(const MachineOperand &MO) {
+static bool isValidReg(const MachineOperand &MO) {
   return MO.isReg() && MO.getReg();
 }
 
-bool isValidRegUse(const MachineOperand &MO) {
+static bool isValidRegUse(const MachineOperand &MO) {
   return isValidReg(MO) && MO.isUse();
 }
 
-bool isValidRegUseOf(const MachineOperand &MO, int PhysReg) {
+static bool isValidRegUseOf(const MachineOperand &MO, int PhysReg) {
   return isValidRegUse(MO) && MO.getReg() == PhysReg;
 }
 
-bool isValidRegDef(const MachineOperand &MO) {
+static bool isValidRegDef(const MachineOperand &MO) {
   return isValidReg(MO) && MO.isDef();
 }
 
-bool isValidRegDefOf(const MachineOperand &MO, int PhysReg) {
+static bool isValidRegDefOf(const MachineOperand &MO, int PhysReg) {
   return isValidRegDef(MO) && MO.getReg() == PhysReg;
 }
 

llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp

@@ -441,7 +441,7 @@ const uint8_t MachO_x86_64_GOTAndStubsBuilder::StubContent[6] = {
     0xFF, 0x25, 0x00, 0x00, 0x00, 0x00};
 } // namespace
 
-Error optimizeMachO_x86_64_GOTAndStubs(LinkGraph &G) {
+static Error optimizeMachO_x86_64_GOTAndStubs(LinkGraph &G) {
   LLVM_DEBUG(dbgs() << "Optimizing GOT entries and stubs:\n");
 
   for (auto *B : G.blocks())

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

@@ -26,7 +26,7 @@ struct TypesAndMemOps {
 
 // Assumes power of 2 memory size. Subtargets that have only naturally-aligned
 // memory access need to perform additional legalization here.
-bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) {
+static bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) {
   assert(isPowerOf2_64(MemSize) && "Expected power of 2 memory size");
   assert(isPowerOf2_64(AlignInBits) && "Expected power of 2 align");
   if (MemSize > AlignInBits)

llvm/lib/Transforms/Scalar/DivRemPairs.cpp

@@ -71,6 +71,7 @@ static llvm::Optional<ExpandedMatch> matchExpandedRem(Instruction &I) {
   return M;
 }
 
+namespace {
 /// A thin wrapper to store two values that we matched as div-rem pair.
 /// We want this extra indirection to avoid dealing with RAUW'ing the map keys.
 struct DivRemPairWorklistEntry {
@@ -111,6 +112,7 @@ struct DivRemPairWorklistEntry {
     }
   }
 };
+} // namespace
 using DivRemWorklistTy = SmallVector<DivRemPairWorklistEntry, 4>;
 
 /// Find matching pairs of integer div/rem ops (they have the same numerator,

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

@@ -3228,10 +3228,9 @@ bool BoUpSLP::areAllUsersVectorized(Instruction *I) const {
          });
 }
 
-std::pair<unsigned, unsigned> getVectorCallCosts(CallInst *CI,
-                                                 VectorType *VecTy,
-                                                 TargetTransformInfo *TTI,
-                                                 TargetLibraryInfo *TLI) {
+static std::pair<unsigned, unsigned>
+getVectorCallCosts(CallInst *CI, VectorType *VecTy, TargetTransformInfo *TTI,
+                   TargetLibraryInfo *TLI) {
   Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI);
 
   // Calculate the cost of the scalar and vector calls.

mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp

@@ -414,7 +414,7 @@ Optional<TiledLinalgOp> static tileLinalgOpImpl(OpBuilder &b, LinalgOp op,
 }
 
 template <typename LoopTy>
-Optional<TiledLinalgOp>
+static Optional<TiledLinalgOp>
 tileLinalgOpImpl(OpBuilder &b, LinalgOp op, ArrayRef<int64_t> tileSizes,
                  ArrayRef<unsigned> permutation, OperationFolder *folder) {
   assert(op.hasBufferSemantics() && "expected linalg op with buffer semantics");

mlir/lib/Dialect/LoopOps/Transforms/ParallelLoopFusion.cpp

@@ -46,13 +46,6 @@ static bool equalIterationSpaces(ParallelOp firstPloop,
          matchOperands(firstPloop.step(), secondPloop.step());
 }
 
-/// Returns true if the defining operation for the memref is inside the body
-/// of parallel loop.
-bool isDefinedInPloopBody(Value memref, ParallelOp ploop) {
-  auto *memrefDef = memref.getDefiningOp();
-  return memrefDef && ploop.getOperation()->isAncestor(memrefDef);
-}
-
 /// Checks if the parallel loops have mixed access to the same buffers. Returns
 /// `true` if the first parallel loop writes to the same indices that the second
 /// loop reads.