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[X86][AVX] Remove LowerCTTZ's AVX1 custom vector handling.

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We can now rely on generic expansion to handle this.

llvm-svn: 361038
This commit is contained in:
Simon Pilgrim 2019-05-17 14:37:19 +00:00
parent 8369a9beb7
commit 279314e81b
1 changed files with 0 additions and 7 deletions
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7
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -1190,9 +1190,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::CTPOP, VT, Custom);
setOperationAction(ISD::CTLZ, VT, Custom);
// TODO - remove this once 256-bit X86ISD::ANDNP correctly split.
setOperationAction(ISD::CTTZ, VT, HasInt256 ? Expand : Custom);
// The condition codes aren't legal in SSE/AVX and under AVX512 we use
// setcc all the way to isel and prefer SETGT in some isel patterns.
setCondCodeAction(ISD::SETLT, VT, Custom);
@ -24018,10 +24015,6 @@ static SDValue LowerCTTZ(SDValue Op, const X86Subtarget &Subtarget,
SDValue N0 = Op.getOperand(0);
SDLoc dl(Op);
// Decompose 256-bit ops into smaller 128-bit ops.
if (VT.is256BitVector() && !Subtarget.hasInt256())
return Lower256IntUnary(Op, DAG);
assert(!VT.isVector() && Op.getOpcode() == ISD::CTTZ &&
"Only scalar CTTZ requires custom lowering");